1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/pm_qos.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
28 #include <linux/pm_runtime.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
32 #include "cqhci.h"
33
34 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
35 #define ESDHC_CTRL_D3CD 0x08
36 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
37 /* VENDOR SPEC register */
38 #define ESDHC_VENDOR_SPEC 0xc0
39 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
40 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
41 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
42 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
43 #define ESDHC_DEBUG_SEL_REG 0xc3
44 #define ESDHC_DEBUG_SEL_MASK 0xf
45 #define ESDHC_DEBUG_SEL_CMD_STATE 1
46 #define ESDHC_DEBUG_SEL_DATA_STATE 2
47 #define ESDHC_DEBUG_SEL_TRANS_STATE 3
48 #define ESDHC_DEBUG_SEL_DMA_STATE 4
49 #define ESDHC_DEBUG_SEL_ADMA_STATE 5
50 #define ESDHC_DEBUG_SEL_FIFO_STATE 6
51 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
52 #define ESDHC_WTMK_LVL 0x44
53 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
54 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
55 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
56 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
57 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
58 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
59 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
60 #define ESDHC_MIX_CTRL 0x48
61 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
62 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
63 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
64 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
65 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
66 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
67 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
68 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
69 /* Bits 3 and 6 are not SDHCI standard definitions */
70 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
71 /* Tuning bits */
72 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
73
74 /* dll control register */
75 #define ESDHC_DLL_CTRL 0x60
76 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
77 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
78
79 /* tune control register */
80 #define ESDHC_TUNE_CTRL_STATUS 0x68
81 #define ESDHC_TUNE_CTRL_STEP 1
82 #define ESDHC_TUNE_CTRL_MIN 0
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
84
85 /* strobe dll register */
86 #define ESDHC_STROBE_DLL_CTRL 0x70
87 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
88 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
90 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
91 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
92
93 #define ESDHC_STROBE_DLL_STATUS 0x74
94 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
95 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
96
97 #define ESDHC_VEND_SPEC2 0xc8
98 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
99
100 #define ESDHC_TUNING_CTRL 0xcc
101 #define ESDHC_STD_TUNING_EN (1 << 24)
102 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
103 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
104 #define ESDHC_TUNING_START_TAP_MASK 0x7f
105 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
106 #define ESDHC_TUNING_STEP_MASK 0x00070000
107 #define ESDHC_TUNING_STEP_SHIFT 16
108
109 /* pinctrl state */
110 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
111 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
112
113 /*
114 * Our interpretation of the SDHCI_HOST_CONTROL register
115 */
116 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
117 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
118 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
119
120 /*
121 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
122 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
123 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
124 * Define this macro DMA error INT for fsl eSDHC
125 */
126 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
127
128 /* the address offset of CQHCI */
129 #define ESDHC_CQHCI_ADDR_OFFSET 0x100
130
131 /*
132 * The CMDTYPE of the CMD register (offset 0xE) should be set to
133 * "11" when the STOP CMD12 is issued on imx53 to abort one
134 * open ended multi-blk IO. Otherwise the TC INT wouldn't
135 * be generated.
136 * In exact block transfer, the controller doesn't complete the
137 * operations automatically as required at the end of the
138 * transfer and remains on hold if the abort command is not sent.
139 * As a result, the TC flag is not asserted and SW received timeout
140 * exception. Bit1 of Vendor Spec register is used to fix it.
141 */
142 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
143 /*
144 * The flag tells that the ESDHC controller is an USDHC block that is
145 * integrated on the i.MX6 series.
146 */
147 #define ESDHC_FLAG_USDHC BIT(3)
148 /* The IP supports manual tuning process */
149 #define ESDHC_FLAG_MAN_TUNING BIT(4)
150 /* The IP supports standard tuning process */
151 #define ESDHC_FLAG_STD_TUNING BIT(5)
152 /* The IP has SDHCI_CAPABILITIES_1 register */
153 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
154 /*
155 * The IP has erratum ERR004536
156 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
157 * when reading data from the card
158 * This flag is also set for i.MX25 and i.MX35 in order to get
159 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
160 */
161 #define ESDHC_FLAG_ERR004536 BIT(7)
162 /* The IP supports HS200 mode */
163 #define ESDHC_FLAG_HS200 BIT(8)
164 /* The IP supports HS400 mode */
165 #define ESDHC_FLAG_HS400 BIT(9)
166 /*
167 * The IP has errata ERR010450
168 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
169 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
170 */
171 #define ESDHC_FLAG_ERR010450 BIT(10)
172 /* The IP supports HS400ES mode */
173 #define ESDHC_FLAG_HS400_ES BIT(11)
174 /* The IP has Host Controller Interface for Command Queuing */
175 #define ESDHC_FLAG_CQHCI BIT(12)
176 /* need request pmqos during low power */
177 #define ESDHC_FLAG_PMQOS BIT(13)
178 /* The IP state got lost in low power mode */
179 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
180 /* The IP lost clock rate in PM_RUNTIME */
181 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
182 /*
183 * The IP do not support the ACMD23 feature completely when use ADMA mode.
184 * In ADMA mode, it only use the 16 bit block count of the register 0x4
185 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
186 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
187 * write operation in RPMB, because RPMB reliable write need to set the bit31
188 * of the CMD23's argument.
189 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
190 * do not has this limitation. so when these SoC use ADMA mode, it need to
191 * disable the ACMD23 feature.
192 */
193 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
194
195 struct esdhc_soc_data {
196 u32 flags;
197 };
198
199 static const struct esdhc_soc_data esdhc_imx25_data = {
200 .flags = ESDHC_FLAG_ERR004536,
201 };
202
203 static const struct esdhc_soc_data esdhc_imx35_data = {
204 .flags = ESDHC_FLAG_ERR004536,
205 };
206
207 static const struct esdhc_soc_data esdhc_imx51_data = {
208 .flags = 0,
209 };
210
211 static const struct esdhc_soc_data esdhc_imx53_data = {
212 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
213 };
214
215 static const struct esdhc_soc_data usdhc_imx6q_data = {
216 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
217 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
218 };
219
220 static const struct esdhc_soc_data usdhc_imx6sl_data = {
221 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
222 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
223 | ESDHC_FLAG_HS200
224 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
225 };
226
227 static const struct esdhc_soc_data usdhc_imx6sll_data = {
228 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
229 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
230 | ESDHC_FLAG_HS400
231 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
232 };
233
234 static const struct esdhc_soc_data usdhc_imx6sx_data = {
235 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
236 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
237 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
238 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
239 };
240
241 static const struct esdhc_soc_data usdhc_imx6ull_data = {
242 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
243 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
244 | ESDHC_FLAG_ERR010450
245 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
246 };
247
248 static const struct esdhc_soc_data usdhc_imx7d_data = {
249 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
250 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
251 | ESDHC_FLAG_HS400
252 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
253 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
254 };
255
256 static struct esdhc_soc_data usdhc_imx7ulp_data = {
257 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
258 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
259 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
260 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
261 };
262
263 static struct esdhc_soc_data usdhc_imx8qxp_data = {
264 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
265 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
266 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
267 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
268 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
269 };
270
271 static struct esdhc_soc_data usdhc_imx8mm_data = {
272 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
273 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
274 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
275 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
276 };
277
278 struct pltfm_imx_data {
279 u32 scratchpad;
280 struct pinctrl *pinctrl;
281 struct pinctrl_state *pins_100mhz;
282 struct pinctrl_state *pins_200mhz;
283 const struct esdhc_soc_data *socdata;
284 struct esdhc_platform_data boarddata;
285 struct clk *clk_ipg;
286 struct clk *clk_ahb;
287 struct clk *clk_per;
288 unsigned int actual_clock;
289 enum {
290 NO_CMD_PENDING, /* no multiblock command pending */
291 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
292 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
293 } multiblock_status;
294 u32 is_ddr;
295 struct pm_qos_request pm_qos_req;
296 };
297
298 static const struct of_device_id imx_esdhc_dt_ids[] = {
299 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
300 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
301 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
302 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
303 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
304 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
305 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
306 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
307 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
308 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
309 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
310 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
311 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
312 { /* sentinel */ }
313 };
314 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
315
is_imx25_esdhc(struct pltfm_imx_data * data)316 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
317 {
318 return data->socdata == &esdhc_imx25_data;
319 }
320
is_imx53_esdhc(struct pltfm_imx_data * data)321 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
322 {
323 return data->socdata == &esdhc_imx53_data;
324 }
325
is_imx6q_usdhc(struct pltfm_imx_data * data)326 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
327 {
328 return data->socdata == &usdhc_imx6q_data;
329 }
330
esdhc_is_usdhc(struct pltfm_imx_data * data)331 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
332 {
333 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
334 }
335
esdhc_clrset_le(struct sdhci_host * host,u32 mask,u32 val,int reg)336 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
337 {
338 void __iomem *base = host->ioaddr + (reg & ~0x3);
339 u32 shift = (reg & 0x3) * 8;
340
341 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
342 }
343
344 #define DRIVER_NAME "sdhci-esdhc-imx"
345 #define ESDHC_IMX_DUMP(f, x...) \
346 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
esdhc_dump_debug_regs(struct sdhci_host * host)347 static void esdhc_dump_debug_regs(struct sdhci_host *host)
348 {
349 int i;
350 char *debug_status[7] = {
351 "cmd debug status",
352 "data debug status",
353 "trans debug status",
354 "dma debug status",
355 "adma debug status",
356 "fifo debug status",
357 "async fifo debug status"
358 };
359
360 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
361 for (i = 0; i < 7; i++) {
362 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
363 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
364 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
365 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
366 }
367
368 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
369
370 }
371
esdhc_wait_for_card_clock_gate_off(struct sdhci_host * host)372 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
373 {
374 u32 present_state;
375 int ret;
376
377 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
378 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
379 if (ret == -ETIMEDOUT)
380 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
381 }
382
esdhc_readl_le(struct sdhci_host * host,int reg)383 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
384 {
385 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
386 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
387 u32 val = readl(host->ioaddr + reg);
388
389 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
390 u32 fsl_prss = val;
391 /* save the least 20 bits */
392 val = fsl_prss & 0x000FFFFF;
393 /* move dat[0-3] bits */
394 val |= (fsl_prss & 0x0F000000) >> 4;
395 /* move cmd line bit */
396 val |= (fsl_prss & 0x00800000) << 1;
397 }
398
399 if (unlikely(reg == SDHCI_CAPABILITIES)) {
400 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
401 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
402 val &= 0xffff0000;
403
404 /* In FSL esdhc IC module, only bit20 is used to indicate the
405 * ADMA2 capability of esdhc, but this bit is messed up on
406 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
407 * don't actually support ADMA2). So set the BROKEN_ADMA
408 * quirk on MX25/35 platforms.
409 */
410
411 if (val & SDHCI_CAN_DO_ADMA1) {
412 val &= ~SDHCI_CAN_DO_ADMA1;
413 val |= SDHCI_CAN_DO_ADMA2;
414 }
415 }
416
417 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
418 if (esdhc_is_usdhc(imx_data)) {
419 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
420 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
421 else
422 /* imx6q/dl does not have cap_1 register, fake one */
423 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
424 | SDHCI_SUPPORT_SDR50
425 | SDHCI_USE_SDR50_TUNING
426 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
427 SDHCI_TUNING_MODE_3);
428
429 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
430 val |= SDHCI_SUPPORT_HS400;
431
432 /*
433 * Do not advertise faster UHS modes if there are no
434 * pinctrl states for 100MHz/200MHz.
435 */
436 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
437 IS_ERR_OR_NULL(imx_data->pins_200mhz))
438 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
439 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
440 }
441 }
442
443 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
444 val = 0;
445 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
446 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
447 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
448 }
449
450 if (unlikely(reg == SDHCI_INT_STATUS)) {
451 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
452 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
453 val |= SDHCI_INT_ADMA_ERROR;
454 }
455
456 /*
457 * mask off the interrupt we get in response to the manually
458 * sent CMD12
459 */
460 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
461 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
462 val &= ~SDHCI_INT_RESPONSE;
463 writel(SDHCI_INT_RESPONSE, host->ioaddr +
464 SDHCI_INT_STATUS);
465 imx_data->multiblock_status = NO_CMD_PENDING;
466 }
467 }
468
469 return val;
470 }
471
esdhc_writel_le(struct sdhci_host * host,u32 val,int reg)472 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
473 {
474 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
475 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
476 u32 data;
477
478 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
479 reg == SDHCI_INT_STATUS)) {
480 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
481 /*
482 * Clear and then set D3CD bit to avoid missing the
483 * card interrupt. This is an eSDHC controller problem
484 * so we need to apply the following workaround: clear
485 * and set D3CD bit will make eSDHC re-sample the card
486 * interrupt. In case a card interrupt was lost,
487 * re-sample it by the following steps.
488 */
489 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
490 data &= ~ESDHC_CTRL_D3CD;
491 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
492 data |= ESDHC_CTRL_D3CD;
493 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
494 }
495
496 if (val & SDHCI_INT_ADMA_ERROR) {
497 val &= ~SDHCI_INT_ADMA_ERROR;
498 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
499 }
500 }
501
502 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
503 && (reg == SDHCI_INT_STATUS)
504 && (val & SDHCI_INT_DATA_END))) {
505 u32 v;
506 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
507 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
508 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
509
510 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
511 {
512 /* send a manual CMD12 with RESPTYP=none */
513 data = MMC_STOP_TRANSMISSION << 24 |
514 SDHCI_CMD_ABORTCMD << 16;
515 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
516 imx_data->multiblock_status = WAIT_FOR_INT;
517 }
518 }
519
520 writel(val, host->ioaddr + reg);
521 }
522
esdhc_readw_le(struct sdhci_host * host,int reg)523 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
524 {
525 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
526 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
527 u16 ret = 0;
528 u32 val;
529
530 if (unlikely(reg == SDHCI_HOST_VERSION)) {
531 reg ^= 2;
532 if (esdhc_is_usdhc(imx_data)) {
533 /*
534 * The usdhc register returns a wrong host version.
535 * Correct it here.
536 */
537 return SDHCI_SPEC_300;
538 }
539 }
540
541 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
542 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
543 if (val & ESDHC_VENDOR_SPEC_VSELECT)
544 ret |= SDHCI_CTRL_VDD_180;
545
546 if (esdhc_is_usdhc(imx_data)) {
547 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
548 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
549 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
550 /* the std tuning bits is in ACMD12_ERR for imx6sl */
551 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
552 }
553
554 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
555 ret |= SDHCI_CTRL_EXEC_TUNING;
556 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
557 ret |= SDHCI_CTRL_TUNED_CLK;
558
559 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
560
561 return ret;
562 }
563
564 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
565 if (esdhc_is_usdhc(imx_data)) {
566 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
567 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
568 /* Swap AC23 bit */
569 if (m & ESDHC_MIX_CTRL_AC23EN) {
570 ret &= ~ESDHC_MIX_CTRL_AC23EN;
571 ret |= SDHCI_TRNS_AUTO_CMD23;
572 }
573 } else {
574 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
575 }
576
577 return ret;
578 }
579
580 return readw(host->ioaddr + reg);
581 }
582
esdhc_writew_le(struct sdhci_host * host,u16 val,int reg)583 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
584 {
585 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
586 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
587 u32 new_val = 0;
588
589 switch (reg) {
590 case SDHCI_CLOCK_CONTROL:
591 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
592 if (val & SDHCI_CLOCK_CARD_EN)
593 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
594 else
595 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
596 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
597 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
598 esdhc_wait_for_card_clock_gate_off(host);
599 return;
600 case SDHCI_HOST_CONTROL2:
601 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
602 if (val & SDHCI_CTRL_VDD_180)
603 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
604 else
605 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
606 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
607 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
608 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
609 if (val & SDHCI_CTRL_TUNED_CLK) {
610 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
611 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
612 } else {
613 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
614 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
615 }
616 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
617 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
618 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
619 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
620 if (val & SDHCI_CTRL_TUNED_CLK) {
621 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
622 } else {
623 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
624 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
625 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
626 }
627
628 if (val & SDHCI_CTRL_EXEC_TUNING) {
629 v |= ESDHC_MIX_CTRL_EXE_TUNE;
630 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
631 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
632 } else {
633 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
634 }
635
636 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
637 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
638 }
639 return;
640 case SDHCI_TRANSFER_MODE:
641 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
642 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
643 && (host->cmd->data->blocks > 1)
644 && (host->cmd->data->flags & MMC_DATA_READ)) {
645 u32 v;
646 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
647 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
648 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
649 }
650
651 if (esdhc_is_usdhc(imx_data)) {
652 u32 wml;
653 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
654 /* Swap AC23 bit */
655 if (val & SDHCI_TRNS_AUTO_CMD23) {
656 val &= ~SDHCI_TRNS_AUTO_CMD23;
657 val |= ESDHC_MIX_CTRL_AC23EN;
658 }
659 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
660 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
661
662 /* Set watermark levels for PIO access to maximum value
663 * (128 words) to accommodate full 512 bytes buffer.
664 * For DMA access restore the levels to default value.
665 */
666 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
667 if (val & SDHCI_TRNS_DMA) {
668 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
669 } else {
670 u8 ctrl;
671 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
672
673 /*
674 * Since already disable DMA mode, so also need
675 * to clear the DMASEL. Otherwise, for standard
676 * tuning, when send tuning command, usdhc will
677 * still prefetch the ADMA script from wrong
678 * DMA address, then we will see IOMMU report
679 * some error which show lack of TLB mapping.
680 */
681 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
682 ctrl &= ~SDHCI_CTRL_DMA_MASK;
683 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
684 }
685 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
686 ESDHC_WTMK_LVL_WR_WML_MASK);
687 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
688 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
689 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
690 } else {
691 /*
692 * Postpone this write, we must do it together with a
693 * command write that is down below.
694 */
695 imx_data->scratchpad = val;
696 }
697 return;
698 case SDHCI_COMMAND:
699 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
700 val |= SDHCI_CMD_ABORTCMD;
701
702 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
703 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
704 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
705
706 if (esdhc_is_usdhc(imx_data))
707 writel(val << 16,
708 host->ioaddr + SDHCI_TRANSFER_MODE);
709 else
710 writel(val << 16 | imx_data->scratchpad,
711 host->ioaddr + SDHCI_TRANSFER_MODE);
712 return;
713 case SDHCI_BLOCK_SIZE:
714 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
715 break;
716 }
717 esdhc_clrset_le(host, 0xffff, val, reg);
718 }
719
esdhc_readb_le(struct sdhci_host * host,int reg)720 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
721 {
722 u8 ret;
723 u32 val;
724
725 switch (reg) {
726 case SDHCI_HOST_CONTROL:
727 val = readl(host->ioaddr + reg);
728
729 ret = val & SDHCI_CTRL_LED;
730 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
731 ret |= (val & ESDHC_CTRL_4BITBUS);
732 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
733 return ret;
734 }
735
736 return readb(host->ioaddr + reg);
737 }
738
esdhc_writeb_le(struct sdhci_host * host,u8 val,int reg)739 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
740 {
741 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
742 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
743 u32 new_val = 0;
744 u32 mask;
745
746 switch (reg) {
747 case SDHCI_POWER_CONTROL:
748 /*
749 * FSL put some DMA bits here
750 * If your board has a regulator, code should be here
751 */
752 return;
753 case SDHCI_HOST_CONTROL:
754 /* FSL messed up here, so we need to manually compose it. */
755 new_val = val & SDHCI_CTRL_LED;
756 /* ensure the endianness */
757 new_val |= ESDHC_HOST_CONTROL_LE;
758 /* bits 8&9 are reserved on mx25 */
759 if (!is_imx25_esdhc(imx_data)) {
760 /* DMA mode bits are shifted */
761 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
762 }
763
764 /*
765 * Do not touch buswidth bits here. This is done in
766 * esdhc_pltfm_bus_width.
767 * Do not touch the D3CD bit either which is used for the
768 * SDIO interrupt erratum workaround.
769 */
770 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
771
772 esdhc_clrset_le(host, mask, new_val, reg);
773 return;
774 case SDHCI_SOFTWARE_RESET:
775 if (val & SDHCI_RESET_DATA)
776 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
777 break;
778 }
779 esdhc_clrset_le(host, 0xff, val, reg);
780
781 if (reg == SDHCI_SOFTWARE_RESET) {
782 if (val & SDHCI_RESET_ALL) {
783 /*
784 * The esdhc has a design violation to SDHC spec which
785 * tells that software reset should not affect card
786 * detection circuit. But esdhc clears its SYSCTL
787 * register bits [0..2] during the software reset. This
788 * will stop those clocks that card detection circuit
789 * relies on. To work around it, we turn the clocks on
790 * back to keep card detection circuit functional.
791 */
792 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
793 /*
794 * The reset on usdhc fails to clear MIX_CTRL register.
795 * Do it manually here.
796 */
797 if (esdhc_is_usdhc(imx_data)) {
798 /*
799 * the tuning bits should be kept during reset
800 */
801 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
802 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
803 host->ioaddr + ESDHC_MIX_CTRL);
804 imx_data->is_ddr = 0;
805 }
806 } else if (val & SDHCI_RESET_DATA) {
807 /*
808 * The eSDHC DAT line software reset clears at least the
809 * data transfer width on i.MX25, so make sure that the
810 * Host Control register is unaffected.
811 */
812 esdhc_clrset_le(host, 0xff, new_val,
813 SDHCI_HOST_CONTROL);
814 }
815 }
816 }
817
esdhc_pltfm_get_max_clock(struct sdhci_host * host)818 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
819 {
820 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
821
822 return pltfm_host->clock;
823 }
824
esdhc_pltfm_get_min_clock(struct sdhci_host * host)825 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
826 {
827 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
828
829 return pltfm_host->clock / 256 / 16;
830 }
831
esdhc_pltfm_set_clock(struct sdhci_host * host,unsigned int clock)832 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
833 unsigned int clock)
834 {
835 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
836 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
837 unsigned int host_clock = pltfm_host->clock;
838 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
839 int pre_div = 1;
840 int div = 1;
841 int ret;
842 u32 temp, val;
843
844 if (esdhc_is_usdhc(imx_data)) {
845 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
846 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
847 host->ioaddr + ESDHC_VENDOR_SPEC);
848 esdhc_wait_for_card_clock_gate_off(host);
849 }
850
851 if (clock == 0) {
852 host->mmc->actual_clock = 0;
853 return;
854 }
855
856 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
857 if (is_imx53_esdhc(imx_data)) {
858 /*
859 * According to the i.MX53 reference manual, if DLLCTRL[10] can
860 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
861 */
862 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
863 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
864 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
865 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
866 if (temp & BIT(10))
867 pre_div = 2;
868 }
869
870 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
871 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
872 | ESDHC_CLOCK_MASK);
873 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
874
875 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
876 unsigned int max_clock;
877
878 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
879
880 clock = min(clock, max_clock);
881 }
882
883 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
884 pre_div < 256)
885 pre_div *= 2;
886
887 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
888 div++;
889
890 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
891 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
892 clock, host->mmc->actual_clock);
893
894 pre_div >>= 1;
895 div--;
896
897 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
898 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
899 | (div << ESDHC_DIVIDER_SHIFT)
900 | (pre_div << ESDHC_PREDIV_SHIFT));
901 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
902
903 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
904 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
905 (temp & ESDHC_CLOCK_STABLE), 2, 100);
906 if (ret == -ETIMEDOUT)
907 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
908
909 if (esdhc_is_usdhc(imx_data)) {
910 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
911 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
912 host->ioaddr + ESDHC_VENDOR_SPEC);
913 }
914
915 }
916
esdhc_pltfm_get_ro(struct sdhci_host * host)917 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
918 {
919 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
920 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
921 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
922
923 switch (boarddata->wp_type) {
924 case ESDHC_WP_GPIO:
925 return mmc_gpio_get_ro(host->mmc);
926 case ESDHC_WP_CONTROLLER:
927 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
928 SDHCI_WRITE_PROTECT);
929 case ESDHC_WP_NONE:
930 break;
931 }
932
933 return -ENOSYS;
934 }
935
esdhc_pltfm_set_bus_width(struct sdhci_host * host,int width)936 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
937 {
938 u32 ctrl;
939
940 switch (width) {
941 case MMC_BUS_WIDTH_8:
942 ctrl = ESDHC_CTRL_8BITBUS;
943 break;
944 case MMC_BUS_WIDTH_4:
945 ctrl = ESDHC_CTRL_4BITBUS;
946 break;
947 default:
948 ctrl = 0;
949 break;
950 }
951
952 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
953 SDHCI_HOST_CONTROL);
954 }
955
usdhc_execute_tuning(struct mmc_host * mmc,u32 opcode)956 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
957 {
958 struct sdhci_host *host = mmc_priv(mmc);
959
960 /*
961 * i.MX uSDHC internally already uses a fixed optimized timing for
962 * DDR50, normally does not require tuning for DDR50 mode.
963 */
964 if (host->timing == MMC_TIMING_UHS_DDR50)
965 return 0;
966
967 return sdhci_execute_tuning(mmc, opcode);
968 }
969
esdhc_prepare_tuning(struct sdhci_host * host,u32 val)970 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
971 {
972 u32 reg;
973 u8 sw_rst;
974 int ret;
975
976 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
977 mdelay(1);
978
979 /* IC suggest to reset USDHC before every tuning command */
980 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
981 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
982 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
983 if (ret == -ETIMEDOUT)
984 dev_warn(mmc_dev(host->mmc),
985 "warning! RESET_ALL never complete before sending tuning command\n");
986
987 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
988 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
989 ESDHC_MIX_CTRL_FBCLK_SEL;
990 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
991 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
992 dev_dbg(mmc_dev(host->mmc),
993 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
994 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
995 }
996
esdhc_post_tuning(struct sdhci_host * host)997 static void esdhc_post_tuning(struct sdhci_host *host)
998 {
999 u32 reg;
1000
1001 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1002 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1003 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1004 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1005 }
1006
esdhc_executing_tuning(struct sdhci_host * host,u32 opcode)1007 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1008 {
1009 int min, max, avg, ret;
1010
1011 /* find the mininum delay first which can pass tuning */
1012 min = ESDHC_TUNE_CTRL_MIN;
1013 while (min < ESDHC_TUNE_CTRL_MAX) {
1014 esdhc_prepare_tuning(host, min);
1015 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1016 break;
1017 min += ESDHC_TUNE_CTRL_STEP;
1018 }
1019
1020 /* find the maxinum delay which can not pass tuning */
1021 max = min + ESDHC_TUNE_CTRL_STEP;
1022 while (max < ESDHC_TUNE_CTRL_MAX) {
1023 esdhc_prepare_tuning(host, max);
1024 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1025 max -= ESDHC_TUNE_CTRL_STEP;
1026 break;
1027 }
1028 max += ESDHC_TUNE_CTRL_STEP;
1029 }
1030
1031 /* use average delay to get the best timing */
1032 avg = (min + max) / 2;
1033 esdhc_prepare_tuning(host, avg);
1034 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1035 esdhc_post_tuning(host);
1036
1037 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1038 ret ? "failed" : "passed", avg, ret);
1039
1040 return ret;
1041 }
1042
esdhc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)1043 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1044 {
1045 struct sdhci_host *host = mmc_priv(mmc);
1046 u32 m;
1047
1048 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1049 if (ios->enhanced_strobe)
1050 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1051 else
1052 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1053 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1054 }
1055
esdhc_change_pinstate(struct sdhci_host * host,unsigned int uhs)1056 static int esdhc_change_pinstate(struct sdhci_host *host,
1057 unsigned int uhs)
1058 {
1059 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1060 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1061 struct pinctrl_state *pinctrl;
1062
1063 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1064
1065 if (IS_ERR(imx_data->pinctrl) ||
1066 IS_ERR(imx_data->pins_100mhz) ||
1067 IS_ERR(imx_data->pins_200mhz))
1068 return -EINVAL;
1069
1070 switch (uhs) {
1071 case MMC_TIMING_UHS_SDR50:
1072 case MMC_TIMING_UHS_DDR50:
1073 pinctrl = imx_data->pins_100mhz;
1074 break;
1075 case MMC_TIMING_UHS_SDR104:
1076 case MMC_TIMING_MMC_HS200:
1077 case MMC_TIMING_MMC_HS400:
1078 pinctrl = imx_data->pins_200mhz;
1079 break;
1080 default:
1081 /* back to default state for other legacy timing */
1082 return pinctrl_select_default_state(mmc_dev(host->mmc));
1083 }
1084
1085 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1086 }
1087
1088 /*
1089 * For HS400 eMMC, there is a data_strobe line. This signal is generated
1090 * by the device and used for data output and CRC status response output
1091 * in HS400 mode. The frequency of this signal follows the frequency of
1092 * CLK generated by host. The host receives the data which is aligned to the
1093 * edge of data_strobe line. Due to the time delay between CLK line and
1094 * data_strobe line, if the delay time is larger than one clock cycle,
1095 * then CLK and data_strobe line will be misaligned, read error shows up.
1096 */
esdhc_set_strobe_dll(struct sdhci_host * host)1097 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1098 {
1099 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1100 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1101 u32 strobe_delay;
1102 u32 v;
1103 int ret;
1104
1105 /* disable clock before enabling strobe dll */
1106 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1107 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1108 host->ioaddr + ESDHC_VENDOR_SPEC);
1109 esdhc_wait_for_card_clock_gate_off(host);
1110
1111 /* force a reset on strobe dll */
1112 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1113 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1114 /* clear the reset bit on strobe dll before any setting */
1115 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1116
1117 /*
1118 * enable strobe dll ctrl and adjust the delay target
1119 * for the uSDHC loopback read clock
1120 */
1121 if (imx_data->boarddata.strobe_dll_delay_target)
1122 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1123 else
1124 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1125 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1126 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1127 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1128 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1129
1130 /* wait max 50us to get the REF/SLV lock */
1131 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1132 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1133 if (ret == -ETIMEDOUT)
1134 dev_warn(mmc_dev(host->mmc),
1135 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1136 }
1137
esdhc_reset_tuning(struct sdhci_host * host)1138 static void esdhc_reset_tuning(struct sdhci_host *host)
1139 {
1140 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1141 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1142 u32 ctrl;
1143 int ret;
1144
1145 /* Reset the tuning circuit */
1146 if (esdhc_is_usdhc(imx_data)) {
1147 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1148 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1149 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1150 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1151 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1152 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1153 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1154 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1155 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1156 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1157 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1158 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1159 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1160 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1161 if (ret == -ETIMEDOUT)
1162 dev_warn(mmc_dev(host->mmc),
1163 "Warning! clear execute tuning bit failed\n");
1164 /*
1165 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1166 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1167 * will finally make sure the normal data transfer logic correct.
1168 */
1169 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1170 ctrl |= SDHCI_INT_DATA_AVAIL;
1171 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1172 }
1173 }
1174 }
1175
esdhc_set_uhs_signaling(struct sdhci_host * host,unsigned timing)1176 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1177 {
1178 u32 m;
1179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1180 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1181 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1182
1183 /* disable ddr mode and disable HS400 mode */
1184 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1185 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1186 imx_data->is_ddr = 0;
1187
1188 switch (timing) {
1189 case MMC_TIMING_UHS_SDR12:
1190 case MMC_TIMING_UHS_SDR25:
1191 case MMC_TIMING_UHS_SDR50:
1192 case MMC_TIMING_UHS_SDR104:
1193 case MMC_TIMING_MMC_HS:
1194 case MMC_TIMING_MMC_HS200:
1195 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1196 break;
1197 case MMC_TIMING_UHS_DDR50:
1198 case MMC_TIMING_MMC_DDR52:
1199 m |= ESDHC_MIX_CTRL_DDREN;
1200 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1201 imx_data->is_ddr = 1;
1202 if (boarddata->delay_line) {
1203 u32 v;
1204 v = boarddata->delay_line <<
1205 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1206 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1207 if (is_imx53_esdhc(imx_data))
1208 v <<= 1;
1209 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1210 }
1211 break;
1212 case MMC_TIMING_MMC_HS400:
1213 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1214 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1215 imx_data->is_ddr = 1;
1216 /* update clock after enable DDR for strobe DLL lock */
1217 host->ops->set_clock(host, host->clock);
1218 esdhc_set_strobe_dll(host);
1219 break;
1220 case MMC_TIMING_LEGACY:
1221 default:
1222 esdhc_reset_tuning(host);
1223 break;
1224 }
1225
1226 esdhc_change_pinstate(host, timing);
1227 }
1228
esdhc_reset(struct sdhci_host * host,u8 mask)1229 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1230 {
1231 sdhci_and_cqhci_reset(host, mask);
1232
1233 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1234 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1235 }
1236
esdhc_get_max_timeout_count(struct sdhci_host * host)1237 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1238 {
1239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1240 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1241
1242 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1243 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1244 }
1245
esdhc_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1246 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1247 {
1248 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1249 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1250
1251 /* use maximum timeout counter */
1252 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1253 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1254 SDHCI_TIMEOUT_CONTROL);
1255 }
1256
esdhc_cqhci_irq(struct sdhci_host * host,u32 intmask)1257 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1258 {
1259 int cmd_error = 0;
1260 int data_error = 0;
1261
1262 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1263 return intmask;
1264
1265 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1266
1267 return 0;
1268 }
1269
1270 static struct sdhci_ops sdhci_esdhc_ops = {
1271 .read_l = esdhc_readl_le,
1272 .read_w = esdhc_readw_le,
1273 .read_b = esdhc_readb_le,
1274 .write_l = esdhc_writel_le,
1275 .write_w = esdhc_writew_le,
1276 .write_b = esdhc_writeb_le,
1277 .set_clock = esdhc_pltfm_set_clock,
1278 .get_max_clock = esdhc_pltfm_get_max_clock,
1279 .get_min_clock = esdhc_pltfm_get_min_clock,
1280 .get_max_timeout_count = esdhc_get_max_timeout_count,
1281 .get_ro = esdhc_pltfm_get_ro,
1282 .set_timeout = esdhc_set_timeout,
1283 .set_bus_width = esdhc_pltfm_set_bus_width,
1284 .set_uhs_signaling = esdhc_set_uhs_signaling,
1285 .reset = esdhc_reset,
1286 .irq = esdhc_cqhci_irq,
1287 .dump_vendor_regs = esdhc_dump_debug_regs,
1288 };
1289
1290 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1291 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1292 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1293 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1294 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1295 .ops = &sdhci_esdhc_ops,
1296 };
1297
sdhci_esdhc_imx_hwinit(struct sdhci_host * host)1298 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1299 {
1300 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1301 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1302 struct cqhci_host *cq_host = host->mmc->cqe_private;
1303 int tmp;
1304
1305 if (esdhc_is_usdhc(imx_data)) {
1306 /*
1307 * The imx6q ROM code will change the default watermark
1308 * level setting to something insane. Change it back here.
1309 */
1310 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1311
1312 /*
1313 * ROM code will change the bit burst_length_enable setting
1314 * to zero if this usdhc is chosen to boot system. Change
1315 * it back here, otherwise it will impact the performance a
1316 * lot. This bit is used to enable/disable the burst length
1317 * for the external AHB2AXI bridge. It's useful especially
1318 * for INCR transfer because without burst length indicator,
1319 * the AHB2AXI bridge does not know the burst length in
1320 * advance. And without burst length indicator, AHB INCR
1321 * transfer can only be converted to singles on the AXI side.
1322 */
1323 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1324 | ESDHC_BURST_LEN_EN_INCR,
1325 host->ioaddr + SDHCI_HOST_CONTROL);
1326
1327 /*
1328 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1329 * TO1.1, it's harmless for MX6SL
1330 */
1331 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1332 host->ioaddr + 0x6c);
1333
1334 /* disable DLL_CTRL delay line settings */
1335 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1336
1337 /*
1338 * For the case of command with busy, if set the bit
1339 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1340 * transfer complete interrupt when busy is deasserted.
1341 * When CQHCI use DCMD to send a CMD need R1b respons,
1342 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1343 * otherwise DCMD will always meet timeout waiting for
1344 * hardware interrupt issue.
1345 */
1346 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1347 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1348 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1349 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1350
1351 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1352 }
1353
1354 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1355 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1356 tmp |= ESDHC_STD_TUNING_EN |
1357 ESDHC_TUNING_START_TAP_DEFAULT;
1358 if (imx_data->boarddata.tuning_start_tap) {
1359 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1360 tmp |= imx_data->boarddata.tuning_start_tap;
1361 }
1362
1363 if (imx_data->boarddata.tuning_step) {
1364 tmp &= ~ESDHC_TUNING_STEP_MASK;
1365 tmp |= imx_data->boarddata.tuning_step
1366 << ESDHC_TUNING_STEP_SHIFT;
1367 }
1368
1369 /* Disable the CMD CRC check for tuning, if not, need to
1370 * add some delay after every tuning command, because
1371 * hardware standard tuning logic will directly go to next
1372 * step once it detect the CMD CRC error, will not wait for
1373 * the card side to finally send out the tuning data, trigger
1374 * the buffer read ready interrupt immediately. If usdhc send
1375 * the next tuning command some eMMC card will stuck, can't
1376 * response, block the tuning procedure or the first command
1377 * after the whole tuning procedure always can't get any response.
1378 */
1379 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1380 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1381 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1382 /*
1383 * ESDHC_STD_TUNING_EN may be configed in bootloader
1384 * or ROM code, so clear this bit here to make sure
1385 * the manual tuning can work.
1386 */
1387 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1388 tmp &= ~ESDHC_STD_TUNING_EN;
1389 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1390 }
1391
1392 /*
1393 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1394 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1395 * the 1st linux configure power/clock for the 2nd Linux.
1396 *
1397 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1398 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1399 * After we clear the pending interrupt and halt CQCTL, issue gone.
1400 */
1401 if (cq_host) {
1402 tmp = cqhci_readl(cq_host, CQHCI_IS);
1403 cqhci_writel(cq_host, tmp, CQHCI_IS);
1404 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1405 }
1406 }
1407 }
1408
esdhc_cqe_enable(struct mmc_host * mmc)1409 static void esdhc_cqe_enable(struct mmc_host *mmc)
1410 {
1411 struct sdhci_host *host = mmc_priv(mmc);
1412 struct cqhci_host *cq_host = mmc->cqe_private;
1413 u32 reg;
1414 u16 mode;
1415 int count = 10;
1416
1417 /*
1418 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1419 * the case after tuning, so ensure the buffer is drained.
1420 */
1421 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1422 while (reg & SDHCI_DATA_AVAILABLE) {
1423 sdhci_readl(host, SDHCI_BUFFER);
1424 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1425 if (count-- == 0) {
1426 dev_warn(mmc_dev(host->mmc),
1427 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1428 break;
1429 }
1430 mdelay(1);
1431 }
1432
1433 /*
1434 * Runtime resume will reset the entire host controller, which
1435 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1436 * Here set DMAEN and BCEN when enable CMDQ.
1437 */
1438 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1439 if (host->flags & SDHCI_REQ_USE_DMA)
1440 mode |= SDHCI_TRNS_DMA;
1441 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1442 mode |= SDHCI_TRNS_BLK_CNT_EN;
1443 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1444
1445 /*
1446 * Though Runtime resume reset the entire host controller,
1447 * but do not impact the CQHCI side, need to clear the
1448 * HALT bit, avoid CQHCI stuck in the first request when
1449 * system resume back.
1450 */
1451 cqhci_writel(cq_host, 0, CQHCI_CTL);
1452 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1453 dev_err(mmc_dev(host->mmc),
1454 "failed to exit halt state when enable CQE\n");
1455
1456
1457 sdhci_cqe_enable(mmc);
1458 }
1459
esdhc_sdhci_dumpregs(struct mmc_host * mmc)1460 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1461 {
1462 sdhci_dumpregs(mmc_priv(mmc));
1463 }
1464
1465 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1466 .enable = esdhc_cqe_enable,
1467 .disable = sdhci_cqe_disable,
1468 .dumpregs = esdhc_sdhci_dumpregs,
1469 };
1470
1471 #ifdef CONFIG_OF
1472 static int
sdhci_esdhc_imx_probe_dt(struct platform_device * pdev,struct sdhci_host * host,struct pltfm_imx_data * imx_data)1473 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1474 struct sdhci_host *host,
1475 struct pltfm_imx_data *imx_data)
1476 {
1477 struct device_node *np = pdev->dev.of_node;
1478 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1479 int ret;
1480
1481 if (of_get_property(np, "fsl,wp-controller", NULL))
1482 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1483
1484 /*
1485 * If we have this property, then activate WP check.
1486 * Retrieveing and requesting the actual WP GPIO will happen
1487 * in the call to mmc_of_parse().
1488 */
1489 if (of_property_read_bool(np, "wp-gpios"))
1490 boarddata->wp_type = ESDHC_WP_GPIO;
1491
1492 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1493 of_property_read_u32(np, "fsl,tuning-start-tap",
1494 &boarddata->tuning_start_tap);
1495
1496 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1497 &boarddata->strobe_dll_delay_target);
1498 if (of_find_property(np, "no-1-8-v", NULL))
1499 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1500
1501 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1502 boarddata->delay_line = 0;
1503
1504 mmc_of_parse_voltage(np, &host->ocr_mask);
1505
1506 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1507 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1508 ESDHC_PINCTRL_STATE_100MHZ);
1509 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1510 ESDHC_PINCTRL_STATE_200MHZ);
1511 }
1512
1513 /* call to generic mmc_of_parse to support additional capabilities */
1514 ret = mmc_of_parse(host->mmc);
1515 if (ret)
1516 return ret;
1517
1518 if (mmc_gpio_get_cd(host->mmc) >= 0)
1519 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1520
1521 return 0;
1522 }
1523 #else
1524 static inline int
sdhci_esdhc_imx_probe_dt(struct platform_device * pdev,struct sdhci_host * host,struct pltfm_imx_data * imx_data)1525 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1526 struct sdhci_host *host,
1527 struct pltfm_imx_data *imx_data)
1528 {
1529 return -ENODEV;
1530 }
1531 #endif
1532
sdhci_esdhc_imx_probe(struct platform_device * pdev)1533 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1534 {
1535 const struct of_device_id *of_id =
1536 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1537 struct sdhci_pltfm_host *pltfm_host;
1538 struct sdhci_host *host;
1539 struct cqhci_host *cq_host;
1540 int err;
1541 struct pltfm_imx_data *imx_data;
1542
1543 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1544 sizeof(*imx_data));
1545 if (IS_ERR(host))
1546 return PTR_ERR(host);
1547
1548 pltfm_host = sdhci_priv(host);
1549
1550 imx_data = sdhci_pltfm_priv(pltfm_host);
1551
1552 imx_data->socdata = of_id->data;
1553
1554 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1555 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1556
1557 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1558 if (IS_ERR(imx_data->clk_ipg)) {
1559 err = PTR_ERR(imx_data->clk_ipg);
1560 goto free_sdhci;
1561 }
1562
1563 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1564 if (IS_ERR(imx_data->clk_ahb)) {
1565 err = PTR_ERR(imx_data->clk_ahb);
1566 goto free_sdhci;
1567 }
1568
1569 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1570 if (IS_ERR(imx_data->clk_per)) {
1571 err = PTR_ERR(imx_data->clk_per);
1572 goto free_sdhci;
1573 }
1574
1575 pltfm_host->clk = imx_data->clk_per;
1576 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1577 err = clk_prepare_enable(imx_data->clk_per);
1578 if (err)
1579 goto free_sdhci;
1580 err = clk_prepare_enable(imx_data->clk_ipg);
1581 if (err)
1582 goto disable_per_clk;
1583 err = clk_prepare_enable(imx_data->clk_ahb);
1584 if (err)
1585 goto disable_ipg_clk;
1586
1587 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1588 if (IS_ERR(imx_data->pinctrl))
1589 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1590
1591 if (esdhc_is_usdhc(imx_data)) {
1592 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1593 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1594
1595 /* GPIO CD can be set as a wakeup source */
1596 host->mmc->caps |= MMC_CAP_CD_WAKE;
1597
1598 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1599 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1600
1601 /* clear tuning bits in case ROM has set it already */
1602 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1603 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1604 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1605
1606 /*
1607 * Link usdhc specific mmc_host_ops execute_tuning function,
1608 * to replace the standard one in sdhci_ops.
1609 */
1610 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1611 }
1612
1613 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1614 if (err)
1615 goto disable_ahb_clk;
1616
1617 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1618 sdhci_esdhc_ops.platform_execute_tuning =
1619 esdhc_executing_tuning;
1620
1621 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1622 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1623
1624 if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1625 imx_data->socdata->flags & ESDHC_FLAG_HS400)
1626 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1627
1628 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1629 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1630
1631 if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1632 imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1633 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1634 host->mmc_host_ops.hs400_enhanced_strobe =
1635 esdhc_hs400_enhanced_strobe;
1636 }
1637
1638 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1639 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1640 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1641 if (!cq_host) {
1642 err = -ENOMEM;
1643 goto disable_ahb_clk;
1644 }
1645
1646 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1647 cq_host->ops = &esdhc_cqhci_ops;
1648
1649 err = cqhci_init(cq_host, host->mmc, false);
1650 if (err)
1651 goto disable_ahb_clk;
1652 }
1653
1654 sdhci_esdhc_imx_hwinit(host);
1655
1656 err = sdhci_add_host(host);
1657 if (err)
1658 goto disable_ahb_clk;
1659
1660 pm_runtime_set_active(&pdev->dev);
1661 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1662 pm_runtime_use_autosuspend(&pdev->dev);
1663 pm_suspend_ignore_children(&pdev->dev, 1);
1664 pm_runtime_enable(&pdev->dev);
1665
1666 return 0;
1667
1668 disable_ahb_clk:
1669 clk_disable_unprepare(imx_data->clk_ahb);
1670 disable_ipg_clk:
1671 clk_disable_unprepare(imx_data->clk_ipg);
1672 disable_per_clk:
1673 clk_disable_unprepare(imx_data->clk_per);
1674 free_sdhci:
1675 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1676 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1677 sdhci_pltfm_free(pdev);
1678 return err;
1679 }
1680
sdhci_esdhc_imx_remove(struct platform_device * pdev)1681 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1682 {
1683 struct sdhci_host *host = platform_get_drvdata(pdev);
1684 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1685 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1686 int dead;
1687
1688 pm_runtime_get_sync(&pdev->dev);
1689 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1690 pm_runtime_disable(&pdev->dev);
1691 pm_runtime_put_noidle(&pdev->dev);
1692
1693 sdhci_remove_host(host, dead);
1694
1695 clk_disable_unprepare(imx_data->clk_per);
1696 clk_disable_unprepare(imx_data->clk_ipg);
1697 clk_disable_unprepare(imx_data->clk_ahb);
1698
1699 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1700 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1701
1702 sdhci_pltfm_free(pdev);
1703
1704 return 0;
1705 }
1706
1707 #ifdef CONFIG_PM_SLEEP
sdhci_esdhc_suspend(struct device * dev)1708 static int sdhci_esdhc_suspend(struct device *dev)
1709 {
1710 struct sdhci_host *host = dev_get_drvdata(dev);
1711 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1712 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1713 int ret;
1714
1715 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1716 ret = cqhci_suspend(host->mmc);
1717 if (ret)
1718 return ret;
1719 }
1720
1721 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1722 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1723 mmc_retune_timer_stop(host->mmc);
1724 mmc_retune_needed(host->mmc);
1725 }
1726
1727 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1728 mmc_retune_needed(host->mmc);
1729
1730 ret = sdhci_suspend_host(host);
1731 if (ret)
1732 return ret;
1733
1734 ret = pinctrl_pm_select_sleep_state(dev);
1735 if (ret)
1736 return ret;
1737
1738 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1739
1740 return ret;
1741 }
1742
sdhci_esdhc_resume(struct device * dev)1743 static int sdhci_esdhc_resume(struct device *dev)
1744 {
1745 struct sdhci_host *host = dev_get_drvdata(dev);
1746 int ret;
1747
1748 ret = pinctrl_pm_select_default_state(dev);
1749 if (ret)
1750 return ret;
1751
1752 /* re-initialize hw state in case it's lost in low power mode */
1753 sdhci_esdhc_imx_hwinit(host);
1754
1755 ret = sdhci_resume_host(host);
1756 if (ret)
1757 return ret;
1758
1759 if (host->mmc->caps2 & MMC_CAP2_CQE)
1760 ret = cqhci_resume(host->mmc);
1761
1762 if (!ret)
1763 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1764
1765 return ret;
1766 }
1767 #endif
1768
1769 #ifdef CONFIG_PM
sdhci_esdhc_runtime_suspend(struct device * dev)1770 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1771 {
1772 struct sdhci_host *host = dev_get_drvdata(dev);
1773 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1774 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1775 int ret;
1776
1777 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1778 ret = cqhci_suspend(host->mmc);
1779 if (ret)
1780 return ret;
1781 }
1782
1783 ret = sdhci_runtime_suspend_host(host);
1784 if (ret)
1785 return ret;
1786
1787 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1788 mmc_retune_needed(host->mmc);
1789
1790 imx_data->actual_clock = host->mmc->actual_clock;
1791 esdhc_pltfm_set_clock(host, 0);
1792 clk_disable_unprepare(imx_data->clk_per);
1793 clk_disable_unprepare(imx_data->clk_ipg);
1794 clk_disable_unprepare(imx_data->clk_ahb);
1795
1796 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1797 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1798
1799 return ret;
1800 }
1801
sdhci_esdhc_runtime_resume(struct device * dev)1802 static int sdhci_esdhc_runtime_resume(struct device *dev)
1803 {
1804 struct sdhci_host *host = dev_get_drvdata(dev);
1805 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1806 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1807 int err;
1808
1809 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1810 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1811
1812 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1813 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1814
1815 err = clk_prepare_enable(imx_data->clk_ahb);
1816 if (err)
1817 goto remove_pm_qos_request;
1818
1819 err = clk_prepare_enable(imx_data->clk_per);
1820 if (err)
1821 goto disable_ahb_clk;
1822
1823 err = clk_prepare_enable(imx_data->clk_ipg);
1824 if (err)
1825 goto disable_per_clk;
1826
1827 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1828
1829 err = sdhci_runtime_resume_host(host, 0);
1830 if (err)
1831 goto disable_ipg_clk;
1832
1833 if (host->mmc->caps2 & MMC_CAP2_CQE)
1834 err = cqhci_resume(host->mmc);
1835
1836 return err;
1837
1838 disable_ipg_clk:
1839 clk_disable_unprepare(imx_data->clk_ipg);
1840 disable_per_clk:
1841 clk_disable_unprepare(imx_data->clk_per);
1842 disable_ahb_clk:
1843 clk_disable_unprepare(imx_data->clk_ahb);
1844 remove_pm_qos_request:
1845 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1846 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1847 return err;
1848 }
1849 #endif
1850
1851 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1852 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1853 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1854 sdhci_esdhc_runtime_resume, NULL)
1855 };
1856
1857 static struct platform_driver sdhci_esdhc_imx_driver = {
1858 .driver = {
1859 .name = "sdhci-esdhc-imx",
1860 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1861 .of_match_table = imx_esdhc_dt_ids,
1862 .pm = &sdhci_esdhc_pmops,
1863 },
1864 .probe = sdhci_esdhc_imx_probe,
1865 .remove = sdhci_esdhc_imx_remove,
1866 };
1867
1868 module_platform_driver(sdhci_esdhc_imx_driver);
1869
1870 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1871 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1872 MODULE_LICENSE("GPL v2");
1873