1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SDHCI support for CNS3xxx SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2008 Cavium Networks
6*4882a593Smuzhiyun * Copyright 2010 MontaVista Software, LLC.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Authors: Scott Shu
9*4882a593Smuzhiyun * Anton Vorontsov <avorontsov@mvista.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/mmc/host.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include "sdhci-pltfm.h"
17*4882a593Smuzhiyun
sdhci_cns3xxx_get_max_clk(struct sdhci_host * host)18*4882a593Smuzhiyun static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun return 150000000;
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
sdhci_cns3xxx_set_clock(struct sdhci_host * host,unsigned int clock)23*4882a593Smuzhiyun static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct device *dev = mmc_dev(host->mmc);
26*4882a593Smuzhiyun int div = 1;
27*4882a593Smuzhiyun u16 clk;
28*4882a593Smuzhiyun unsigned long timeout;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun host->mmc->actual_clock = 0;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (clock == 0)
35*4882a593Smuzhiyun return;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun while (host->max_clk / div > clock) {
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * On CNS3xxx divider grows linearly up to 4, and then
40*4882a593Smuzhiyun * exponentially up to 256.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun if (div < 4)
43*4882a593Smuzhiyun div += 1;
44*4882a593Smuzhiyun else if (div < 256)
45*4882a593Smuzhiyun div *= 2;
46*4882a593Smuzhiyun else
47*4882a593Smuzhiyun break;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun dev_dbg(dev, "desired SD clock: %d, actual: %d\n",
51*4882a593Smuzhiyun clock, host->max_clk / div);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Divide by 3 is special. */
54*4882a593Smuzhiyun if (div != 3)
55*4882a593Smuzhiyun div >>= 1;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun clk = div << SDHCI_DIVIDER_SHIFT;
58*4882a593Smuzhiyun clk |= SDHCI_CLOCK_INT_EN;
59*4882a593Smuzhiyun sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun timeout = 20;
62*4882a593Smuzhiyun while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
63*4882a593Smuzhiyun & SDHCI_CLOCK_INT_STABLE)) {
64*4882a593Smuzhiyun if (timeout == 0) {
65*4882a593Smuzhiyun dev_warn(dev, "clock is unstable");
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun timeout--;
69*4882a593Smuzhiyun mdelay(1);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun clk |= SDHCI_CLOCK_CARD_EN;
73*4882a593Smuzhiyun sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct sdhci_ops sdhci_cns3xxx_ops = {
77*4882a593Smuzhiyun .get_max_clock = sdhci_cns3xxx_get_max_clk,
78*4882a593Smuzhiyun .set_clock = sdhci_cns3xxx_set_clock,
79*4882a593Smuzhiyun .set_bus_width = sdhci_set_bus_width,
80*4882a593Smuzhiyun .reset = sdhci_reset,
81*4882a593Smuzhiyun .set_uhs_signaling = sdhci_set_uhs_signaling,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
85*4882a593Smuzhiyun .ops = &sdhci_cns3xxx_ops,
86*4882a593Smuzhiyun .quirks = SDHCI_QUIRK_BROKEN_DMA |
87*4882a593Smuzhiyun SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
88*4882a593Smuzhiyun SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
89*4882a593Smuzhiyun SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
90*4882a593Smuzhiyun SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
sdhci_cns3xxx_probe(struct platform_device * pdev)93*4882a593Smuzhiyun static int sdhci_cns3xxx_probe(struct platform_device *pdev)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct platform_driver sdhci_cns3xxx_driver = {
99*4882a593Smuzhiyun .driver = {
100*4882a593Smuzhiyun .name = "sdhci-cns3xxx",
101*4882a593Smuzhiyun .probe_type = PROBE_PREFER_ASYNCHRONOUS,
102*4882a593Smuzhiyun .pm = &sdhci_pltfm_pmops,
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun .probe = sdhci_cns3xxx_probe,
105*4882a593Smuzhiyun .remove = sdhci_pltfm_unregister,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun module_platform_driver(sdhci_cns3xxx_driver);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun MODULE_DESCRIPTION("SDHCI driver for CNS3xxx");
111*4882a593Smuzhiyun MODULE_AUTHOR("Scott Shu, "
112*4882a593Smuzhiyun "Anton Vorontsov <avorontsov@mvista.com>");
113*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
114