1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _DW_MMC_ZX_H_ 3*4882a593Smuzhiyun #define _DW_MMC_ZX_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* ZX296718 SoC specific DLL register offset. */ 6*4882a593Smuzhiyun #define LB_AON_EMMC_CFG_REG0 0x1B0 7*4882a593Smuzhiyun #define LB_AON_EMMC_CFG_REG1 0x1B4 8*4882a593Smuzhiyun #define LB_AON_EMMC_CFG_REG2 0x1B8 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* LB_AON_EMMC_CFG_REG0 register defines */ 11*4882a593Smuzhiyun #define PARA_DLL_START(x) ((x) & 0xFF) 12*4882a593Smuzhiyun #define PARA_DLL_START_MASK 0xFF 13*4882a593Smuzhiyun #define DLL_REG_SET BIT(8) 14*4882a593Smuzhiyun #define PARA_DLL_LOCK_NUM(x) (((x) & 7) << 16) 15*4882a593Smuzhiyun #define PARA_DLL_LOCK_NUM_MASK (7 << 16) 16*4882a593Smuzhiyun #define PARA_PHASE_DET_SEL(x) (((x) & 7) << 20) 17*4882a593Smuzhiyun #define PARA_PHASE_DET_SEL_MASK (7 << 20) 18*4882a593Smuzhiyun #define PARA_DLL_BYPASS_MODE BIT(23) 19*4882a593Smuzhiyun #define PARA_HALF_CLK_MODE BIT(24) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* LB_AON_EMMC_CFG_REG1 register defines */ 22*4882a593Smuzhiyun #define READ_DQS_DELAY(x) ((x) & 0x7F) 23*4882a593Smuzhiyun #define READ_DQS_DELAY_MASK (0x7F) 24*4882a593Smuzhiyun #define READ_DQS_BYPASS_MODE BIT(7) 25*4882a593Smuzhiyun #define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8) 26*4882a593Smuzhiyun #define CLK_SAMP_DELAY_MASK (0x7F << 8) 27*4882a593Smuzhiyun #define CLK_SAMP_BYPASS_MODE BIT(15) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* LB_AON_EMMC_CFG_REG2 register defines */ 30*4882a593Smuzhiyun #define ZX_DLL_LOCKED BIT(2) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif /* _DW_MMC_ZX_H_ */ 33