1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DW_MMC_EXYNOS_H_ 9*4882a593Smuzhiyun #define _DW_MMC_EXYNOS_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SDMMC_CLKSEL 0x09C 12*4882a593Smuzhiyun #define SDMMC_CLKSEL64 0x0A8 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Extended Register's Offset */ 15*4882a593Smuzhiyun #define SDMMC_HS400_DQS_EN 0x180 16*4882a593Smuzhiyun #define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184 17*4882a593Smuzhiyun #define SDMMC_HS400_DLINE_CTRL 0x188 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* CLKSEL register defines */ 20*4882a593Smuzhiyun #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) 21*4882a593Smuzhiyun #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) 22*4882a593Smuzhiyun #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) 23*4882a593Smuzhiyun #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) 24*4882a593Smuzhiyun #define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7) 25*4882a593Smuzhiyun #define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\ 26*4882a593Smuzhiyun SDMMC_CLKSEL_CCLK_SAMPLE(y)) 27*4882a593Smuzhiyun #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ 28*4882a593Smuzhiyun SDMMC_CLKSEL_CCLK_DRIVE(y) | \ 29*4882a593Smuzhiyun SDMMC_CLKSEL_CCLK_DIVIDER(z)) 30*4882a593Smuzhiyun #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7) 31*4882a593Smuzhiyun #define SDMMC_CLKSEL_WAKEUP_INT BIT(11) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* RCLK_EN register defines */ 34*4882a593Smuzhiyun #define DATA_STROBE_EN BIT(0) 35*4882a593Smuzhiyun #define AXI_NON_BLOCKING_WR BIT(7) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* DLINE_CTRL register defines */ 38*4882a593Smuzhiyun #define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF)) 39*4882a593Smuzhiyun #define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Protector Register */ 42*4882a593Smuzhiyun #define SDMMC_EMMCP_BASE 0x1000 43*4882a593Smuzhiyun #define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) 44*4882a593Smuzhiyun #define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) 45*4882a593Smuzhiyun #define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) 46*4882a593Smuzhiyun #define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SMU control defines */ 49*4882a593Smuzhiyun #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) 50*4882a593Smuzhiyun #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) 51*4882a593Smuzhiyun #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) 52*4882a593Smuzhiyun #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) 53*4882a593Smuzhiyun #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) 54*4882a593Smuzhiyun #define SDMMC_MPSCTRL_ECB_MODE BIT(2) 55*4882a593Smuzhiyun #define SDMMC_MPSCTRL_ENCRYPTION BIT(1) 56*4882a593Smuzhiyun #define SDMMC_MPSCTRL_VALID BIT(0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Maximum number of Ending sector */ 59*4882a593Smuzhiyun #define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Fixed clock divider */ 62*4882a593Smuzhiyun #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 63*4882a593Smuzhiyun #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 64*4882a593Smuzhiyun #define HS400_FIXED_CIU_CLK_DIV 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Minimal required clock frequency for cclkin, unit: HZ */ 67*4882a593Smuzhiyun #define EXYNOS_CCLKIN_MIN 50000000 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* _DW_MMC_EXYNOS_H_ */ 70