1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7 #include "rk628.h"
8 #include "rk628_config.h"
9 #include "rk628_cru.h"
10
calc_dsp_frm_hst_vst(const struct rk628_display_mode * src,const struct rk628_display_mode * dst,u32 * dsp_frame_hst,u32 * dsp_frame_vst)11 static void calc_dsp_frm_hst_vst(const struct rk628_display_mode *src,
12 const struct rk628_display_mode *dst,
13 u32 *dsp_frame_hst,
14 u32 *dsp_frame_vst)
15 {
16 u32 bp_in, bp_out;
17 u32 v_scale_ratio;
18 u64 t_frm_st;
19 u64 t_bp_in, t_bp_out, t_delta, tin;
20 u32 src_pixclock, dst_pixclock;
21 u32 dst_htotal, dst_hsync_len, dst_hback_porch;
22 u32 dst_vsync_len, dst_vback_porch, dst_vactive;
23 u32 src_htotal, src_hsync_len, src_hback_porch;
24 u32 src_vtotal, src_vsync_len, src_vback_porch, src_vactive;
25 u32 rem;
26 u32 x;
27
28 src_pixclock = div_u64(1000000000llu, src->clock);
29 dst_pixclock = div_u64(1000000000llu, dst->clock);
30
31 src_hsync_len = src->hsync_end - src->hsync_start;
32 src_hback_porch = src->htotal - src->hsync_end;
33 src_htotal = src->htotal;
34 src_vsync_len = src->vsync_end - src->vsync_start;
35 src_vback_porch = src->vtotal - src->vsync_end;
36 src_vactive = src->vdisplay;
37 src_vtotal = src->vtotal;
38
39 dst_hsync_len = dst->hsync_end - dst->hsync_start;
40 dst_hback_porch = dst->htotal - dst->hsync_end;
41 dst_htotal = dst->htotal;
42 dst_vsync_len = dst->vsync_end - dst->vsync_start;
43 dst_vback_porch = dst->vtotal - dst->vsync_end;
44 dst_vactive = dst->vdisplay;
45
46 bp_in = (src_vback_porch + src_vsync_len) * src_htotal +
47 src_hsync_len + src_hback_porch;
48 bp_out = (dst_vback_porch + dst_vsync_len) * dst_htotal +
49 dst_hsync_len + dst_hback_porch;
50
51 t_bp_in = bp_in * src_pixclock;
52 t_bp_out = bp_out * dst_pixclock;
53 tin = src_vtotal * src_htotal * src_pixclock;
54
55 v_scale_ratio = src_vactive / dst_vactive;
56 x = 5;
57 __retry:
58 if (v_scale_ratio <= 2)
59 t_delta = x * src_htotal * src_pixclock;
60 else
61 t_delta = 12 * src_htotal * src_pixclock;
62
63 if (t_bp_in + t_delta > t_bp_out)
64 t_frm_st = (t_bp_in + t_delta - t_bp_out);
65 else
66 t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
67
68 do_div(t_frm_st, src_pixclock);
69 rem = do_div(t_frm_st, src_htotal);
70 if ((t_frm_st < 2 || t_frm_st > 14) && x < 12) {
71 x++;
72 goto __retry;
73 }
74 if (t_frm_st < 2 || t_frm_st > 14)
75 t_frm_st = 4;
76
77 *dsp_frame_hst = rem;
78 *dsp_frame_vst = t_frm_st;
79 }
80
rk628_post_process_scaler_init(struct rk628 * rk628,struct rk628_display_mode * src,const struct rk628_display_mode * dst)81 static void rk628_post_process_scaler_init(struct rk628 *rk628,
82 struct rk628_display_mode *src,
83 const struct rk628_display_mode *dst)
84 {
85 u32 dsp_frame_hst, dsp_frame_vst;
86 u32 scl_hor_mode, scl_ver_mode;
87 u32 scl_v_factor, scl_h_factor;
88 u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
89 u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
90 u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
91 u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
92 u8 hor_down_mode = 0, ver_down_mode = 0;
93 u32 dst_hsync_len, dst_hback_porch, dst_hfront_porch, dst_hactive;
94 u32 dst_vsync_len, dst_vback_porch, dst_vfront_porch, dst_vactive;
95 u32 src_hactive;
96 u32 src_vactive;
97
98 src_hactive = src->hdisplay;
99 src_vactive = src->vdisplay;
100
101 dst_hactive = dst->hdisplay;
102 dst_hsync_len = dst->hsync_end - dst->hsync_start;
103 dst_hback_porch = dst->htotal - dst->hsync_end;
104 dst_hfront_porch = dst->hsync_start - dst->hdisplay;
105 dst_vsync_len = dst->vsync_end - dst->vsync_start;
106 dst_vback_porch = dst->vtotal - dst->vsync_end;
107 dst_vfront_porch = dst->vsync_start - dst->vdisplay;
108 dst_vactive = dst->vdisplay;
109
110 dsp_htotal = dst_hsync_len + dst_hback_porch +
111 dst_hactive + dst_hfront_porch;
112 dsp_vtotal = dst_vsync_len + dst_vback_porch +
113 dst_vactive + dst_vfront_porch;
114 dsp_hs_end = dst_hsync_len;
115 dsp_vs_end = dst_vsync_len;
116 dsp_hbor_end = dst_hsync_len + dst_hback_porch + dst_hactive;
117 dsp_hbor_st = dst_hsync_len + dst_hback_porch;
118 dsp_vbor_end = dst_vsync_len + dst_vback_porch + dst_vactive;
119 dsp_vbor_st = dst_vsync_len + dst_vback_porch;
120 dsp_hact_st = dsp_hbor_st + bor_left;
121 dsp_hact_end = dsp_hbor_end - bor_right;
122 dsp_vact_st = dsp_vbor_st + bor_up;
123 dsp_vact_end = dsp_vbor_end - bor_down;
124
125 calc_dsp_frm_hst_vst(src, dst, &dsp_frame_hst, &dsp_frame_vst);
126 dev_info(rk628->dev, "dsp_frame_vst:%d dsp_frame_hst:%d\n",
127 dsp_frame_vst, dsp_frame_hst);
128
129 if (src_hactive > dst_hactive) {
130 scl_hor_mode = 2;
131
132 if (hor_down_mode == 0) {
133 if ((src_hactive - 1) / (dst_hactive - 1) > 2)
134 scl_h_factor = ((src_hactive - 1) << 14) /
135 (dst_hactive - 1);
136 else
137 scl_h_factor = ((src_hactive - 2) << 14) /
138 (dst_hactive - 1);
139 } else {
140 scl_h_factor = (dst_hactive << 16) / (src_hactive - 1);
141 }
142
143 } else if (src_hactive == dst_hactive) {
144 scl_hor_mode = 0;
145 scl_h_factor = 0;
146 } else {
147 scl_hor_mode = 1;
148 scl_h_factor = ((src_hactive - 1) << 16) / (dst_hactive - 1);
149 }
150
151 if (src_vactive > dst_vactive) {
152 scl_ver_mode = 2;
153
154 if (ver_down_mode == 0) {
155 if ((src_vactive - 1) / (dst_vactive - 1) > 2)
156 scl_v_factor = ((src_vactive - 1) << 14) /
157 (dst_vactive - 1);
158 else
159 scl_v_factor = ((src_vactive - 2) << 14) /
160 (dst_vactive - 1);
161 } else {
162 scl_v_factor = (dst_vactive << 16) / (src_vactive - 1);
163 }
164
165 } else if (src_vactive == dst_vactive) {
166 scl_ver_mode = 0;
167 scl_v_factor = 0;
168 } else {
169 scl_ver_mode = 1;
170 scl_v_factor = ((src_vactive - 1) << 16) / (dst_vactive - 1);
171 }
172
173 rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0, SW_HRES_MASK,
174 SW_HRES(src_hactive));
175 rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_VER_DOWN_MODE(ver_down_mode) |
176 SCL_HOR_DOWN_MODE(hor_down_mode) |
177 SCL_VER_MODE(scl_ver_mode) |
178 SCL_HOR_MODE(scl_hor_mode));
179 rk628_i2c_write(rk628, GRF_SCALER_CON1, SCL_V_FACTOR(scl_v_factor) |
180 SCL_H_FACTOR(scl_h_factor));
181 rk628_i2c_write(rk628, GRF_SCALER_CON2, DSP_FRAME_VST(dsp_frame_vst) |
182 DSP_FRAME_HST(dsp_frame_hst));
183 rk628_i2c_write(rk628, GRF_SCALER_CON3, DSP_HS_END(dsp_hs_end) |
184 DSP_HTOTAL(dsp_htotal));
185 rk628_i2c_write(rk628, GRF_SCALER_CON4, DSP_HACT_END(dsp_hact_end) |
186 DSP_HACT_ST(dsp_hact_st));
187 rk628_i2c_write(rk628, GRF_SCALER_CON5, DSP_VS_END(dsp_vs_end) |
188 DSP_VTOTAL(dsp_vtotal));
189 rk628_i2c_write(rk628, GRF_SCALER_CON6, DSP_VACT_END(dsp_vact_end) |
190 DSP_VACT_ST(dsp_vact_st));
191 rk628_i2c_write(rk628, GRF_SCALER_CON7, DSP_HBOR_END(dsp_hbor_end) |
192 DSP_HBOR_ST(dsp_hbor_st));
193 rk628_i2c_write(rk628, GRF_SCALER_CON8, DSP_VBOR_END(dsp_vbor_end) |
194 DSP_VBOR_ST(dsp_vbor_st));
195 }
196
rk628_post_process_init(struct rk628 * rk628)197 void rk628_post_process_init(struct rk628 *rk628)
198 {
199 struct rk628_display_mode *src = &rk628->src_mode;
200 const struct rk628_display_mode *dst = &rk628->dst_mode;
201 u64 dst_rate, src_rate;
202
203 src_rate = src->clock * 1000;
204 dst_rate = src_rate * dst->vdisplay * dst->htotal;
205 do_div(dst_rate, (src->vdisplay * src->htotal));
206 do_div(dst_rate, 1000);
207 dev_info(rk628->dev, "src %dx%d clock:%d\n",
208 src->hdisplay, src->vdisplay, src->clock);
209
210 dev_info(rk628->dev, "dst %dx%d clock:%llu\n",
211 dst->hdisplay, dst->vdisplay, dst_rate);
212
213 rk628_cru_clk_set_rate(rk628, CGU_CLK_RX_READ, src->clock * 1000);
214 rk628_cru_clk_set_rate(rk628, CGU_SCLK_VOP, dst_rate * 1000);
215
216 if (rk628->output_mode == OUTPUT_MODE_HDMI) {
217 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,
218 SW_VSYNC_POL(rk628->sync_pol));
219 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,
220 SW_HSYNC_POL(rk628->sync_pol));
221 } else {
222 if (src->flags & DRM_MODE_FLAG_PVSYNC)
223 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
224 SW_VSYNC_POL_MASK, SW_VSYNC_POL(1));
225 if (src->flags & DRM_MODE_FLAG_PHSYNC)
226 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
227 SW_HSYNC_POL_MASK,
228 SW_HSYNC_POL(1));
229 }
230
231 rk628_post_process_scaler_init(rk628, src, dst);
232 }
233
rk628_post_process_csc(struct rk628 * rk628)234 static void rk628_post_process_csc(struct rk628 *rk628)
235 {
236 enum bus_format in_fmt, out_fmt;
237
238 in_fmt = rk628_get_input_bus_format(rk628);
239 out_fmt = rk628_get_output_bus_format(rk628);
240
241 if (in_fmt == out_fmt) {
242 if (out_fmt == BUS_FMT_YUV422) {
243 rk628_i2c_write(rk628, GRF_CSC_CTRL_CON,
244 SW_YUV2VYU_SWP(1) |
245 SW_R2Y_EN(0));
246 return;
247 }
248 rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_R2Y_EN(0));
249 rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(0));
250 return;
251 }
252
253 if (in_fmt == BUS_FMT_RGB)
254 rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_R2Y_EN(1));
255 else if (out_fmt == BUS_FMT_RGB)
256 rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
257 }
258
rk628_post_process_enable(struct rk628 * rk628)259 void rk628_post_process_enable(struct rk628 *rk628)
260 {
261 rk628_post_process_csc(rk628);
262 rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_EN(1));
263 }
264
rk628_post_process_disable(struct rk628 * rk628)265 void rk628_post_process_disable(struct rk628 *rk628)
266 {
267 rk628_i2c_write(rk628, GRF_SCALER_CON0, SCL_EN(0));
268 }
269