1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Guochun Huang <hero.huang@rock-chips.com>
6 */
7
8 #include <asm/unaligned.h>
9 #include "rk628.h"
10 #include "rk628_cru.h"
11 #include "rk628_dsi.h"
12 #include "rk628_combtxphy.h"
13 #include "rk628_config.h"
14 #include "panel.h"
15
16 /* Test Code: 0x44 (HS RX Control of Lane 0) */
17 #define HSFREQRANGE(x) UPDATE(x, 6, 1)
18
19 /* request ACK from peripheral */
20 #define MIPI_DSI_MSG_REQ_ACK BIT(0)
21 /* use Low Power Mode to transmit message */
22 #define MIPI_DSI_MSG_USE_LPM BIT(1)
23
24 static u32 lane_mbps;
25
26 enum vid_mode_type {
27 VIDEO_MODE,
28 COMMAND_MODE,
29 };
30
31 enum dpi_color_coding {
32 DPI_COLOR_CODING_16BIT_1,
33 DPI_COLOR_CODING_16BIT_2,
34 DPI_COLOR_CODING_16BIT_3,
35 DPI_COLOR_CODING_18BIT_1,
36 DPI_COLOR_CODING_18BIT_2,
37 DPI_COLOR_CODING_24BIT,
38 };
39
40 enum {
41 VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
42 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
43 VID_MODE_TYPE_BURST,
44 };
45
46 /* MIPI DSI Processor-to-Peripheral transaction types */
47 enum {
48 MIPI_DSI_V_SYNC_START = 0x01,
49 MIPI_DSI_V_SYNC_END = 0x11,
50 MIPI_DSI_H_SYNC_START = 0x21,
51 MIPI_DSI_H_SYNC_END = 0x31,
52
53 MIPI_DSI_COLOR_MODE_OFF = 0x02,
54 MIPI_DSI_COLOR_MODE_ON = 0x12,
55 MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
56 MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
57
58 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
59 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
60 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
61
62 MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
63 MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
64 MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
65
66 MIPI_DSI_DCS_SHORT_WRITE = 0x05,
67 MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
68
69 MIPI_DSI_DCS_READ = 0x06,
70
71 MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
72 MIPI_DSI_PPS_LONG_WRITE = 0x0A,
73
74 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
75
76 MIPI_DSI_END_OF_TRANSMISSION = 0x08,
77
78 MIPI_DSI_NULL_PACKET = 0x09,
79 MIPI_DSI_BLANKING_PACKET = 0x19,
80 MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
81 MIPI_DSI_DCS_LONG_WRITE = 0x39,
82
83 MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
84 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
85 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
86
87 MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
88 MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
89 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
90
91 MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
92 MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
93 MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
94 MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
95 };
96
97 /* MIPI DSI Peripheral-to-Processor transaction types */
98 enum {
99 MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
100 MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
101 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
102 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
103 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
104 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
105 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
106 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
107 };
108
109 /* MIPI DCS commands */
110 enum {
111 MIPI_DCS_NOP = 0x00,
112 MIPI_DCS_SOFT_RESET = 0x01,
113 MIPI_DCS_GET_DISPLAY_ID = 0x04,
114 MIPI_DCS_GET_RED_CHANNEL = 0x06,
115 MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
116 MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
117 MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
118 MIPI_DCS_GET_POWER_MODE = 0x0A,
119 MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
120 MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
121 MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
122 MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
123 MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
124 MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
125 MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
126 MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
127 MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
128 MIPI_DCS_EXIT_INVERT_MODE = 0x20,
129 MIPI_DCS_ENTER_INVERT_MODE = 0x21,
130 MIPI_DCS_SET_GAMMA_CURVE = 0x26,
131 MIPI_DCS_SET_DISPLAY_OFF = 0x28,
132 MIPI_DCS_SET_DISPLAY_ON = 0x29,
133 MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
134 MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
135 MIPI_DCS_WRITE_MEMORY_START = 0x2C,
136 MIPI_DCS_WRITE_LUT = 0x2D,
137 MIPI_DCS_READ_MEMORY_START = 0x2E,
138 MIPI_DCS_SET_PARTIAL_AREA = 0x30,
139 MIPI_DCS_SET_SCROLL_AREA = 0x33,
140 MIPI_DCS_SET_TEAR_OFF = 0x34,
141 MIPI_DCS_SET_TEAR_ON = 0x35,
142 MIPI_DCS_SET_ADDRESS_MODE = 0x36,
143 MIPI_DCS_SET_SCROLL_START = 0x37,
144 MIPI_DCS_EXIT_IDLE_MODE = 0x38,
145 MIPI_DCS_ENTER_IDLE_MODE = 0x39,
146 MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
147 MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
148 MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
149 MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
150 MIPI_DCS_GET_SCANLINE = 0x45,
151 MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
152 MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */
153 MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */
154 MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */
155 MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */
156 MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */
157 MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
158 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
159 MIPI_DCS_READ_DDB_START = 0xA1,
160 MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
161 };
162
163 /**
164 * struct mipi_dsi_msg - read/write DSI buffer
165 * @channel: virtual channel id
166 * @type: payload data type
167 * @flags: flags controlling this message transmission
168 * @tx_len: length of @tx_buf
169 * @tx_buf: data to be written
170 * @rx_len: length of @rx_buf
171 * @rx_buf: data to be read, or NULL
172 */
173 struct mipi_dsi_msg {
174 u8 channel;
175 u8 type;
176 u16 flags;
177
178 size_t tx_len;
179 const void *tx_buf;
180
181 size_t rx_len;
182 void *rx_buf;
183 };
184
185 /**
186 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
187 * @size: size (in bytes) of the packet
188 * @header: the four bytes that make up the header (Data ID, Word Count or
189 * Packet Data, and ECC)
190 * @payload_length: number of bytes in the payload
191 * @payload: a pointer to a buffer containing the payload, if any
192 */
193 struct mipi_dsi_packet {
194 size_t size;
195 u8 header[4];
196 size_t payload_length;
197 const u8 *payload;
198 };
199
dsi_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u32 reg,u32 val)200 static inline int dsi_write(struct rk628 *rk628, const struct rk628_dsi *dsi,
201 u32 reg, u32 val)
202 {
203 unsigned int dsi_base;
204
205 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
206
207 return rk628_i2c_write(rk628, dsi_base + reg, val);
208 }
209
dsi_read(struct rk628 * rk628,const struct rk628_dsi * dsi,u32 reg,u32 * val)210 static inline int dsi_read(struct rk628 *rk628, const struct rk628_dsi *dsi,
211 u32 reg, u32 *val)
212 {
213 unsigned int dsi_base;
214
215 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
216
217 return rk628_i2c_read(rk628, dsi_base + reg, val);
218 }
219
dsi_update_bits(struct rk628 * rk628,const struct rk628_dsi * dsi,u32 reg,u32 mask,u32 val)220 static inline int dsi_update_bits(struct rk628 *rk628,
221 const struct rk628_dsi *dsi,
222 u32 reg, u32 mask, u32 val)
223 {
224 unsigned int dsi_base;
225
226 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
227
228 return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val);
229 }
230
rk628_dsi_parse(struct rk628 * rk628,struct device_node * dsi_np)231 int rk628_dsi_parse(struct rk628 *rk628, struct device_node *dsi_np)
232 {
233 u32 val;
234 const char *string;
235 int ret;
236
237 if (!of_device_is_available(dsi_np))
238 return -EINVAL;
239
240 rk628->output_mode = OUTPUT_MODE_DSI;
241 rk628->dsi0.id = 0;
242 rk628->dsi0.channel = 0;
243 rk628->dsi0.rk628 = rk628;
244
245 if (!of_property_read_u32(dsi_np, "dsi,lanes", &val))
246 rk628->dsi0.lanes = val;
247
248 if (of_property_read_bool(dsi_np, "dsi,video-mode"))
249 rk628->dsi0.mode_flags |= MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO |
250 MIPI_DSI_MODE_VIDEO_BURST;
251 else
252 rk628->dsi0.mode_flags |= MIPI_DSI_MODE_LPM;
253
254 if (of_property_read_bool(dsi_np, "dsi,eotp"))
255 rk628->dsi0.mode_flags |= MIPI_DSI_MODE_EOT_PACKET;
256
257 if (!of_property_read_string(dsi_np, "dsi,format", &string)) {
258 if (!strcmp(string, "rgb666")) {
259 rk628->dsi0.bus_format = MIPI_DSI_FMT_RGB666;
260 rk628->dsi0.bpp = 24;
261 } else if (!strcmp(string, "rgb666-packed")) {
262 rk628->dsi0.bus_format = MIPI_DSI_FMT_RGB666_PACKED;
263 rk628->dsi0.bpp = 18;
264 } else if (!strcmp(string, "rgb565")) {
265 rk628->dsi0.bus_format = MIPI_DSI_FMT_RGB565;
266 rk628->dsi0.bpp = 16;
267 } else {
268 rk628->dsi0.bus_format = MIPI_DSI_FMT_RGB888;
269 rk628->dsi0.bpp = 24;
270 }
271 }
272
273 if (of_property_read_bool(dsi_np, "rockchip,dual-channel")) {
274 rk628->dsi0.master = false;
275 rk628->dsi0.slave = true;
276
277 memcpy(&rk628->dsi1, &rk628->dsi0, sizeof(struct rk628_dsi));
278 rk628->dsi1.id = 1;
279 rk628->dsi1.master = true;
280 rk628->dsi1.slave = false;
281 }
282
283 ret = rk628_panel_info_get(rk628, dsi_np);
284 if (ret)
285 return ret;
286
287
288 return 0;
289 }
290
genif_wait_w_pld_fifo_not_full(struct rk628 * rk628,const struct rk628_dsi * dsi)291 static int genif_wait_w_pld_fifo_not_full(struct rk628 *rk628,
292 const struct rk628_dsi *dsi)
293 {
294 u32 sts;
295 int ret;
296 int dev_id;
297 unsigned int dsi_base;
298
299 dev_id = dsi->id ? RK628_DEV_DSI1 : RK628_DEV_DSI0;
300 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
301
302 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
303 dsi_base + DSI_CMD_PKT_STATUS,
304 sts, !(sts & GEN_PLD_W_FULL),
305 0, 1000);
306 if (ret < 0) {
307 dev_err(rk628->dev, "generic write payload fifo is full\n");
308 return ret;
309 }
310
311 return 0;
312 }
313
genif_wait_cmd_fifo_not_full(struct rk628 * rk628,const struct rk628_dsi * dsi)314 static int genif_wait_cmd_fifo_not_full(struct rk628 *rk628,
315 const struct rk628_dsi *dsi)
316 {
317 u32 sts;
318 int ret = 0;
319 int dev_id;
320 unsigned int dsi_base;
321
322 dev_id = dsi->id ? RK628_DEV_DSI1 : RK628_DEV_DSI0;
323 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
324
325 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
326 dsi_base + DSI_CMD_PKT_STATUS,
327 sts, !(sts & GEN_CMD_FULL),
328 0, 1000);
329 if (ret < 0) {
330 dev_err(rk628->dev, "generic write cmd fifo is full\n");
331 return ret;
332 }
333
334 return 0;
335 }
336
genif_wait_write_fifo_empty(struct rk628 * rk628,const struct rk628_dsi * dsi)337 static int genif_wait_write_fifo_empty(struct rk628 *rk628, const struct rk628_dsi *dsi)
338 {
339 u32 sts;
340 u32 mask;
341 int ret;
342 int dev_id;
343 unsigned int dsi_base;
344
345 dev_id = dsi->id ? RK628_DEV_DSI1 : RK628_DEV_DSI0;
346 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
347
348 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
349
350 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
351 dsi_base + DSI_CMD_PKT_STATUS,
352 sts, (sts & mask) == mask,
353 0, 1000);
354
355 if (ret < 0) {
356 dev_err(rk628->dev, "generic write fifo is full\n");
357 return ret;
358 }
359
360 return 0;
361 }
362
rk628_dsi_read_from_fifo(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct mipi_dsi_msg * msg)363 static int rk628_dsi_read_from_fifo(struct rk628 *rk628,
364 const struct rk628_dsi *dsi,
365 const struct mipi_dsi_msg *msg)
366 {
367 u8 *payload = msg->rx_buf;
368 unsigned int vrefresh = 60;
369 u16 length;
370 u32 val;
371 int ret;
372 int dev_id;
373 unsigned int dsi_base;
374
375 dev_id = dsi->id ? RK628_DEV_DSI1 : RK628_DEV_DSI0;
376 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
377
378 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
379 dsi_base + DSI_CMD_PKT_STATUS,
380 val, !(val & GEN_RD_CMD_BUSY),
381 0, DIV_ROUND_UP(1000000, vrefresh));
382 if (ret) {
383 dev_err(rk628->dev, "entire response isn't stored in the FIFO\n");
384 return ret;
385 }
386
387 /* Receive payload */
388 for (length = msg->rx_len; length; length -= 4) {
389 dsi_read(rk628, dsi, DSI_CMD_PKT_STATUS, &val);
390 if (val & GEN_PLD_R_EMPTY)
391 ret = -ETIMEDOUT;
392 if (ret) {
393 dev_err(rk628->dev, "dsi Read payload FIFO is empty\n");
394 return ret;
395 }
396
397 dsi_read(rk628, dsi, DSI_GEN_PLD_DATA, &val);
398
399 switch (length) {
400 case 3:
401 payload[2] = (val >> 16) & 0xff;
402 fallthrough;
403 case 2:
404 payload[1] = (val >> 8) & 0xff;
405 fallthrough;
406 case 1:
407 payload[0] = val & 0xff;
408 return 0;
409 }
410
411 payload[0] = (val >> 0) & 0xff;
412 payload[1] = (val >> 8) & 0xff;
413 payload[2] = (val >> 16) & 0xff;
414 payload[3] = (val >> 24) & 0xff;
415 payload += 4;
416 }
417
418 return 0;
419 }
420
421 /**
422 * mipi_dsi_packet_format_is_short - check if a packet is of the short format
423 * @type: MIPI DSI data type of the packet
424 *
425 * Return: true if the packet for the given data type is a short packet, false
426 * otherwise.
427 */
mipi_dsi_packet_format_is_short(u8 type)428 static bool mipi_dsi_packet_format_is_short(u8 type)
429 {
430 switch (type) {
431 case MIPI_DSI_V_SYNC_START:
432 case MIPI_DSI_V_SYNC_END:
433 case MIPI_DSI_H_SYNC_START:
434 case MIPI_DSI_H_SYNC_END:
435 case MIPI_DSI_END_OF_TRANSMISSION:
436 case MIPI_DSI_COLOR_MODE_OFF:
437 case MIPI_DSI_COLOR_MODE_ON:
438 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
439 case MIPI_DSI_TURN_ON_PERIPHERAL:
440 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
441 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
442 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
443 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
444 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
445 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
446 case MIPI_DSI_DCS_SHORT_WRITE:
447 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
448 case MIPI_DSI_DCS_READ:
449 case MIPI_DSI_DCS_COMPRESSION_MODE:
450 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
451 return true;
452 }
453
454 return false;
455 }
456
457 /**
458 * mipi_dsi_packet_format_is_long - check if a packet is of the long format
459 * @type: MIPI DSI data type of the packet
460 *
461 * Return: true if the packet for the given data type is a long packet, false
462 * otherwise.
463 */
mipi_dsi_packet_format_is_long(u8 type)464 static bool mipi_dsi_packet_format_is_long(u8 type)
465 {
466 switch (type) {
467 case MIPI_DSI_PPS_LONG_WRITE:
468 case MIPI_DSI_NULL_PACKET:
469 case MIPI_DSI_BLANKING_PACKET:
470 case MIPI_DSI_GENERIC_LONG_WRITE:
471 case MIPI_DSI_DCS_LONG_WRITE:
472 case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
473 case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
474 case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
475 case MIPI_DSI_PACKED_PIXEL_STREAM_30:
476 case MIPI_DSI_PACKED_PIXEL_STREAM_36:
477 case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12:
478 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
479 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
480 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
481 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
482 return true;
483 }
484
485 return false;
486 }
487
488 /**
489 * mipi_dsi_create_packet - create a packet from a message according to the
490 * DSI protocol
491 * @packet: pointer to a DSI packet structure
492 * @msg: message to translate into a packet
493 *
494 * Return: 0 on success or a negative error code on failure.
495 */
mipi_dsi_create_packet(struct mipi_dsi_packet * packet,const struct mipi_dsi_msg * msg)496 static int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
497 const struct mipi_dsi_msg *msg)
498 {
499 if (!packet || !msg)
500 return -EINVAL;
501
502 /* do some minimum sanity checking */
503 if (!mipi_dsi_packet_format_is_short(msg->type) &&
504 !mipi_dsi_packet_format_is_long(msg->type))
505 return -EINVAL;
506
507 if (msg->channel > 3)
508 return -EINVAL;
509
510 memset(packet, 0, sizeof(*packet));
511 packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
512
513 /* TODO: compute ECC if hardware support is not available */
514
515 /*
516 * Long write packets contain the word count in header bytes 1 and 2.
517 * The payload follows the header and is word count bytes long.
518 *
519 * Short write packets encode up to two parameters in header bytes 1
520 * and 2.
521 */
522 if (mipi_dsi_packet_format_is_long(msg->type)) {
523 packet->header[1] = (msg->tx_len >> 0) & 0xff;
524 packet->header[2] = (msg->tx_len >> 8) & 0xff;
525
526 packet->payload_length = msg->tx_len;
527 packet->payload = msg->tx_buf;
528 } else {
529 const u8 *tx = msg->tx_buf;
530
531 packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0;
532 packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0;
533 }
534
535 packet->size = sizeof(packet->header) + packet->payload_length;
536
537 return 0;
538 }
539
rk628_dsi_transfer(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct mipi_dsi_msg * msg)540 static int rk628_dsi_transfer(struct rk628 *rk628, const struct rk628_dsi *dsi,
541 const struct mipi_dsi_msg *msg)
542 {
543 struct mipi_dsi_packet packet;
544 int ret;
545 u32 val;
546
547 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
548 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG,
549 ACK_RQST_EN, ACK_RQST_EN);
550
551 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
552 dsi_update_bits(rk628, dsi, DSI_VID_MODE_CFG,
553 LP_CMD_EN, LP_CMD_EN);
554 } else {
555 dsi_update_bits(rk628, dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0);
556 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
557 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS);
558 }
559
560 switch (msg->type) {
561 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
562 //return rk628_dsi_shutdown_peripheral(dsi);
563 case MIPI_DSI_TURN_ON_PERIPHERAL:
564 //return rk628_dsi_turn_on_peripheral(dsi);
565 case MIPI_DSI_DCS_SHORT_WRITE:
566 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,
567 msg->flags & MIPI_DSI_MSG_USE_LPM ?
568 DCS_SW_0P_TX : 0);
569 break;
570 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
571 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,
572 msg->flags & MIPI_DSI_MSG_USE_LPM ?
573 DCS_SW_1P_TX : 0);
574 break;
575 case MIPI_DSI_DCS_LONG_WRITE:
576 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,
577 msg->flags & MIPI_DSI_MSG_USE_LPM ?
578 DCS_LW_TX : 0);
579 break;
580 case MIPI_DSI_DCS_READ:
581 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,
582 msg->flags & MIPI_DSI_MSG_USE_LPM ?
583 DCS_SR_0P_TX : 0);
584 break;
585 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
586 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE,
587 msg->flags & MIPI_DSI_MSG_USE_LPM ?
588 MAX_RD_PKT_SIZE : 0);
589 break;
590 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
591 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,
592 msg->flags & MIPI_DSI_MSG_USE_LPM ?
593 GEN_SW_0P_TX : 0);
594 break;
595 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
596 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,
597 msg->flags & MIPI_DSI_MSG_USE_LPM ?
598 GEN_SW_1P_TX : 0);
599 break;
600 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
601 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,
602 msg->flags & MIPI_DSI_MSG_USE_LPM ?
603 GEN_SW_2P_TX : 0);
604 break;
605 case MIPI_DSI_GENERIC_LONG_WRITE:
606 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,
607 msg->flags & MIPI_DSI_MSG_USE_LPM ?
608 GEN_LW_TX : 0);
609 break;
610 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
611 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,
612 msg->flags & MIPI_DSI_MSG_USE_LPM ? GEN_SR_0P_TX : 0);
613 break;
614 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
615 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,
616 msg->flags & MIPI_DSI_MSG_USE_LPM ? GEN_SR_1P_TX : 0);
617 break;
618 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
619 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,
620 msg->flags & MIPI_DSI_MSG_USE_LPM ? GEN_SR_2P_TX : 0);
621 break;
622 default:
623 return -EINVAL;
624 }
625
626 /* create a packet to the DSI protocol */
627 ret = mipi_dsi_create_packet(&packet, msg);
628 if (ret) {
629 dev_err(rk628->dev, "failed to create packet\n");
630 return ret;
631 }
632
633 /* Send payload */
634 while (packet.payload_length >= 4) {
635 /*
636 * Alternatively, you can always keep the FIFO
637 * nearly full by monitoring the FIFO state until
638 * it is not full, and then writea single word of data.
639 * This solution is more resource consuming
640 * but it simultaneously avoids FIFO starvation,
641 * making it possible to use FIFO sizes smaller than
642 * the amount of data of the longest packet to be written.
643 */
644 ret = genif_wait_w_pld_fifo_not_full(rk628, dsi);
645 if (ret)
646 return ret;
647
648 val = get_unaligned_le32(packet.payload);
649
650 dsi_write(rk628, dsi, DSI_GEN_PLD_DATA, val);
651
652
653 packet.payload += 4;
654 packet.payload_length -= 4;
655 }
656
657 val = 0;
658 switch (packet.payload_length) {
659 case 3:
660 val |= packet.payload[2] << 16;
661 fallthrough;
662 case 2:
663 val |= packet.payload[1] << 8;
664 fallthrough;
665 case 1:
666 val |= packet.payload[0];
667
668 dsi_write(rk628, dsi, DSI_GEN_PLD_DATA, val);
669 break;
670 }
671
672 ret = genif_wait_cmd_fifo_not_full(rk628, dsi);
673 if (ret)
674 return ret;
675
676 /* Send packet header */
677 val = get_unaligned_le32(packet.header);
678
679 dsi_write(rk628, dsi, DSI_GEN_HDR, val);
680
681 ret = genif_wait_write_fifo_empty(rk628, dsi);
682 if (ret)
683 return ret;
684
685 if (msg->rx_len) {
686 ret = rk628_dsi_read_from_fifo(rk628, dsi, msg);
687 if (ret < 0)
688 return ret;
689 }
690
691 if (dsi->slave) {
692 const struct rk628_dsi *dsi1 = &rk628->dsi1;
693
694 rk628_dsi_transfer(rk628, dsi1, msg);
695 }
696
697 return msg->tx_len;
698 }
699
rk628_mipi_dsi_generic_write(struct rk628 * rk628,const void * payload,size_t size)700 int rk628_mipi_dsi_generic_write(struct rk628 *rk628,
701 const void *payload, size_t size)
702 {
703 const struct rk628_dsi *dsi = &rk628->dsi0;
704 struct mipi_dsi_msg msg;
705
706 memset(&msg, 0, sizeof(msg));
707 msg.channel = dsi->channel;
708 msg.tx_buf = payload;
709 msg.tx_len = size;
710 msg.rx_len = 0;
711
712 switch (size) {
713 case 0:
714 msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
715 break;
716
717 case 1:
718 msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
719 break;
720 case 2:
721 msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
722 break;
723 default:
724 msg.type = MIPI_DSI_GENERIC_LONG_WRITE;
725 break;
726 }
727
728 if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
729 msg.flags |= MIPI_DSI_MSG_USE_LPM;
730
731 return rk628_dsi_transfer(rk628, dsi, &msg);
732 }
733
rk628_mipi_dsi_dcs_write_buffer(struct rk628 * rk628,const void * data,size_t len)734 int rk628_mipi_dsi_dcs_write_buffer(struct rk628 *rk628,
735 const void *data, size_t len)
736 {
737 const struct rk628_dsi *dsi = &rk628->dsi0;
738 struct mipi_dsi_msg msg;
739
740 memset(&msg, 0, sizeof(msg));
741 msg.channel = dsi->channel;
742 msg.tx_buf = data;
743 msg.tx_len = len;
744 msg.rx_len = 0;
745
746 switch (len) {
747 case 0:
748 return -EINVAL;
749 case 1:
750 msg.type = MIPI_DSI_DCS_SHORT_WRITE;
751 break;
752 case 2:
753 msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
754 break;
755 default:
756 msg.type = MIPI_DSI_DCS_LONG_WRITE;
757 break;
758 }
759
760 if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
761 msg.flags |= MIPI_DSI_MSG_USE_LPM;
762
763 return rk628_dsi_transfer(rk628, dsi, &msg);
764 }
765
rk628_mipi_dsi_dcs_read(struct rk628 * rk628,u8 cmd,void * data,size_t len)766 int rk628_mipi_dsi_dcs_read(struct rk628 *rk628, u8 cmd, void *data, size_t len)
767 {
768 const struct rk628_dsi *dsi = &rk628->dsi0;
769 struct mipi_dsi_msg msg;
770
771 memset(&msg, 0, sizeof(msg));
772 msg.channel = dsi->channel;
773 msg.type = MIPI_DSI_DCS_READ;
774 msg.tx_buf = &cmd;
775 msg.tx_len = 1;
776 msg.rx_buf = data;
777 msg.rx_len = len;
778
779 return rk628_dsi_transfer(rk628, dsi, &msg);
780 }
781
782 static int
panel_simple_xfer_dsi_cmd_seq(struct rk628 * rk628,struct panel_cmds * cmds)783 panel_simple_xfer_dsi_cmd_seq(struct rk628 *rk628, struct panel_cmds *cmds)
784 {
785 u16 i;
786 int err;
787
788 if (!cmds)
789 return 0;
790
791 for (i = 0; i < cmds->cmd_cnt; i++) {
792 struct cmd_desc *cmd = &cmds->cmds[i];
793
794 switch (cmd->dchdr.dtype) {
795 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
796 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
797 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
798 case MIPI_DSI_GENERIC_LONG_WRITE:
799 err = rk628_mipi_dsi_generic_write(rk628, cmd->payload,
800 cmd->dchdr.dlen);
801 break;
802 case MIPI_DSI_DCS_SHORT_WRITE:
803 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
804 case MIPI_DSI_DCS_LONG_WRITE:
805 err = rk628_mipi_dsi_dcs_write_buffer(rk628, cmd->payload,
806 cmd->dchdr.dlen);
807 break;
808 default:
809 dev_err(rk628->dev, "panel cmd desc invalid data type\n");
810 return -EINVAL;
811 }
812
813 if (err < 0)
814 dev_err(rk628->dev, "failed to write cmd\n");
815
816 if (cmd->dchdr.wait)
817 mdelay(cmd->dchdr.wait);
818 }
819
820 return 0;
821 }
822
rk628_dsi_get_lane_rate(const struct rk628_dsi * dsi)823 static u32 rk628_dsi_get_lane_rate(const struct rk628_dsi *dsi)
824 {
825 const struct rk628_display_mode *mode = &dsi->rk628->dst_mode;
826 u32 lane_rate;
827 u32 max_lane_rate = 1500;
828 u8 bpp, lanes;
829
830 bpp = dsi->bpp;
831 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
832 lane_rate = mode->clock / 1000 * bpp / lanes;
833 lane_rate = DIV_ROUND_UP(lane_rate * 5, 4);
834
835 if (lane_rate > max_lane_rate)
836 lane_rate = max_lane_rate;
837
838 return lane_rate;
839 }
840
testif_testclk_assert(struct rk628 * rk628,const struct rk628_dsi * dsi)841 static void testif_testclk_assert(struct rk628 *rk628,
842 const struct rk628_dsi *dsi)
843 {
844 rk628_i2c_update_bits(rk628, dsi->id ?
845 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
846 PHY_TESTCLK, PHY_TESTCLK);
847 udelay(1);
848 }
849
testif_testclk_deassert(struct rk628 * rk628,const struct rk628_dsi * dsi)850 static void testif_testclk_deassert(struct rk628 *rk628,
851 const struct rk628_dsi *dsi)
852 {
853 rk628_i2c_update_bits(rk628, dsi->id ?
854 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
855 PHY_TESTCLK, 0);
856 udelay(1);
857 }
858
testif_testclr_assert(struct rk628 * rk628,const struct rk628_dsi * dsi)859 static void testif_testclr_assert(struct rk628 *rk628,
860 const struct rk628_dsi *dsi)
861 {
862 rk628_i2c_update_bits(rk628, dsi->id ?
863 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
864 PHY_TESTCLR, PHY_TESTCLR);
865 udelay(1);
866 }
867
testif_testclr_deassert(struct rk628 * rk628,const struct rk628_dsi * dsi)868 static void testif_testclr_deassert(struct rk628 *rk628,
869 const struct rk628_dsi *dsi)
870 {
871 rk628_i2c_update_bits(rk628, dsi->id ?
872 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
873 PHY_TESTCLR, 0);
874 udelay(1);
875 }
876
testif_set_data(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 data)877 static void testif_set_data(struct rk628 *rk628,
878 const struct rk628_dsi *dsi, u8 data)
879 {
880 rk628_i2c_update_bits(rk628, dsi->id ?
881 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
882 PHY_TESTDIN_MASK, PHY_TESTDIN(data));
883 udelay(1);
884 }
885
testif_testen_assert(struct rk628 * rk628,const struct rk628_dsi * dsi)886 static void testif_testen_assert(struct rk628 *rk628,
887 const struct rk628_dsi *dsi)
888 {
889 rk628_i2c_update_bits(rk628, dsi->id ?
890 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
891 PHY_TESTEN, PHY_TESTEN);
892 udelay(1);
893 }
894
testif_testen_deassert(struct rk628 * rk628,const struct rk628_dsi * dsi)895 static void testif_testen_deassert(struct rk628 *rk628,
896 const struct rk628_dsi *dsi)
897 {
898 rk628_i2c_update_bits(rk628, dsi->id ?
899 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
900 PHY_TESTEN, 0);
901 udelay(1);
902 }
903
testif_test_code_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 test_code)904 static void testif_test_code_write(struct rk628 *rk628,
905 const struct rk628_dsi *dsi, u8 test_code)
906 {
907 testif_testclk_assert(rk628, dsi);
908 testif_set_data(rk628, dsi, test_code);
909 testif_testen_assert(rk628, dsi);
910 testif_testclk_deassert(rk628, dsi);
911 testif_testen_deassert(rk628, dsi);
912 }
913
testif_test_data_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 test_data)914 static void testif_test_data_write(struct rk628 *rk628,
915 const struct rk628_dsi *dsi, u8 test_data)
916 {
917 testif_testclk_deassert(rk628, dsi);
918 testif_set_data(rk628, dsi, test_data);
919 testif_testclk_assert(rk628, dsi);
920 }
921
testif_get_data(struct rk628 * rk628,const struct rk628_dsi * dsi)922 static u8 testif_get_data(struct rk628 *rk628, const struct rk628_dsi *dsi)
923 {
924 u32 data = 0;
925
926 rk628_i2c_read(rk628, dsi->id ? GRF_DPHY1_STATUS : GRF_DPHY0_STATUS, &data);
927
928 return data >> PHY_TESTDOUT_SHIFT;
929 }
930
testif_write(struct rk628 * rk628,const struct rk628_dsi * dsi,u8 reg,u8 value)931 static void testif_write(struct rk628 *rk628, const struct rk628_dsi *dsi,
932 u8 reg, u8 value)
933 {
934 u8 monitor_data;
935
936 testif_test_code_write(rk628, dsi, reg);
937 testif_test_data_write(rk628, dsi, value);
938 monitor_data = testif_get_data(rk628, dsi);
939 dev_info(rk628->dev, "monitor_data: 0x%x\n", monitor_data);
940 }
941
mipi_dphy_init(struct rk628 * rk628,const struct rk628_dsi * dsi)942 static void mipi_dphy_init(struct rk628 *rk628, const struct rk628_dsi *dsi)
943 {
944 const struct {
945 unsigned long max_lane_mbps;
946 u8 hsfreqrange;
947 } hsfreqrange_table[] = {
948 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
949 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
950 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
951 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
952 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
953 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
954 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
955 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
956 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
957 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
958 };
959 u8 hsfreqrange;
960 unsigned int index;
961
962 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
963 if (lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
964 break;
965
966 if (index == ARRAY_SIZE(hsfreqrange_table))
967 --index;
968
969 hsfreqrange = hsfreqrange_table[index].hsfreqrange;
970 testif_write(rk628, dsi, 0x44, HSFREQRANGE(hsfreqrange));
971 }
972
mipi_dphy_power_on(struct rk628 * rk628,const struct rk628_dsi * dsi)973 static void mipi_dphy_power_on(struct rk628 *rk628, const struct rk628_dsi *dsi)
974 {
975 int dev_id;
976 unsigned int dsi_base;
977 unsigned int val, mask;
978 int ret;
979
980 dev_id = dsi->id ? RK628_DEV_DSI1 : RK628_DEV_DSI0;
981 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE;
982
983 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
984 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
985 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0);
986 testif_testclr_assert(rk628, dsi);
987
988 /* Set all REQUEST inputs to zero */
989 rk628_i2c_update_bits(rk628, dsi->id ?
990 GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
991 FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
992 FORCETXSTOPMODE(0) | FORCERXMODE(0));
993 udelay(1);
994
995 testif_testclr_deassert(rk628, dsi);
996
997 mipi_dphy_init(rk628, dsi);
998
999 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ,
1000 PHY_ENABLECLK, PHY_ENABLECLK);
1001 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ,
1002 PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
1003 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
1004 usleep_range(1500, 2000);
1005
1006 rk628_combtxphy_power_on(rk628);
1007
1008 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
1009 dsi_base + DSI_PHY_STATUS,
1010 val, val & PHY_LOCK, 0, 1000);
1011 if (ret < 0)
1012 dev_err(rk628->dev, "PHY is not locked\n");
1013
1014 usleep_range(100, 200);
1015
1016 mask = PHY_STOPSTATELANE;
1017 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
1018 dsi_base + DSI_PHY_STATUS,
1019 val, (val & mask) == mask,
1020 0, 1000);
1021 if (ret < 0)
1022 dev_err(rk628->dev, "lane module is not in stop state\n");
1023
1024 udelay(10);
1025 }
1026
rk628_dsi0_reset_control_assert(struct rk628 * rk628)1027 void rk628_dsi0_reset_control_assert(struct rk628 *rk628)
1028 {
1029 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x400040);
1030 }
1031
rk628_dsi0_reset_control_deassert(struct rk628 * rk628)1032 void rk628_dsi0_reset_control_deassert(struct rk628 *rk628)
1033 {
1034 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x400000);
1035 }
1036
rk628_dsi1_reset_control_assert(struct rk628 * rk628)1037 void rk628_dsi1_reset_control_assert(struct rk628 *rk628)
1038 {
1039 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x800080);
1040 }
1041
rk628_dsi1_reset_control_deassert(struct rk628 * rk628)1042 void rk628_dsi1_reset_control_deassert(struct rk628 *rk628)
1043 {
1044 rk628_i2c_write(rk628, CRU_SOFTRST_CON02, 0x800000);
1045 }
1046
rk628_dsi_bridge_pre_enable(struct rk628 * rk628,const struct rk628_dsi * dsi)1047 void rk628_dsi_bridge_pre_enable(struct rk628 *rk628,
1048 const struct rk628_dsi *dsi)
1049 {
1050 u32 val;
1051
1052 dsi_write(rk628, dsi, DSI_PWR_UP, RESET);
1053 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
1054
1055 val = DIV_ROUND_UP(lane_mbps >> 3, 20);
1056 dsi_write(rk628, dsi, DSI_CLKMGR_CFG,
1057 TO_CLK_DIVISION(10) | TX_ESC_CLK_DIVISION(val));
1058
1059 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
1060 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
1061 val &= ~EOTP_TX_EN;
1062
1063 dsi_write(rk628, dsi, DSI_PCKHDL_CFG, val);
1064
1065 dsi_write(rk628, dsi, DSI_TO_CNT_CFG,
1066 HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
1067 dsi_write(rk628, dsi, DSI_BTA_TO_CNT, 0xd00);
1068 dsi_write(rk628, dsi, DSI_PHY_TMR_CFG,
1069 PHY_HS2LP_TIME(0x14) | PHY_LP2HS_TIME(0x10) |
1070 MAX_RD_TIME(10000));
1071 dsi_write(rk628, dsi, DSI_PHY_TMR_LPCLK_CFG,
1072 PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));
1073 dsi_write(rk628, dsi, DSI_PHY_IF_CFG,
1074 PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes - 1));
1075
1076 mipi_dphy_power_on(rk628, dsi);
1077
1078 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP);
1079 }
1080
rk628_dsi_set_vid_mode(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct rk628_display_mode * mode)1081 static void rk628_dsi_set_vid_mode(struct rk628 *rk628,
1082 const struct rk628_dsi *dsi,
1083 const struct rk628_display_mode *mode)
1084 {
1085 unsigned int lanebyteclk = (lane_mbps * 1000L) >> 3;
1086 unsigned int dpipclk = mode->clock;
1087 u32 hline, hsa, hbp, hline_time, hsa_time, hbp_time;
1088 u32 vactive, vsa, vfp, vbp;
1089 u32 val;
1090 int pkt_size;
1091
1092 val = LP_HFP_EN | LP_HBP_EN | LP_VACT_EN | LP_VFP_EN | LP_VBP_EN |
1093 LP_VSA_EN;
1094
1095 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
1096 val &= ~LP_HFP_EN;
1097
1098 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
1099 val &= ~LP_HBP_EN;
1100
1101 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
1102 val |= VID_MODE_TYPE_BURST;
1103 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
1104 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
1105 else
1106 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
1107
1108 dsi_write(rk628, dsi, DSI_VID_MODE_CFG, val);
1109
1110 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
1111 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
1112 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
1113
1114 if (dsi->slave || dsi->master)
1115 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2);
1116 else
1117 pkt_size = VID_PKT_SIZE(mode->hdisplay);
1118
1119 dsi_write(rk628, dsi, DSI_VID_PKT_SIZE, pkt_size);
1120
1121 vactive = mode->vdisplay;
1122 vsa = mode->vsync_end - mode->vsync_start;
1123 vfp = mode->vsync_start - mode->vdisplay;
1124 vbp = mode->vtotal - mode->vsync_end;
1125 hsa = mode->hsync_end - mode->hsync_start;
1126 hbp = mode->htotal - mode->hsync_end;
1127 hline = mode->htotal;
1128
1129 //hline_time = hline * lanebyteclk / dpipclk;
1130 hline_time = DIV_ROUND_CLOSEST_ULL(hline * lanebyteclk, dpipclk);
1131 dsi_write(rk628, dsi, DSI_VID_HLINE_TIME,
1132 VID_HLINE_TIME(hline_time));
1133 //hsa_time = hsa * lanebyteclk / dpipclk;
1134 hsa_time = DIV_ROUND_CLOSEST_ULL(hsa * lanebyteclk, dpipclk);
1135 dsi_write(rk628, dsi, DSI_VID_HSA_TIME, VID_HSA_TIME(hsa_time));
1136 //hbp_time = hbp * lanebyteclk / dpipclk;
1137 hbp_time = DIV_ROUND_CLOSEST_ULL(hbp * lanebyteclk, dpipclk);
1138 dsi_write(rk628, dsi, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
1139
1140 dsi_write(rk628, dsi, DSI_VID_VACTIVE_LINES, vactive);
1141 dsi_write(rk628, dsi, DSI_VID_VSA_LINES, vsa);
1142 dsi_write(rk628, dsi, DSI_VID_VFP_LINES, vfp);
1143 dsi_write(rk628, dsi, DSI_VID_VBP_LINES, vbp);
1144
1145 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));
1146 }
1147
rk628_dsi_set_cmd_mode(struct rk628 * rk628,const struct rk628_dsi * dsi,const struct rk628_display_mode * mode)1148 static void rk628_dsi_set_cmd_mode(struct rk628 *rk628,
1149 const struct rk628_dsi *dsi,
1150 const struct rk628_display_mode *mode)
1151 {
1152 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
1153 dsi_write(rk628, dsi, DSI_EDPI_CMD_SIZE,
1154 EDPI_ALLOWED_CMD_SIZE(mode->hdisplay));
1155 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
1156 }
1157
rk628_dsi_bridge_enable(struct rk628 * rk628,const struct rk628_dsi * dsi)1158 static void rk628_dsi_bridge_enable(struct rk628 *rk628,
1159 const struct rk628_dsi *dsi)
1160 {
1161 u32 val;
1162 const struct rk628_display_mode *mode = &rk628->dst_mode;
1163
1164 dsi_write(rk628, dsi, DSI_PWR_UP, RESET);
1165
1166 switch (dsi->bus_format) {
1167 case MIPI_DSI_FMT_RGB666:
1168 val = DPI_COLOR_CODING(DPI_COLOR_CODING_18BIT_2) |
1169 LOOSELY18_EN;
1170 break;
1171 case MIPI_DSI_FMT_RGB666_PACKED:
1172 val = DPI_COLOR_CODING(DPI_COLOR_CODING_18BIT_1);
1173 break;
1174 case MIPI_DSI_FMT_RGB565:
1175 val = DPI_COLOR_CODING(DPI_COLOR_CODING_16BIT_1);
1176 break;
1177 case MIPI_DSI_FMT_RGB888:
1178 default:
1179 val = DPI_COLOR_CODING(DPI_COLOR_CODING_24BIT);
1180 break;
1181 }
1182
1183 dsi_write(rk628, dsi, DSI_DPI_COLOR_CODING, val);
1184
1185 val = 0;
1186 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1187 val |= VSYNC_ACTIVE_LOW;
1188 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1189 val |= HSYNC_ACTIVE_LOW;
1190
1191 dsi_write(rk628, dsi, DSI_DPI_CFG_POL, val);
1192
1193 dsi_write(rk628, dsi, DSI_DPI_VCID, DPI_VID(0));
1194 dsi_write(rk628, dsi, DSI_DPI_LP_CMD_TIM,
1195 OUTVACT_LPCMD_TIME(4) | INVACT_LPCMD_TIME(4));
1196 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL,
1197 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS);
1198
1199 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO)
1200 rk628_dsi_set_vid_mode(rk628, dsi, mode);
1201 else
1202 rk628_dsi_set_cmd_mode(rk628, dsi, mode);
1203
1204 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP);
1205 }
1206
rk628_mipi_dsi_pre_enable(struct rk628 * rk628)1207 void rk628_mipi_dsi_pre_enable(struct rk628 *rk628)
1208 {
1209 const struct rk628_dsi *dsi = &rk628->dsi0;
1210 const struct rk628_dsi *dsi1 = &rk628->dsi1;
1211 u32 rate = rk628_dsi_get_lane_rate(dsi);
1212 int bus_width;
1213
1214 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
1215 SW_OUTPUT_MODE(OUTPUT_MODE_DSI));
1216 rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN,
1217 dsi->slave ? SW_SPLIT_EN : 0);
1218
1219 bus_width = rate << 8;
1220 if (dsi->slave)
1221 bus_width |= COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
1222 else if (dsi->id)
1223 bus_width |= COMBTXPHY_MODULEB_EN;
1224 else
1225 bus_width |= COMBTXPHY_MODULEA_EN;
1226
1227 rk628_combtxphy_set_bus_width(rk628, bus_width);
1228 rk628_combtxphy_set_mode(rk628, PHY_MODE_VIDEO_MIPI);
1229 lane_mbps = rk628_combtxphy_get_bus_width(rk628);
1230
1231 if (dsi->slave)
1232 lane_mbps = rk628_combtxphy_get_bus_width(rk628);
1233
1234 /* rst for dsi0 */
1235 rk628_dsi0_reset_control_assert(rk628);
1236 usleep_range(20, 40);
1237 rk628_dsi0_reset_control_deassert(rk628);
1238 usleep_range(20, 40);
1239
1240 rk628_dsi_bridge_pre_enable(rk628, dsi);
1241
1242 if (dsi->slave) {
1243 /* rst for dsi1 */
1244 rk628_dsi1_reset_control_assert(rk628);
1245 usleep_range(20, 40);
1246 rk628_dsi1_reset_control_deassert(rk628);
1247 usleep_range(20, 40);
1248
1249 rk628_dsi_bridge_pre_enable(rk628, dsi1);
1250 }
1251
1252 rk628_panel_prepare(rk628);
1253 panel_simple_xfer_dsi_cmd_seq(rk628, rk628->panel->on_cmds);
1254
1255 #ifdef DSI_READ_POWER_MODE
1256 u8 mode;
1257
1258 rk628_mipi_dsi_dcs_read(rk628, MIPI_DCS_GET_POWER_MODE,
1259 &mode, sizeof(mode));
1260
1261 dev_info(rk628->dev, "dsi: mode: 0x%x\n", mode);
1262 #endif
1263
1264 dev_info(rk628->dev, "rk628_dsi final DSI-Link bandwidth: %d x %d\n",
1265 lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);
1266 }
1267
rk628_mipi_dsi_enable(struct rk628 * rk628)1268 void rk628_mipi_dsi_enable(struct rk628 *rk628)
1269 {
1270 const struct rk628_dsi *dsi = &rk628->dsi0;
1271 const struct rk628_dsi *dsi1 = &rk628->dsi1;
1272
1273 rk628_dsi_bridge_enable(rk628, dsi);
1274
1275 if (dsi->slave)
1276 rk628_dsi_bridge_enable(rk628, dsi1);
1277
1278 rk628_panel_enable(rk628);
1279 }
1280
rk628_dsi_disable(struct rk628 * rk628)1281 void rk628_dsi_disable(struct rk628 *rk628)
1282 {
1283 const struct rk628_dsi *dsi = &rk628->dsi0;
1284 const struct rk628_dsi *dsi1 = &rk628->dsi1;
1285
1286 rk628_panel_disable(rk628);
1287
1288 dsi_write(rk628, dsi, DSI_PWR_UP, RESET);
1289 dsi_write(rk628, dsi, DSI_LPCLK_CTRL, 0);
1290 dsi_write(rk628, dsi, DSI_EDPI_CMD_SIZE, 0);
1291 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
1292 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP);
1293
1294 //dsi_write(rk628, dsi, DSI_PHY_RSTZ, 0);
1295
1296 if (dsi->slave) {
1297 dsi_write(rk628, dsi1, DSI_PWR_UP, RESET);
1298 dsi_write(rk628, dsi1, DSI_LPCLK_CTRL, 0);
1299 dsi_write(rk628, dsi1, DSI_EDPI_CMD_SIZE, 0);
1300 dsi_write(rk628, dsi1, DSI_MODE_CFG,
1301 CMD_VIDEO_MODE(COMMAND_MODE));
1302 dsi_write(rk628, dsi1, DSI_PWR_UP, POWER_UP);
1303
1304 //dsi_write(rk628, dsi1, DSI_PHY_RSTZ, 0);
1305 }
1306
1307 panel_simple_xfer_dsi_cmd_seq(rk628, rk628->panel->off_cmds);
1308 rk628_panel_unprepare(rk628);
1309 rk628_combtxphy_power_off(rk628);
1310 }
1311