1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Shunqing Chen <csq@rock-chisp.com>
6 */
7
8 #include "rk628.h"
9 #include "rk628_combrxphy.h"
10
11 #define MAX_ROUND 6
12 #define MAX_DATA_NUM 16
13 #define MAX_CHANNEL 3
14 #define CLK_DET_TRY_TIMES 10
15 #define CHECK_CNT 100
16 #define CLK_STABLE_LOOP_CNT 10
17 #define CLK_STABLE_THRESHOLD 6
18
rk628_combrxphy_try_clk_detect(struct rk628 * rk628)19 static int rk628_combrxphy_try_clk_detect(struct rk628 *rk628)
20 {
21 u32 val, i;
22 int ret;
23
24 ret = -1;
25
26 /* step1: set pin_rst_n to 1’b0.wait 1 period(1us).release reset */
27 /* step2: select pll clock src and enable auto check */
28 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val);
29 /* clear bit0 and bit3 */
30 val = val & 0xfffffff6;
31 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val);
32 /*
33 * step3: select hdmi mode and enable chip, read reg6654,
34 * make sure auto setup done.
35 */
36 /* auto fsm reset related */
37 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val);
38 val = val | BIT(24);
39 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val);
40 /* pull down ana rstn */
41 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
42 val = val & 0xfffffeff;
43 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
44 /* pull down dig rstn */
45 rk628_i2c_read(rk628, COMBRX_REG(0x66f4), &val);
46 val = val & 0xfffffffe;
47 rk628_i2c_write(rk628, COMBRX_REG(0x66f4), val);
48 /* pull up ana rstn */
49 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
50 val = val | 0x100;
51 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
52 /* pull up dig rstn */
53 rk628_i2c_read(rk628, COMBRX_REG(0x66f4), &val);
54 val = val | 0x1;
55 rk628_i2c_write(rk628, COMBRX_REG(0x66f4), val);
56
57 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
58 /* set bit0 and bit2 to 1*/
59 val = (val & 0xfffffff8) | 0x5;
60 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
61
62 /* auto fsm en = 0 */
63 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
64 /* set bit0 and bit2 to 1*/
65 val = (val & 0xfffffff8) | 0x4;
66 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
67
68 for (i = 0; i < 10; i++) {
69 mdelay(1);
70 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
71 if ((val & 0xf0000000) == 0x80000000) {
72 ret = 0;
73 dev_info(rk628->dev, "clock detected!\n");
74 break;
75 }
76 }
77
78 return ret;
79 }
80
rk628_combrxphy_get_data_of_round(struct rk628 * rk628,u32 * data)81 static void rk628_combrxphy_get_data_of_round(struct rk628 *rk628,
82 u32 *data)
83 {
84 u32 i;
85
86 for (i = 0; i < MAX_DATA_NUM; i++)
87 rk628_i2c_read(rk628, COMBRX_REG(0x6740 + i * 4), &data[i]);
88 }
89
rk628_combrxphy_set_dc_gain(struct rk628 * rk628,u32 x,u32 y,u32 z)90 static void rk628_combrxphy_set_dc_gain(struct rk628 *rk628,
91 u32 x, u32 y, u32 z)
92 {
93 u32 val;
94 u32 dc_gain_ch0, dc_gain_ch1, dc_gain_ch2;
95
96 dc_gain_ch0 = x & 0xf;
97 dc_gain_ch1 = y & 0xf;
98 dc_gain_ch2 = z & 0xf;
99 rk628_i2c_read(rk628, COMBRX_REG(0x661c), &val);
100
101 val = (val & 0xff0f0f0f) | (dc_gain_ch0 << 20) | (dc_gain_ch1 << 12) |
102 (dc_gain_ch2 << 4);
103 rk628_i2c_write(rk628, COMBRX_REG(0x661c), val);
104 }
105
rk628_combrxphy_set_data_of_round(u32 * data,u32 * data_in)106 static void rk628_combrxphy_set_data_of_round(u32 *data, u32 *data_in)
107 {
108 if ((data != NULL) && (data_in != NULL)) {
109 data_in[0] = data[0];
110 data_in[1] = data[7];
111 data_in[2] = data[13];
112 data_in[3] = data[14];
113 data_in[4] = data[15];
114 data_in[5] = data[1];
115 data_in[6] = data[2];
116 data_in[7] = data[3];
117 data_in[8] = data[4];
118 data_in[9] = data[5];
119 data_in[10] = data[6];
120 data_in[11] = data[8];
121 data_in[12] = data[9];
122 data_in[13] = data[10];
123 data_in[14] = data[11];
124 data_in[15] = data[12];
125 }
126 }
127
128 static void
rk628_combrxphy_max_zero_of_round(struct rk628 * rk628,u32 * data_in,u32 * max_zero,u32 * max_val,int n,int ch)129 rk628_combrxphy_max_zero_of_round(struct rk628 *rk628,
130 u32 *data_in, u32 *max_zero,
131 u32 *max_val, int n, int ch)
132 {
133 u32 i;
134 u32 cnt = 0;
135 u32 max_cnt = 0;
136 u32 max_v = 0;
137
138 for (i = 0; i < MAX_DATA_NUM; i++) {
139 if (max_v < data_in[i])
140 max_v = data_in[i];
141 }
142
143 for (i = 0; i < MAX_DATA_NUM; i++) {
144 if (data_in[i] == 0)
145 cnt = cnt + 200;
146 else if ((data_in[i] > 0) && (data_in[i] < 100))
147 cnt = cnt + 100 - data_in[i];
148 }
149 max_cnt = (cnt >= 3200) ? 0 : cnt;
150
151 max_zero[n] = max_cnt;
152 max_val[n] = max_v;
153 dev_info(rk628->dev, "channel:%d, round:%d, max_zero_cnt:%d, max_val:%#x\n",
154 ch, n, max_zero[n], max_val[n]);
155 }
156
rk628_combrxphy_chose_round_for_ch(struct rk628 * rk628,u32 * rd_max_zero,u32 * rd_max_val,int ch)157 static int rk628_combrxphy_chose_round_for_ch(struct rk628 *rk628,
158 u32 *rd_max_zero,
159 u32 *rd_max_val, int ch)
160 {
161 int i, rd = 0;
162 u32 max = 0;
163 u32 max_v = 0;
164
165 for (i = 0; i < MAX_ROUND; i++) {
166 if (rd_max_zero[i] > max) {
167 max = rd_max_zero[i];
168 max_v = rd_max_val[i];
169 rd = i;
170 } else if (rd_max_zero[i] == max && rd_max_val[i] > max_v) {
171 max = rd_max_zero[i];
172 max_v = rd_max_val[i];
173 rd = i;
174 }
175 }
176 dev_info(rk628->dev, "%s channel:%d, rd:%d\n", __func__, ch, rd);
177
178 return rd;
179 }
180
rk628_combrxphy_set_sample_edge_round(struct rk628 * rk628,u32 x,u32 y,u32 z)181 static void rk628_combrxphy_set_sample_edge_round(struct rk628 *rk628,
182 u32 x, u32 y, u32 z)
183 {
184 u32 val;
185 u32 equ_gain_ch0, equ_gain_ch1, equ_gain_ch2;
186
187 equ_gain_ch0 = (x & 0xf);
188 equ_gain_ch1 = (y & 0xf);
189 equ_gain_ch2 = (z & 0xf);
190 rk628_i2c_read(rk628, COMBRX_REG(0x6618), &val);
191 val = (val & 0xff00f0ff) | (equ_gain_ch1 << 20) |
192 (equ_gain_ch0 << 16) | (equ_gain_ch2 << 8);
193 rk628_i2c_write(rk628, COMBRX_REG(0x6618), val);
194 }
195
rk628_combrxphy_start_sample_edge(struct rk628 * rk628)196 static void rk628_combrxphy_start_sample_edge(struct rk628 *rk628)
197 {
198 u32 val;
199
200 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
201 val &= 0xfffff1ff;
202 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
203 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
204 val = (val & 0xfffff1ff) | (0x7 << 9);
205 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
206 }
207
rk628_combrxphy_set_sample_edge_mode(struct rk628 * rk628,int ch)208 static void rk628_combrxphy_set_sample_edge_mode(struct rk628 *rk628, int ch)
209 {
210 u32 val;
211
212 rk628_i2c_read(rk628, COMBRX_REG(0x6634), &val);
213 val = val & (~(0xf << ((ch + 1) * 4)));
214 rk628_i2c_write(rk628, COMBRX_REG(0x6634), val);
215 }
216
rk628_combrxphy_select_channel(struct rk628 * rk628,int ch)217 static void rk628_combrxphy_select_channel(struct rk628 *rk628, int ch)
218 {
219 u32 val;
220
221 rk628_i2c_read(rk628, COMBRX_REG(0x6700), &val);
222 val = (val & 0xfffffffc) | (ch & 0x3);
223 rk628_i2c_write(rk628, COMBRX_REG(0x6700), val);
224 }
225
rk628_combrxphy_cfg_6730(struct rk628 * rk628)226 static void rk628_combrxphy_cfg_6730(struct rk628 *rk628)
227 {
228 u32 val;
229
230 rk628_i2c_read(rk628, COMBRX_REG(0x6730), &val);
231 val = (val & 0xffff0000) | 0x1;
232 rk628_i2c_write(rk628, COMBRX_REG(0x6730), val);
233 }
234
rk628_combrxphy_sample_edge_procedure_for_cable(struct rk628 * rk628,u32 cdr_mode)235 static void rk628_combrxphy_sample_edge_procedure_for_cable(struct rk628 *rk628,
236 u32 cdr_mode)
237 {
238 u32 n, ch;
239 u32 data[MAX_DATA_NUM];
240 u32 data_in[MAX_DATA_NUM];
241 u32 round_max_zero[MAX_CHANNEL][MAX_ROUND];
242 u32 round_max_value[MAX_CHANNEL][MAX_ROUND];
243 u32 ch_round[MAX_CHANNEL];
244 u32 edge, dc_gain;
245 u32 rd_offset;
246
247 /* Step1: set sample edge mode for channel 0~2 */
248 for (ch = 0; ch < MAX_CHANNEL; ch++)
249 rk628_combrxphy_set_sample_edge_mode(rk628, ch);
250
251 /* step2: once per round */
252 for (ch = 0; ch < MAX_CHANNEL; ch++) {
253 rk628_combrxphy_select_channel(rk628, ch);
254 rk628_combrxphy_cfg_6730(rk628);
255 }
256
257 /*
258 * step3: config sample edge until the end of one frame
259 * (for example 1080p:2200*1125=32’h25c3f8)
260 */
261 if (cdr_mode < 16) {
262 dc_gain = 0;
263 rd_offset = 0;
264 } else if (cdr_mode < 18) {
265 dc_gain = 1;
266 rd_offset = 0;
267 } else {
268 dc_gain = 3;
269 rd_offset = 2;
270 }
271
272 /*
273 * When the pix clk is the same, the low frame rate resolution is used
274 * to calculate the sampling window (the frame rate is not less than
275 * 30). The sampling delay time is configured as 40ms.
276 */
277 if (cdr_mode <= 1) { /* 27M vic17 720x576P50 */
278 edge = 864 * 625;
279 } else if (cdr_mode <= 4) { /* 59.4M vic81 1680x720P30 */
280 edge = 2640 * 750;
281 } else if (cdr_mode <= 7) { /* 74.25M vic34 1920x1080P30 */
282 edge = 2200 * 1125;
283 } else if (cdr_mode <= 14) { /* 119M vic88 2560x1180P30 */
284 edge = 3520 * 1125;
285 } else if (cdr_mode <= 16) { /* 148.5M vic31 1920x1080P50 */
286 edge = 2640 * 1125;
287 } else if (cdr_mode <= 17) { /* 162M vic89 2560x1080P50 */
288 edge = 3300 * 1125;
289 } else if (cdr_mode <= 18) { /* 297M vic95 3840x2160P30 */
290 edge = 4400 * 2250;
291 } else { /* unknown vic16 1920x1080P60 */
292 edge = 2200 * 1125;
293 }
294
295 dev_info(rk628->dev, "cdr_mode:%d, dc_gain:%d, rd_offset:%d, edge:%#x\n",
296 cdr_mode, dc_gain, rd_offset, edge);
297 for (ch = 0; ch < MAX_CHANNEL; ch++) {
298 rk628_combrxphy_select_channel(rk628, ch);
299 rk628_i2c_write(rk628, COMBRX_REG(0x6708), edge);
300 }
301
302 rk628_combrxphy_set_dc_gain(rk628, dc_gain, dc_gain, dc_gain);
303 for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) {
304 /* step4:set sample edge round value n,n=0(n=0~31) */
305 rk628_combrxphy_set_sample_edge_round(rk628, n, n, n);
306 /* step5:start sample edge */
307 rk628_combrxphy_start_sample_edge(rk628);
308 /* step6:waiting more than one frame time */
309 mdelay(41);
310 for (ch = 0; ch < MAX_CHANNEL; ch++) {
311 /* step7: get data of round n */
312 rk628_combrxphy_select_channel(rk628, ch);
313 rk628_combrxphy_get_data_of_round(rk628, data);
314 rk628_combrxphy_set_data_of_round(data, data_in);
315 /* step8: get the max constant value of round n */
316 rk628_combrxphy_max_zero_of_round(rk628, data_in,
317 round_max_zero[ch], round_max_value[ch],
318 n - rd_offset, ch);
319 }
320 }
321
322 /*
323 * step9: after finish round, get the max constant value and
324 * corresponding value n.
325 */
326 for (ch = 0; ch < MAX_CHANNEL; ch++) {
327 ch_round[ch] = rk628_combrxphy_chose_round_for_ch(rk628, round_max_zero[ch],
328 round_max_value[ch], ch);
329 ch_round[ch] += rd_offset;
330 }
331 dev_info(rk628->dev, "last equ gain ch0:%d, ch1:%d, ch2:%d\n",
332 ch_round[0], ch_round[1], ch_round[2]);
333
334 /* step10: write result to sample edge round value */
335 rk628_combrxphy_set_sample_edge_round(rk628, ch_round[0], ch_round[1], ch_round[2]);
336
337 /* do step5, step6 again */
338 /* step5:start sample edge */
339 rk628_combrxphy_start_sample_edge(rk628);
340 /* step6:waiting more than one frame time */
341 mdelay(41);
342 }
343
rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628 * rk628,int f)344 static int rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628 *rk628, int f)
345 {
346 u32 val, val_a, val_b, data_a, data_b;
347 u32 i, j, count, ret;
348 u32 cdr_mode, cdr_data, pll_man;
349 u32 tmds_bitrate_per_lane;
350 u32 cdr_data_min, cdr_data_max;
351 u32 state, channel_st;
352 bool is_yuv420;
353
354 /*
355 * use the mode of automatic clock detection, only supports fixed TMDS
356 * frequency.Refer to register 0x6654[21:16]:
357 * 5'd31:Error mode
358 * 5'd30:manual mode detected
359 * 5'd18:rx3p clock = 297MHz
360 * 5'd17:rx3p clock = 162MHz
361 * 5'd16:rx3p clock = 148.5MHz
362 * 5'd15:rx3p clock = 135MHz
363 * 5'd14:rx3p clock = 119MHz
364 * 5'd13:rx3p clock = 108MHz
365 * 5'd12:rx3p clock = 101MHz
366 * 5'd11:rx3p clock = 92.8125MHz
367 * 5'd10:rx3p clock = 88.75MHz
368 * 5'd9:rx3p clock = 85.5MHz
369 * 5'd8:rx3p clock = 83.5MHz
370 * 5'd7:rx3p clock = 74.25MHz
371 * 5'd6:rx3p clock = 68.25MHz
372 * 5'd5:rx3p clock = 65MHz
373 * 5'd4:rx3p clock = 59.4MHz
374 * 5'd3:rx3p clock = 40MHz
375 * 5'd2:rx3p clock = 33.75MHz
376 * 5'd1:rx3p clock = 27MHz
377 * 5'd0:rx3p clock = 25.17MHz
378 */
379
380 const u32 cdr_mode_to_khz[] = {
381 25170, 27000, 33750, 40000, 59400, 65000, 68250,
382 74250, 83500, 85500, 88750, 92812, 101000, 108000,
383 119000, 135000, 148500, 162000, 297000,
384 };
385
386 for (i = 0; i < CLK_DET_TRY_TIMES; i++) {
387 if (rk628_combrxphy_try_clk_detect(rk628) >= 0)
388 break;
389 mdelay(1);
390 }
391 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
392 dev_info(rk628->dev, "clk det over cnt:%d, reg_0x6654:%#x\n", i, val);
393 state = (val >> 28) & 0xf;
394 if (state == 5) {
395 dev_info(rk628->dev, "Clock detection anomaly\n");
396 } else if (state == 4) {
397 channel_st = (val >> 21) & 0x7f;
398 dev_info(rk628->dev, "%s%s%s%s%s%s%s%s level detection anomaly\n",
399 channel_st & 0x40 ? "|clk_p|" : "",
400 channel_st & 0x20 ? "|clk_n|" : "",
401 channel_st & 0x10 ? "|d0_p|" : "",
402 channel_st & 0x08 ? "|d0_n|" : "",
403 channel_st & 0x04 ? "|d1_p|" : "",
404 channel_st & 0x02 ? "|d1_n|" : "",
405 channel_st & 0x01 ? "|d2_p|" : "",
406 channel_st ? "" : "|d2_n|");
407 }
408
409 rk628_i2c_read(rk628, COMBRX_REG(0x6620), &val);
410 if ((i == CLK_DET_TRY_TIMES) ||
411 ((val & 0x7f000000) == 0) ||
412 ((val & 0x007f0000) == 0) ||
413 ((val & 0x00007f00) == 0) ||
414 ((val & 0x0000007f) == 0)) {
415 dev_info(rk628->dev, "clock detected failed, cfg resistance manual!\n");
416 rk628_i2c_write(rk628, COMBRX_REG(0x6620), 0x66666666);
417 rk628_i2c_update_bits(rk628, COMBRX_REG(0x6604), BIT(31), BIT(31));
418 mdelay(1);
419 }
420
421 /* step4: get cdr_mode and cdr_data */
422 for (j = 0; j < CLK_STABLE_LOOP_CNT ; j++) {
423 cdr_data_min = 0xffffffff;
424 cdr_data_max = 0;
425
426 for (i = 0; i < CLK_DET_TRY_TIMES; i++) {
427 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
428 cdr_data = val & 0xffff;
429 if (cdr_data <= cdr_data_min)
430 cdr_data_min = cdr_data;
431 if (cdr_data >= cdr_data_max)
432 cdr_data_max = cdr_data;
433 udelay(50);
434 }
435
436 if (((cdr_data_max - cdr_data_min) <= CLK_STABLE_THRESHOLD) &&
437 (cdr_data_min >= 60)) {
438 dev_info(rk628->dev, "clock stable!");
439 break;
440 }
441 }
442
443 if (j == CLK_STABLE_LOOP_CNT) {
444 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val_a);
445 rk628_i2c_read(rk628, COMBRX_REG(0x6608), &val_b);
446 dev_err(rk628->dev,
447 "clk not stable, reg_0x6630:%#x, reg_0x6608:%#x",
448 val_a, val_b);
449 /* bypass level detection anomaly */
450 if (state == 4)
451 rk628_i2c_update_bits(rk628, COMBRX_REG(0x6628), BIT(31), BIT(31));
452 else
453 return -EINVAL;
454 }
455
456 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
457 if ((val & 0x1f0000) == 0x1f0000) {
458 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val_a);
459 rk628_i2c_read(rk628, COMBRX_REG(0x6608), &val_b);
460 dev_err(rk628->dev,
461 "clock error: 0x1f, reg_0x6630:%#x, reg_0x6608:%#x",
462 val_a, val_b);
463
464 return -EINVAL;
465 }
466
467 cdr_mode = (val >> 16) & 0x1f;
468 cdr_data = val & 0xffff;
469 dev_info(rk628->dev, "cdr_mode:%d, cdr_data:%d\n", cdr_mode, cdr_data);
470
471 f = f & 0x7fffffff;
472 is_yuv420 = (f & BIT(30)) ? true : false;
473 f = f & 0xffffff;
474 dev_info(rk628->dev, "f:%d\n", f);
475
476 /*
477 * step5: manually configure PLL
478 * cfg reg 66a8 tmds clock div2 for rgb/yuv444 as default
479 * reg 662c[16:8] pll_pre_div
480 */
481 if (f <= 340000) {
482 rk628_i2c_write(rk628, COMBRX_REG(0x662c), 0x01000500);
483 if (is_yuv420)
484 rk628_i2c_write(rk628, COMBRX_REG(0x66a8), 0x0000c000);
485 else
486 rk628_i2c_write(rk628, COMBRX_REG(0x66a8), 0x0000c600);
487 } else {
488 rk628_i2c_write(rk628, COMBRX_REG(0x662c), 0x01001400);
489 rk628_i2c_write(rk628, COMBRX_REG(0x66a8), 0x0000c600);
490 }
491
492 /* when tmds bitrate/lane <= 340M, bitrate/lane = pix_clk * 10 */
493 tmds_bitrate_per_lane = cdr_mode_to_khz[cdr_mode] * 10;
494 if (tmds_bitrate_per_lane < 400000)
495 pll_man = 0x7960c;
496 else if (tmds_bitrate_per_lane < 600000)
497 pll_man = 0x7750c;
498 else if (tmds_bitrate_per_lane < 800000)
499 pll_man = 0x7964c;
500 else if (tmds_bitrate_per_lane < 1000000)
501 pll_man = 0x7754c;
502 else if (tmds_bitrate_per_lane < 1600000)
503 pll_man = 0x7a108;
504 else if (tmds_bitrate_per_lane < 2400000)
505 pll_man = 0x73588;
506 else if (tmds_bitrate_per_lane < 3400000)
507 pll_man = 0x7a108;
508 else
509 pll_man = 0x7f0c8;
510
511 dev_info(rk628->dev, "cdr_mode:%d, pll_man:%#x\n", cdr_mode, pll_man);
512 rk628_i2c_write(rk628, COMBRX_REG(0x6630), pll_man);
513
514 /* step6: EQ and SAMPLE cfg */
515 rk628_combrxphy_sample_edge_procedure_for_cable(rk628, cdr_mode);
516
517 /* step7: Deassert fifo reset,enable fifo write and read */
518 /* reset rx_infifo */
519 rk628_i2c_write(rk628, COMBRX_REG(0x66a0), 0x00000003);
520 /* rx_infofo wr/rd disable */
521 rk628_i2c_write(rk628, COMBRX_REG(0x66b0), 0x00080060);
522 /* deassert rx_infifo reset */
523 rk628_i2c_write(rk628, COMBRX_REG(0x66a0), 0x00000083);
524 /* enable rx_infofo wr/rd en */
525 rk628_i2c_write(rk628, COMBRX_REG(0x66b0), 0x00380060);
526 /* cfg 0x2260 high_8b to 0x66ac high_8b, low_8b to 0x66b0 low_8b */
527 rk628_i2c_update_bits(rk628, COMBRX_REG(0x66ac),
528 GENMASK(31, 24), UPDATE(0x22, 31, 24));
529 mdelay(6);
530
531 /* step8: check all 3 data channels alignment */
532 count = 0;
533 for (i = 0; i < CHECK_CNT; i++) {
534 mdelay(1);
535 rk628_i2c_read(rk628, COMBRX_REG(0x66b4), &data_a);
536 rk628_i2c_read(rk628, COMBRX_REG(0x66b8), &data_b);
537 /* ch0 ch1 ch2 lock */
538 if (((data_a & 0x00ff00ff) == 0x00ff00ff) &&
539 ((data_b & 0xff) == 0xff)) {
540 count++;
541 }
542 }
543
544 if (count >= CHECK_CNT) {
545 dev_info(rk628->dev, "channel alignment done\n");
546 dev_info(rk628->dev, "rx initial done\n");
547 ret = 0;
548 } else if (count > 0) {
549 dev_info(rk628->dev, "link not stable, count:%d of 100\n", count);
550 ret = 0;
551 } else {
552 dev_err(rk628->dev, "channel alignment failed!\n");
553 ret = -EINVAL;
554 }
555
556 return ret;
557 }
558
rk628_combrxphy_power_on(struct rk628 * rk628,int f)559 int rk628_combrxphy_power_on(struct rk628 *rk628, int f)
560 {
561 return rk628_combrxphy_set_hdmi_mode_for_cable(rk628, f);
562 }
563
rk628_combrxphy_power_off(struct rk628 * rk628)564 int rk628_combrxphy_power_off(struct rk628 *rk628)
565 {
566 return 0;
567 }
568