1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #ifndef _RK628_H
9 #define _RK628_H
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/regmap.h>
15 #include <linux/version.h>
16 #include <linux/of.h>
17 #include <linux/wakelock.h>
18 #include <linux/workqueue.h>
19 #include <linux/regulator/consumer.h>
20
21 #define DRIVER_VERSION "0.0.1"
22 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
23 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | \
24 (GENMASK((h), (l)) << 16))
25
26 #define GRF_SYSTEM_CON0 0x0000
27 #define SW_VSYNC_POL_MASK BIT(26)
28 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
29 #define SW_HSYNC_POL_MASK BIT(25)
30 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
31 #define SW_ADAPTER_I2CSLADR_MASK GENMASK(24, 22)
32 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
33 #define SW_EDID_MODE_MASK BIT(21)
34 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
35 #define SW_I2S_DATA_OEN_MASK BIT(10)
36 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
37 #define SW_BT_DATA_OEN_MASK BIT(9)
38 #define SW_BT_DATA_OEN BIT(9)
39 #define SW_EFUSE_HDCP_EN_MASK BIT(8)
40 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
41 #define SW_OUTPUT_MODE_MASK GENMASK(7, 3)
42 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
43 #define SW_INPUT_MODE_MASK GENMASK(2, 0)
44 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
45 #define GRF_SYSTEM_CON1 0x0004
46 #define GRF_SYSTEM_CON2 0x0008
47 #define GRF_SYSTEM_CON3 0x000c
48 #define GRF_GPIO_RX_CEC_SEL_MASK BIT(7)
49 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
50 #define GRF_GPIO_RXDDC_SDA_SEL_MASK BIT(6)
51 #define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6)
52 #define GRF_GPIO_RXDDC_SCL_SEL_MASK BIT(5)
53 #define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5)
54 #define GRF_SCALER_CON0 0x0010
55 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
56 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
57 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
58 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
59 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
60 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
61 #define GRF_SCALER_CON1 0x0014
62 #define SCL_V_FACTOR(x) UPDATE(x, 31, 16)
63 #define SCL_H_FACTOR(x) UPDATE(x, 15, 0)
64 #define GRF_SCALER_CON2 0x0018
65 #define DSP_FRAME_VST(x) UPDATE(x, 28, 16)
66 #define DSP_FRAME_HST(x) UPDATE(x, 12, 0)
67 #define GRF_SCALER_CON3 0x001c
68 #define DSP_HS_END(x) UPDATE(x, 23, 16)
69 #define DSP_HTOTAL(x) UPDATE(x, 12, 0)
70 #define GRF_SCALER_CON4 0x0020
71 #define DSP_HACT_ST(x) UPDATE(x, 28, 16)
72 #define DSP_HACT_END(x) UPDATE(x, 12, 0)
73 #define GRF_SCALER_CON5 0x0024
74 #define DSP_VS_END(x) UPDATE(x, 23, 16)
75 #define DSP_VTOTAL(x) UPDATE(x, 12, 0)
76 #define GRF_SCALER_CON6 0x0028
77 #define DSP_VACT_ST(x) UPDATE(x, 28, 16)
78 #define DSP_VACT_END(x) UPDATE(x, 12, 0)
79 #define GRF_SCALER_CON7 0x002c
80 #define DSP_HBOR_ST(x) UPDATE(x, 28, 16)
81 #define DSP_HBOR_END(x) UPDATE(x, 12, 0)
82 #define GRF_SCALER_CON8 0x0030
83 #define DSP_VBOR_ST(x) UPDATE(x, 28, 16)
84 #define DSP_VBOR_END(x) UPDATE(x, 12, 0)
85 #define GRF_POST_PROC_CON 0x0034
86 #define SW_DCLK_OUT_INV_EN BIT(9)
87 #define SW_DCLK_IN_INV_EN BIT(8)
88 #define SW_TXPHY_REFCLK_SEL_MASK GENMASK(6, 5)
89 #define SW_TXPHY_REFCLK_SEL(x) UPDATE(x, 6, 5)
90 #define SW_HDMITX_VCLK_PLLREF_SEL_MASK BIT(4)
91 #define SW_HDMITX_VCLK_PLLREF_SEL(x) UPDATE(x, 4, 4)
92 #define SW_HDMITX_DCLK_INV_EN BIT(3)
93 #define SW_SPLIT_MODE(x) UPDATE(x, 1, 1)
94 #define SW_SPLIT_EN BIT(0)
95 #define GRF_CSC_CTRL_CON 0x0038
96 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
97 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
98 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
99 #define GRF_LVDS_TX_CON 0x003c
100 #define SW_LVDS_CON_DUAL_SEL(x) HIWORD_UPDATE(x, 12, 12)
101 #define SW_LVDS_CON_DEN_POLARITY(x) HIWORD_UPDATE(x, 11, 11)
102 #define SW_LVDS_CON_HS_POLARITY(x) HIWORD_UPDATE(x, 10, 10)
103 #define SW_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 9, 9)
104 #define SW_LVDS_STARTPHASE(x) HIWORD_UPDATE(x, 8, 8)
105 #define SW_LVDS_CON_STARTSEL(x) HIWORD_UPDATE(x, 7, 7)
106 #define SW_LVDS_CON_CHASEL(x) HIWORD_UPDATE(x, 6, 6)
107 #define SW_LVDS_TIE_VSYNC_VALUE(x) HIWORD_UPDATE(x, 5, 5)
108 #define SW_LVDS_TIE_HSYNC_VALUE(x) HIWORD_UPDATE(x, 4, 4)
109 #define SW_LVDS_TIE_DEN_ONLY(x) HIWORD_UPDATE(x, 3, 3)
110 #define SW_LVDS_CON_MSBSEL(x) HIWORD_UPDATE(x, 2, 2)
111 #define SW_LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0)
112 #define GRF_RGB_DEC_CON0 0x0040
113 #define SW_HRES_MASK GENMASK(28, 16)
114 #define SW_HRES(x) UPDATE(x, 28, 16)
115 #define DUAL_DATA_SWAP BIT(6)
116 #define DEC_DUALEDGE_EN BIT(5)
117 #define SW_PROGRESS_EN BIT(4)
118 #define SW_YC_SWAP BIT(3)
119 #define SW_CAP_EN_ASYNC BIT(1)
120 #define SW_CAP_EN_PSYNC BIT(0)
121 #define GRF_RGB_DEC_CON1 0x0044
122 #define SW_SET_X_MASK GENMASK(28, 16)
123 #define SW_SET_X(x) HIWORD_UPDATE(x, 28, 16)
124 #define SW_SET_Y_MASK GENMASK(28, 16)
125 #define SW_SET_Y(x) HIWORD_UPDATE(x, 28, 16)
126 #define GRF_RGB_DEC_CON2 0x0048
127 #define GRF_RGB_ENC_CON 0x004c
128 #define BT1120_UV_SWAP(x) HIWORD_UPDATE(x, 5, 5)
129 #define ENC_DUALEDGE_EN(x) HIWORD_UPDATE(x, 3, 3)
130 #define GRF_MIPI_LANE_DELAY_CON0 0x0050
131 #define GRF_MIPI_LANE_DELAY_CON1 0x0054
132 #define GRF_BT1120_DCLK_DELAY_CON0 0x0058
133 #define GRF_BT1120_DCLK_DELAY_CON1 0x005c
134 #define GRF_MIPI_TX0_CON 0x0060
135 #define DPIUPDATECFG BIT(26)
136 #define DPICOLORM BIT(25)
137 #define DPISHUTDN BIT(24)
138 #define CSI_PHYRSTZ BIT(21)
139 #define CSI_PHYSHUTDOWNZ BIT(20)
140 #define FORCETXSTOPMODE_MASK GENMASK(19, 16)
141 #define FORCETXSTOPMODE(x) UPDATE(x, 19, 16)
142 #define FORCERXMODE_MASK GENMASK(15, 12)
143 #define FORCERXMODE(x) UPDATE(x, 15, 12)
144 #define PHY_TESTCLR BIT(10)
145 #define PHY_TESTCLK BIT(9)
146 #define PHY_TESTEN BIT(8)
147 #define PHY_TESTDIN_MASK GENMASK(7, 0)
148 #define PHY_TESTDIN(x) UPDATE(x, 7, 0)
149 #define GRF_DPHY0_STATUS 0x0064
150 #define DPHY_PHYLOCK BIT(24)
151 #define PHY_TESTDOUT_SHIFT 8
152 #define GRF_MIPI_TX1_CON 0x0068
153 #define GRF_DPHY1_STATUS 0x006c
154 #define GRF_GPIO0AB_SEL_CON 0x0070
155 #define GRF_GPIO1AB_SEL_CON 0x0074
156 #define GRF_GPIO2AB_SEL_CON 0x0078
157 #define GRF_GPIO2C_SEL_CON 0x007c
158 #define GRF_GPIO3AB_SEL_CON 0x0080
159 #define GRF_GPIO2A_SMT 0x0090
160 #define GRF_GPIO2B_SMT 0x0094
161 #define GRF_GPIO2C_SMT 0x0098
162 #define GRF_GPIO3AB_SMT 0x009c
163 #define GRF_GPIO0A_P_CON 0x00a0
164 #define GRF_GPIO1A_P_CON 0x00a4
165 #define GRF_GPIO2A_P_CON 0x00a8
166 #define GRF_GPIO2B_P_CON 0x00ac
167 #define GRF_GPIO2C_P_CON 0x00b0
168 #define GRF_GPIO3A_P_CON 0x00b4
169 #define GRF_GPIO3B_P_CON 0x00b8
170 #define GRF_GPIO0B_D_CON 0x00c0
171 #define GRF_GPIO1B_D_CON 0x00c4
172 #define GRF_GPIO2A_D0_CON 0x00c8
173 #define GRF_GPIO2A_D1_CON 0x00cc
174 #define GRF_GPIO2B_D0_CON 0x00d0
175 #define GRF_GPIO2B_D1_CON 0x00d4
176 #define GRF_GPIO2C_D0_CON 0x00d8
177 #define GRF_GPIO2C_D1_CON 0x00dc
178 #define GRF_GPIO3A_D0_CON 0x00e0
179 #define GRF_GPIO3A_D1_CON 0x00e4
180 #define GRF_GPIO3B_D_CON 0x00e8
181 #define GRF_GPIO_SR_CON 0x00ec
182 #define GRF_INTR0_EN 0x0100
183 #define GRF_INTR0_CLR_EN 0x0104
184 #define GRF_INTR0_STATUS 0x0108
185 #define GRF_INTR0_RAW_STATUS 0x010c
186 #define GRF_INTR1_EN 0x0110
187 #define GRF_INTR1_CLR_EN 0x0114
188 #define GRF_INTR1_STATUS 0x0118
189 #define GRF_INTR1_RAW_STATUS 0x011c
190 #define GRF_SYSTEM_STATUS0 0x0120
191 /* 0: i2c mode and mcu mode; 1: i2c mode only */
192 #define I2C_ONLY_FLAG BIT(6)
193 #define GRF_SYSTEM_STATUS3 0x012c
194 #define GRF_SYSTEM_STATUS4 0x0130
195 #define GRF_OS_REG0 0x0140
196 #define GRF_OS_REG1 0x0144
197 #define GRF_OS_REG2 0x0148
198 #define GRF_OS_REG3 0x014c
199 #define GRF_SOC_VERSION 0x0150
200 #define GRF_MAX_REGISTER GRF_SOC_VERSION
201
202 #define DRM_MODE_FLAG_PHSYNC (1<<0)
203 #define DRM_MODE_FLAG_NHSYNC (1<<1)
204 #define DRM_MODE_FLAG_PVSYNC (1<<2)
205 #define DRM_MODE_FLAG_NVSYNC (1<<3)
206
207 enum {
208 COMBTXPHY_MODULEA_EN = BIT(0),
209 COMBTXPHY_MODULEB_EN = BIT(1),
210 };
211
212 enum {
213 RK628_DEV_GRF,
214 RK628_DEV_COMBRXPHY,
215 RK628_DEV_HDMIRX = 3,
216 RK628_DEV_CSI,
217 RK628_DEV_DSI0,
218 RK628_DEV_DSI1,
219 RK628_DEV_HDMITX,
220 RK628_DEV_GVI,
221 RK628_DEV_COMBTXPHY,
222 RK628_DEV_ADAPTER,
223 RK628_DEV_EFUSE,
224 RK628_DEV_CRU,
225 RK628_DEV_GPIO0,
226 RK628_DEV_GPIO1,
227 RK628_DEV_GPIO2,
228 RK628_DEV_GPIO3,
229 RK628_DEV_MAX,
230 };
231
232 enum rk628_input_mode {
233 INPUT_MODE_HDMI,
234 INPUT_MODE_BT1120 = 2,
235 INPUT_MODE_RGB,
236 INPUT_MODE_YUV,
237 };
238
239
240 enum rk628_output_mode {
241 OUTPUT_MODE_GVI = 1,
242 OUTPUT_MODE_LVDS,
243 OUTPUT_MODE_HDMI,
244 OUTPUT_MODE_CSI,
245 OUTPUT_MODE_DSI,
246 OUTPUT_MODE_BT1120 = 8,
247 OUTPUT_MODE_RGB = 16,
248 OUTPUT_MODE_YUV = 24,
249 };
250
251 enum phy_mode {
252 PHY_MODE_INVALID,
253 PHY_MODE_VIDEO_MIPI,
254 PHY_MODE_VIDEO_LVDS,
255 PHY_MODE_VIDEO_GVI,
256 };
257
258 enum lvds_format {
259 LVDS_FORMAT_VESA_24BIT,
260 LVDS_FORMAT_JEIDA_24BIT,
261 LVDS_FORMAT_JEIDA_18BIT,
262 LVDS_FORMAT_VESA_18BIT,
263 };
264
265 enum lvds_link_type {
266 LVDS_SINGLE_LINK,
267 LVDS_DUAL_LINK_ODD_EVEN_PIXELS,
268 LVDS_DUAL_LINK_EVEN_ODD_PIXELS,
269 LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS,
270 LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS,
271 };
272
273 enum gvi_color_depth {
274 COLOR_DEPTH_RGB_YUV444_18BIT,
275 COLOR_DEPTH_RGB_YUV444_24BIT,
276 COLOR_DEPTH_RGB_YUV444_30BIT,
277 COLOR_DEPTH_YUV422_16BIT = 8,
278 COLOR_DEPTH_YUV422_20BIT,
279 };
280
281 enum dsi_mode_flags {
282 MIPI_DSI_MODE_VIDEO = 1,
283 MIPI_DSI_MODE_VIDEO_BURST = 2,
284 MIPI_DSI_MODE_VIDEO_SYNC_PULSE = 4,
285 MIPI_DSI_MODE_VIDEO_HFP = 8,
286 MIPI_DSI_MODE_VIDEO_HBP = 16,
287 MIPI_DSI_MODE_EOT_PACKET = 32,
288 MIPI_DSI_CLOCK_NON_CONTINUOUS = 64,
289 MIPI_DSI_MODE_LPM = 128,
290 };
291
292 enum dsi_bus_format {
293 MIPI_DSI_FMT_RGB888,
294 MIPI_DSI_FMT_RGB666,
295 MIPI_DSI_FMT_RGB666_PACKED,
296 MIPI_DSI_FMT_RGB565,
297 };
298
299 enum gvi_bus_format {
300 GVI_MEDIA_BUS_FMT_RGB666_1X18 = 9,
301 GVI_MEDIA_BUS_FMT_RGB888_1X24 = 10,
302 GVI_MEDIA_BUS_FMT_YUYV10_1X20 = 13,
303 GVI_MEDIA_BUS_FMT_YUYV8_1X16 = 17,
304 GVI_MEDIA_BUS_FMT_RGB101010_1X30 = 24,
305 };
306
307 enum bus_format {
308 BUS_FMT_RGB = 0,
309 BUS_FMT_YUV422 = 1,
310 BUS_FMT_YUV444 = 2,
311 BUS_FMT_YUV420 = 3,
312 BUS_FMT_UNKNOWN,
313 };
314
315 enum rk628_mode_sync_pol {
316 MODE_FLAG_NSYNC,
317 MODE_FLAG_PSYNC,
318 };
319
320 #undef BT1120_DUAL_EDGE
321
322 struct rk628_videomode {
323 u32 pixelclock; /* pixelclock in Hz */
324
325 u32 hactive;
326 u32 hfront_porch;
327 u32 hback_porch;
328 u32 hsync_len;
329
330 u32 vactive;
331 u32 vfront_porch;
332 u32 vback_porch;
333 u32 vsync_len;
334
335 unsigned int flags; /* display flags */
336 };
337
338 struct rk628_display_mode {
339 int clock; /* in kHz */
340 int hdisplay;
341 int hsync_start;
342 int hsync_end;
343 int htotal;
344 int vdisplay;
345 int vsync_start;
346 int vsync_end;
347 int vtotal;
348 unsigned int flags;
349 };
350
351 struct cmd_ctrl_hdr {
352 u8 dtype; /* data type */
353 u8 wait; /* ms */
354 u8 dlen; /* payload len */
355 } __packed;
356
357 struct cmd_desc {
358 struct cmd_ctrl_hdr dchdr;
359 u8 *payload;
360 };
361
362 struct panel_cmds {
363 u8 *buf;
364 int blen;
365 struct cmd_desc *cmds;
366 int cmd_cnt;
367 };
368
369 struct panel_simple {
370 struct backlight_device *backlight;
371
372 struct regulator *supply;
373 struct gpio_desc *enable_gpio;
374 struct gpio_desc *reset_gpio;
375 struct panel_cmds *on_cmds;
376 struct panel_cmds *off_cmds;
377 };
378
379 struct rk628_dsi {
380 int bpp; /* 24/18/16*/
381 enum dsi_bus_format bus_format;
382 enum dsi_mode_flags mode_flags;
383 bool slave;
384 bool master;
385 uint8_t channel;
386 uint8_t lanes;
387 uint8_t id; /* 0:dsi0 1:dsi1 */
388 struct rk628 *rk628;
389 };
390
391 struct rk628_lvds {
392 enum lvds_format format;
393 enum lvds_link_type link_type;
394 };
395
396 struct rk628_gvi {
397 enum gvi_bus_format bus_format;
398 enum gvi_color_depth color_depth;
399 uint8_t lanes;
400 bool division_mode;
401 bool frm_rst;
402 u8 byte_mode;
403 };
404
405 struct rk628_combtxphy {
406 enum phy_mode mode;
407 unsigned int flags;
408 u8 ref_div;
409 u8 fb_div;
410 u16 frac_div;
411 u8 rate_div;
412 u32 bus_width;
413 bool division_mode;
414 };
415
416 struct rk628 {
417 struct device *dev;
418 struct i2c_client *client;
419 struct regmap *regmap[RK628_DEV_MAX];
420 struct gpio_desc *reset_gpio;
421 struct gpio_desc *enable_gpio;
422 struct gpio_desc *plugin_det_gpio;
423 int plugin_irq;
424 int hdmirx_irq;
425 struct clk *soc_24M;
426 struct workqueue_struct *monitor_wq;
427 struct delayed_work delay_work;
428 struct workqueue_struct *dsi_wq;
429 struct delayed_work dsi_delay_work;
430 struct panel_simple *panel;
431 void *hdmirx;
432 bool display_enabled;
433 enum rk628_input_mode input_mode;
434 enum rk628_output_mode output_mode;
435 struct rk628_display_mode src_mode;
436 struct rk628_display_mode dst_mode;
437 enum bus_format input_fmt;
438 enum bus_format output_fmt;
439 struct rk628_dsi dsi0;
440 struct rk628_dsi dsi1;
441 struct rk628_lvds lvds;
442 struct rk628_gvi gvi;
443 struct rk628_combtxphy combtxphy;
444 int sync_pol;
445 void *csi;
446 };
447
rk628_i2c_write(struct rk628 * rk628,u32 reg,u32 val)448 static inline int rk628_i2c_write(struct rk628 *rk628, u32 reg, u32 val)
449 {
450 int region = (reg >> 16) & 0xff;
451 int ret = 0;
452
453 ret = regmap_write(rk628->regmap[region], reg, val);
454 if (ret < 0)
455 pr_info("%s: i2c err reg=0x%x, val=0x%x, ret=%d\n", __func__, reg, val, ret);
456
457 return ret;
458 }
459
rk628_i2c_read(struct rk628 * rk628,u32 reg,u32 * val)460 static inline int rk628_i2c_read(struct rk628 *rk628, u32 reg, u32 *val)
461 {
462 int region = (reg >> 16) & 0xff;
463 int ret = 0;
464
465 ret = regmap_read(rk628->regmap[region], reg, val);
466 if (ret < 0)
467 pr_info("%s: i2c err reg=0x%x, val=0x%x ret=%d\n", __func__, reg, *val, ret);
468
469 return ret;
470 }
471
rk628_i2c_update_bits(struct rk628 * rk628,u32 reg,u32 mask,u32 val)472 static inline int rk628_i2c_update_bits(struct rk628 *rk628, u32 reg, u32 mask,
473 u32 val)
474 {
475 int region = (reg >> 16) & 0xff;
476
477 return regmap_update_bits(rk628->regmap[region], reg, mask, val);
478 }
479
480 #include "rk628_grf.h"
481 #include "rk628_gpio.h"
482 #include "rk628_pinctrl.h"
483
484 #endif
485