1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/i2c.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/regmap.h>
15 #include <linux/backlight.h>
16 #include <linux/pm_runtime.h>
17 #include <video/videomode.h>
18 #include <linux/debugfs.h>
19
20 #include "rk628.h"
21 #include "rk628_cru.h"
22 #include "rk628_combrxphy.h"
23 #include "rk628_post_process.h"
24 #include "rk628_hdmirx.h"
25 #include "rk628_combtxphy.h"
26 #include "rk628_dsi.h"
27 #include "rk628_rgb.h"
28 #include "rk628_lvds.h"
29 #include "rk628_gvi.h"
30 #include "rk628_csi.h"
31 #include "rk628_hdmitx.h"
32
33 static const struct regmap_range rk628_cru_readable_ranges[] = {
34 regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
35 regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4),
36 regmap_reg_range(CRU_MODE_CON00, CRU_MODE_CON00),
37 regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21),
38 regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05),
39 regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04),
40 };
41
42 static const struct regmap_access_table rk628_cru_readable_table = {
43 .yes_ranges = rk628_cru_readable_ranges,
44 .n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges),
45 };
46
47 static const struct regmap_range rk628_combrxphy_readable_ranges[] = {
48 regmap_reg_range(COMBRX_REG(0x6600), COMBRX_REG(0x665b)),
49 regmap_reg_range(COMBRX_REG(0x66a0), COMBRX_REG(0x66db)),
50 regmap_reg_range(COMBRX_REG(0x66f0), COMBRX_REG(0x66ff)),
51 regmap_reg_range(COMBRX_REG(0x6700), COMBRX_REG(0x6790)),
52 };
53
54 static const struct regmap_access_table rk628_combrxphy_readable_table = {
55 .yes_ranges = rk628_combrxphy_readable_ranges,
56 .n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges),
57 };
58
59 static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
60 regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_SETUP_CTRL),
61 regmap_reg_range(HDMI_RX_HDMI_PCB_CTRL, HDMI_RX_HDMI_PCB_CTRL),
62 regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERROR_PROTECT),
63 regmap_reg_range(HDMI_RX_HDMI_SYNC_CTRL, HDMI_RX_HDMI_CKM_RESULT),
64 regmap_reg_range(HDMI_RX_HDMI_RESMPL_CTRL, HDMI_RX_HDMI_RESMPL_CTRL),
65 regmap_reg_range(HDMI_RX_HDMI_VM_CFG_CH2, HDMI_RX_HDMI_STS),
66 regmap_reg_range(HDMI_RX_HDCP_CTRL, HDMI_RX_HDCP_SETTINGS),
67 regmap_reg_range(HDMI_RX_HDCP_KIDX, HDMI_RX_HDCP_KIDX),
68 regmap_reg_range(HDMI_RX_HDCP_DBG, HDMI_RX_HDCP_AN0),
69 regmap_reg_range(HDMI_RX_HDCP_STS, HDMI_RX_HDCP_STS),
70 regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_HACT_PX),
71 regmap_reg_range(HDMI_RX_MD_VCTRL, HDMI_RX_MD_VSC),
72 regmap_reg_range(HDMI_RX_MD_VOL, HDMI_RX_MD_VTL),
73 regmap_reg_range(HDMI_RX_MD_IL_POL, HDMI_RX_MD_STS),
74 regmap_reg_range(HDMI_RX_AUD_CTRL, HDMI_RX_AUD_CTRL),
75 regmap_reg_range(HDMI_RX_AUD_PLL_CTRL, HDMI_RX_AUD_PLL_CTRL),
76 regmap_reg_range(HDMI_RX_AUD_CLK_CTRL, HDMI_RX_AUD_CLK_CTRL),
77 regmap_reg_range(HDMI_RX_AUD_FIFO_CTRL, HDMI_RX_AUD_FIFO_TH),
78 regmap_reg_range(HDMI_RX_AUD_CHEXTR_CTRL, HDMI_RX_AUD_PAO_CTRL),
79 regmap_reg_range(HDMI_RX_AUD_FIFO_STS, HDMI_RX_AUD_FIFO_STS),
80 regmap_reg_range(HDMI_RX_AUDPLL_GEN_CTS, HDMI_RX_AUDPLL_GEN_N),
81 regmap_reg_range(HDMI_RX_PDEC_CTRL, HDMI_RX_PDEC_CTRL),
82 regmap_reg_range(HDMI_RX_PDEC_AUDIODET_CTRL, HDMI_RX_PDEC_AUDIODET_CTRL),
83 regmap_reg_range(HDMI_RX_PDEC_ERR_FILTER, HDMI_RX_PDEC_ASP_CTRL),
84 regmap_reg_range(HDMI_RX_PDEC_STS, HDMI_RX_PDEC_STS),
85 regmap_reg_range(HDMI_RX_PDEC_GCP_AVMUTE, HDMI_RX_PDEC_GCP_AVMUTE),
86 regmap_reg_range(HDMI_RX_PDEC_ACR_CTS, HDMI_RX_PDEC_ACR_N),
87 regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_AIF_PB0),
88 regmap_reg_range(HDMI_RX_PDEC_AVI_PB, HDMI_RX_PDEC_AVI_PB),
89 regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
90 regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS2),
91 regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA0),
92 regmap_reg_range(HDMI_RX_PDEC_ISTS, HDMI_RX_PDEC_IEN),
93 regmap_reg_range(HDMI_RX_AUD_FIFO_ISTS, HDMI_RX_AUD_FIFO_IEN),
94 regmap_reg_range(HDMI_RX_MD_ISTS, HDMI_RX_MD_IEN),
95 regmap_reg_range(HDMI_RX_HDMI_ISTS, HDMI_RX_HDMI_IEN),
96 regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
97 };
98
99 static const struct regmap_access_table rk628_hdmirx_readable_table = {
100 .yes_ranges = rk628_hdmirx_readable_ranges,
101 .n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
102 };
103
104 static const struct regmap_range rk628_key_readable_ranges[] = {
105 regmap_reg_range(EDID_BASE, EDID_BASE + 0x400),
106 };
107
108 static const struct regmap_access_table rk628_key_readable_table = {
109 .yes_ranges = rk628_key_readable_ranges,
110 .n_yes_ranges = ARRAY_SIZE(rk628_key_readable_ranges),
111 };
112
113 static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
114 regmap_reg_range(COMBTXPHY_BASE, COMBTXPHY_CON10),
115 };
116
117 static const struct regmap_access_table rk628_combtxphy_readable_table = {
118 .yes_ranges = rk628_combtxphy_readable_ranges,
119 .n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
120 };
121
122 static const struct regmap_range rk628_dsi0_readable_ranges[] = {
123 regmap_reg_range(DSI0_BASE, DSI0_BASE + DSI_MAX_REGISTER),
124 };
125
126 static const struct regmap_access_table rk628_dsi0_readable_table = {
127 .yes_ranges = rk628_dsi0_readable_ranges,
128 .n_yes_ranges = ARRAY_SIZE(rk628_dsi0_readable_ranges),
129 };
130
131 static const struct regmap_range rk628_dsi1_readable_ranges[] = {
132 regmap_reg_range(DSI1_BASE, DSI1_BASE + DSI_MAX_REGISTER),
133 };
134
135 static const struct regmap_access_table rk628_dsi1_readable_table = {
136 .yes_ranges = rk628_dsi1_readable_ranges,
137 .n_yes_ranges = ARRAY_SIZE(rk628_dsi1_readable_ranges),
138 };
139
140 static const struct regmap_range rk628_gvi_readable_ranges[] = {
141 regmap_reg_range(GVI_BASE, GVI_BASE + GVI_COLOR_BAR_VTIMING1),
142 };
143
144 static const struct regmap_access_table rk628_gvi_readable_table = {
145 .yes_ranges = rk628_gvi_readable_ranges,
146 .n_yes_ranges = ARRAY_SIZE(rk628_gvi_readable_ranges),
147 };
148
149 static const struct regmap_range rk628_csi_readable_ranges[] = {
150 regmap_reg_range(CSITX_CONFIG_DONE, CSITX_CSITX_VERSION),
151 regmap_reg_range(CSITX_SYS_CTRL0_IMD, CSITX_TIMING_HPW_PADDING_NUM),
152 regmap_reg_range(CSITX_VOP_PATH_CTRL, CSITX_VOP_PATH_CTRL),
153 regmap_reg_range(CSITX_VOP_PATH_PKT_CTRL, CSITX_VOP_PATH_PKT_CTRL),
154 regmap_reg_range(CSITX_CSITX_STATUS0, CSITX_LPDT_DATA_IMD),
155 regmap_reg_range(CSITX_DPHY_CTRL, CSITX_DPHY_CTRL),
156 };
157
158 static const struct regmap_access_table rk628_csi_readable_table = {
159 .yes_ranges = rk628_csi_readable_ranges,
160 .n_yes_ranges = ARRAY_SIZE(rk628_csi_readable_ranges),
161 };
162
163 static const struct regmap_range rk628_hdmi_volatile_reg_ranges[] = {
164 regmap_reg_range(HDMI_SYS_CTRL, HDMI_MAX_REG),
165 };
166
167 static const struct regmap_access_table rk628_hdmi_volatile_regs = {
168 .yes_ranges = rk628_hdmi_volatile_reg_ranges,
169 .n_yes_ranges = ARRAY_SIZE(rk628_hdmi_volatile_reg_ranges),
170 };
171
172 static const struct regmap_range rk628_gpio0_readable_ranges[] = {
173 regmap_reg_range(RK628_GPIO0_BASE, RK628_GPIO0_BASE + GPIO_VER_ID),
174 };
175
176 static const struct regmap_access_table rk628_gpio0_readable_table = {
177 .yes_ranges = rk628_gpio0_readable_ranges,
178 .n_yes_ranges = ARRAY_SIZE(rk628_gpio0_readable_ranges),
179 };
180
181 static const struct regmap_range rk628_gpio1_readable_ranges[] = {
182 regmap_reg_range(RK628_GPIO1_BASE, RK628_GPIO1_BASE + GPIO_VER_ID),
183 };
184
185 static const struct regmap_access_table rk628_gpio1_readable_table = {
186 .yes_ranges = rk628_gpio1_readable_ranges,
187 .n_yes_ranges = ARRAY_SIZE(rk628_gpio1_readable_ranges),
188 };
189
190 static const struct regmap_range rk628_gpio2_readable_ranges[] = {
191 regmap_reg_range(RK628_GPIO2_BASE, RK628_GPIO2_BASE + GPIO_VER_ID),
192 };
193
194 static const struct regmap_access_table rk628_gpio2_readable_table = {
195 .yes_ranges = rk628_gpio2_readable_ranges,
196 .n_yes_ranges = ARRAY_SIZE(rk628_gpio2_readable_ranges),
197 };
198
199 static const struct regmap_range rk628_gpio3_readable_ranges[] = {
200 regmap_reg_range(RK628_GPIO3_BASE, RK628_GPIO3_BASE + GPIO_VER_ID),
201 };
202
203 static const struct regmap_access_table rk628_gpio3_readable_table = {
204 .yes_ranges = rk628_gpio3_readable_ranges,
205 .n_yes_ranges = ARRAY_SIZE(rk628_gpio3_readable_ranges),
206 };
207
208 static const struct regmap_config rk628_regmap_config[RK628_DEV_MAX] = {
209 [RK628_DEV_GRF] = {
210 .name = "grf",
211 .reg_bits = 32,
212 .val_bits = 32,
213 .reg_stride = 4,
214 .max_register = GRF_MAX_REGISTER,
215 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
216 .val_format_endian = REGMAP_ENDIAN_NATIVE,
217 },
218 [RK628_DEV_CRU] = {
219 .name = "cru",
220 .reg_bits = 32,
221 .val_bits = 32,
222 .reg_stride = 4,
223 .max_register = CRU_MAX_REGISTER,
224 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
225 .val_format_endian = REGMAP_ENDIAN_NATIVE,
226 .rd_table = &rk628_cru_readable_table,
227 },
228 [RK628_DEV_COMBRXPHY] = {
229 .name = "combrxphy",
230 .reg_bits = 32,
231 .val_bits = 32,
232 .reg_stride = 4,
233 .max_register = COMBRX_REG(0x6790),
234 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
235 .val_format_endian = REGMAP_ENDIAN_NATIVE,
236 .rd_table = &rk628_combrxphy_readable_table,
237 },
238 [RK628_DEV_HDMIRX] = {
239 .name = "hdmirx",
240 .reg_bits = 32,
241 .val_bits = 32,
242 .reg_stride = 4,
243 .max_register = HDMI_RX_MAX_REGISTER,
244 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
245 .val_format_endian = REGMAP_ENDIAN_NATIVE,
246 .rd_table = &rk628_hdmirx_readable_table,
247 },
248 [RK628_DEV_ADAPTER] = {
249 .name = "adapter",
250 .reg_bits = 32,
251 .val_bits = 32,
252 .reg_stride = 4,
253 .max_register = KEY_MAX_REGISTER,
254 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
255 .val_format_endian = REGMAP_ENDIAN_NATIVE,
256 .rd_table = &rk628_key_readable_table,
257 },
258 [RK628_DEV_COMBTXPHY] = {
259 .name = "combtxphy",
260 .reg_bits = 32,
261 .val_bits = 32,
262 .reg_stride = 4,
263 .max_register = COMBTXPHY_CON10,
264 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
265 .val_format_endian = REGMAP_ENDIAN_NATIVE,
266 .rd_table = &rk628_combtxphy_readable_table,
267 },
268 [RK628_DEV_DSI0] = {
269 .name = "dsi0",
270 .reg_bits = 32,
271 .val_bits = 32,
272 .reg_stride = 4,
273 .max_register = DSI0_BASE + DSI_MAX_REGISTER,
274 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
275 .val_format_endian = REGMAP_ENDIAN_NATIVE,
276 .rd_table = &rk628_dsi0_readable_table,
277 },
278 [RK628_DEV_DSI1] = {
279 .name = "dsi1",
280 .reg_bits = 32,
281 .val_bits = 32,
282 .reg_stride = 4,
283 .max_register = DSI1_BASE + DSI_MAX_REGISTER,
284 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
285 .val_format_endian = REGMAP_ENDIAN_NATIVE,
286 .rd_table = &rk628_dsi1_readable_table,
287 },
288 [RK628_DEV_GVI] = {
289 .name = "gvi",
290 .reg_bits = 32,
291 .val_bits = 32,
292 .reg_stride = 4,
293 .max_register = GVI_COLOR_BAR_VTIMING1,
294 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
295 .val_format_endian = REGMAP_ENDIAN_NATIVE,
296 .rd_table = &rk628_gvi_readable_table,
297 },
298 [RK628_DEV_CSI] = {
299 .name = "csi",
300 .reg_bits = 32,
301 .val_bits = 32,
302 .reg_stride = 4,
303 .max_register = CSI_MAX_REGISTER,
304 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
305 .val_format_endian = REGMAP_ENDIAN_NATIVE,
306 .rd_table = &rk628_csi_readable_table,
307 },
308 [RK628_DEV_HDMITX] = {
309 .name = "hdmi",
310 .reg_bits = 32,
311 .val_bits = 32,
312 .reg_stride = 4,
313 .max_register = HDMI_MAX_REG,
314 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
315 .val_format_endian = REGMAP_ENDIAN_NATIVE,
316 .rd_table = &rk628_hdmi_volatile_regs,
317 },
318 [RK628_DEV_GPIO0] = {
319 .name = "gpio0",
320 .reg_bits = 32,
321 .val_bits = 32,
322 .reg_stride = 4,
323 .max_register = RK628_GPIO0_BASE + GPIO_VER_ID,
324 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
325 .val_format_endian = REGMAP_ENDIAN_NATIVE,
326 .rd_table = &rk628_gpio0_readable_table,
327 },
328 [RK628_DEV_GPIO1] = {
329 .name = "gpio1",
330 .reg_bits = 32,
331 .val_bits = 32,
332 .reg_stride = 4,
333 .max_register = RK628_GPIO1_BASE + GPIO_VER_ID,
334 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
335 .val_format_endian = REGMAP_ENDIAN_NATIVE,
336 .rd_table = &rk628_gpio1_readable_table,
337 },
338 [RK628_DEV_GPIO2] = {
339 .name = "gpio2",
340 .reg_bits = 32,
341 .val_bits = 32,
342 .reg_stride = 4,
343 .max_register = RK628_GPIO2_BASE + GPIO_VER_ID,
344 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
345 .val_format_endian = REGMAP_ENDIAN_NATIVE,
346 .rd_table = &rk628_gpio2_readable_table,
347 },
348 [RK628_DEV_GPIO3] = {
349 .name = "gpio3",
350 .reg_bits = 32,
351 .val_bits = 32,
352 .reg_stride = 4,
353 .max_register = RK628_GPIO3_BASE + GPIO_VER_ID,
354 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
355 .val_format_endian = REGMAP_ENDIAN_NATIVE,
356 .rd_table = &rk628_gpio3_readable_table,
357 },
358 };
359
rk628_display_disable(struct rk628 * rk628)360 static void rk628_display_disable(struct rk628 *rk628)
361 {
362 if (!rk628->display_enabled)
363 return;
364
365 if (rk628->output_mode == OUTPUT_MODE_CSI)
366 rk628_csi_disable(rk628);
367
368 if (rk628->output_mode == OUTPUT_MODE_GVI)
369 rk628_gvi_disable(rk628);
370
371 if (rk628->output_mode == OUTPUT_MODE_LVDS)
372 rk628_lvds_disable(rk628);
373
374 if (rk628->output_mode == OUTPUT_MODE_DSI)
375 rk628_dsi_disable(rk628);
376
377 rk628_post_process_disable(rk628);
378
379 if (rk628->input_mode == INPUT_MODE_HDMI)
380 rk628_hdmirx_disable(rk628);
381
382 rk628->display_enabled = false;
383 }
384
rk628_display_resume(struct rk628 * rk628)385 static void rk628_display_resume(struct rk628 *rk628)
386 {
387 u8 ret = 0;
388
389 if (rk628->display_enabled)
390 return;
391
392 if (rk628->input_mode == INPUT_MODE_HDMI) {
393 ret = rk628_hdmirx_enable(rk628);
394 if ((ret == HDMIRX_PLUGOUT) || (ret & HDMIRX_NOSIGNAL)) {
395 rk628_display_disable(rk628);
396 return;
397 }
398 }
399
400 if (rk628->input_mode == INPUT_MODE_RGB)
401 rk628_rgb_rx_enable(rk628);
402
403 if (rk628->input_mode == INPUT_MODE_BT1120)
404 rk628_bt1120_rx_enable(rk628);
405
406 rk628_post_process_init(rk628);
407 rk628_post_process_enable(rk628);
408
409 if (rk628->output_mode == OUTPUT_MODE_DSI) {
410 rk628_mipi_dsi_pre_enable(rk628);
411 rk628_mipi_dsi_enable(rk628);
412 }
413
414 if (rk628->output_mode == OUTPUT_MODE_LVDS)
415 rk628_lvds_enable(rk628);
416
417 if (rk628->output_mode == OUTPUT_MODE_GVI)
418 rk628_gvi_enable(rk628);
419
420 if (rk628->output_mode == OUTPUT_MODE_CSI)
421 rk628_csi_enable(rk628);
422
423 #ifdef CONFIG_RK628_MISC_HDMITX
424 if (rk628->output_mode == OUTPUT_MODE_HDMI)
425 rk628_hdmitx_enable(rk628);
426 #endif
427
428 rk628->display_enabled = true;
429 }
430
rk628_display_enable(struct rk628 * rk628)431 static void rk628_display_enable(struct rk628 *rk628)
432 {
433 u8 ret = 0;
434
435 if (rk628->display_enabled)
436 return;
437
438 if (rk628->input_mode == INPUT_MODE_RGB)
439 rk628_rgb_rx_enable(rk628);
440
441 if (rk628->input_mode == INPUT_MODE_BT1120)
442 rk628_bt1120_rx_enable(rk628);
443
444 if (rk628->output_mode == OUTPUT_MODE_BT1120)
445 rk628_bt1120_tx_enable(rk628);
446
447 if (rk628->output_mode == OUTPUT_MODE_DSI)
448 queue_delayed_work(rk628->dsi_wq, &rk628->dsi_delay_work, msecs_to_jiffies(10));
449
450 if (rk628->input_mode == INPUT_MODE_HDMI) {
451 ret = rk628_hdmirx_enable(rk628);
452 if ((ret == HDMIRX_PLUGOUT) || (ret & HDMIRX_NOSIGNAL)) {
453 rk628_display_disable(rk628);
454 return;
455 }
456 }
457
458 if (rk628->output_mode != OUTPUT_MODE_HDMI) {
459 rk628_post_process_init(rk628);
460 rk628_post_process_enable(rk628);
461 }
462
463 if (rk628->output_mode == OUTPUT_MODE_LVDS)
464 rk628_lvds_enable(rk628);
465
466 if (rk628->output_mode == OUTPUT_MODE_GVI)
467 rk628_gvi_enable(rk628);
468
469 if (rk628->output_mode == OUTPUT_MODE_CSI)
470 rk628_csi_enable(rk628);
471
472 #ifdef CONFIG_RK628_MISC_HDMITX
473 if (rk628->output_mode == OUTPUT_MODE_HDMI)
474 rk628_hdmitx_enable(rk628);
475 #endif
476
477 rk628->display_enabled = true;
478 }
479
rk628_display_work(struct work_struct * work)480 static void rk628_display_work(struct work_struct *work)
481 {
482 u8 ret = 0;
483 struct rk628 *rk628 =
484 container_of(work, struct rk628, delay_work.work);
485 int delay = msecs_to_jiffies(2000);
486
487 if (rk628->input_mode == INPUT_MODE_HDMI) {
488 ret = rk628_hdmirx_detect(rk628);
489 if (!(ret & (HDMIRX_CHANGED | HDMIRX_NOLOCK))) {
490 if (!rk628->plugin_det_gpio)
491 queue_delayed_work(rk628->monitor_wq,
492 &rk628->delay_work, delay);
493 else
494 rk628_hdmirx_enable_interrupts(rk628, true);
495 return;
496 }
497 }
498
499 if (ret & HDMIRX_PLUGIN) {
500 /* if resolution or input format change, disable first */
501 rk628_display_disable(rk628);
502 rk628_display_enable(rk628);
503 } else if (ret & HDMIRX_PLUGOUT) {
504 rk628_display_disable(rk628);
505 }
506
507 if (rk628->input_mode == INPUT_MODE_HDMI) {
508 if (!rk628->plugin_det_gpio) {
509 if (ret & HDMIRX_NOLOCK)
510 delay = msecs_to_jiffies(200);
511 queue_delayed_work(rk628->monitor_wq, &rk628->delay_work,
512 delay);
513 } else {
514 rk628_hdmirx_enable_interrupts(rk628, true);
515 }
516 }
517 }
518
rk628_dsi_work(struct work_struct * work)519 static void rk628_dsi_work(struct work_struct *work)
520 {
521 struct rk628 *rk628 = container_of(work, struct rk628, dsi_delay_work.work);
522
523 rk628_mipi_dsi_pre_enable(rk628);
524 rk628_mipi_dsi_enable(rk628);
525 }
526
rk628_hdmirx_plugin_irq(int irq,void * dev_id)527 static irqreturn_t rk628_hdmirx_plugin_irq(int irq, void *dev_id)
528 {
529 struct rk628 *rk628 = dev_id;
530
531 rk628_hdmirx_enable_interrupts(rk628, false);
532 /* clear interrupts */
533 rk628_i2c_write(rk628, HDMI_RX_MD_ICLR, 0xffffffff);
534 rk628_i2c_write(rk628, HDMI_RX_PDEC_ICLR, 0xffffffff);
535 rk628_i2c_write(rk628, GRF_INTR0_CLR_EN, 0x01000100);
536
537 /* control hpd after 50ms */
538 schedule_delayed_work(&rk628->delay_work, HZ / 20);
539
540 return IRQ_HANDLED;
541 }
542
rk628_input_is_rgb(struct rk628 * rk628)543 static bool rk628_input_is_rgb(struct rk628 *rk628)
544 {
545 if (rk628->input_mode == INPUT_MODE_RGB || rk628->input_mode == INPUT_MODE_BT1120)
546 return true;
547
548 return false;
549 }
550
rk628_display_route_info_parse(struct rk628 * rk628)551 static int rk628_display_route_info_parse(struct rk628 *rk628)
552 {
553 struct device_node *np;
554 int ret = 0;
555 u32 val;
556
557 if (of_property_read_bool(rk628->dev->of_node, "rk628,hdmi-in"))
558 rk628->input_mode = INPUT_MODE_HDMI;
559 else if (of_property_read_bool(rk628->dev->of_node, "rk628,rgb-in"))
560 rk628->input_mode = INPUT_MODE_RGB;
561 else if (of_property_read_bool(rk628->dev->of_node, "rk628,bt1120-in"))
562 rk628->input_mode = INPUT_MODE_BT1120;
563 else
564 rk628->input_mode = INPUT_MODE_RGB;
565
566 if (of_find_node_by_name(rk628->dev->of_node, "rk628-dsi")) {
567 np = of_find_node_by_name(rk628->dev->of_node, "rk628-dsi");
568 ret = rk628_dsi_parse(rk628, np);
569 } else if (of_find_node_by_name(rk628->dev->of_node, "rk628-lvds")) {
570 np = of_find_node_by_name(rk628->dev->of_node, "rk628-lvds");
571 ret = rk628_lvds_parse(rk628, np);
572 } else if (of_find_node_by_name(rk628->dev->of_node, "rk628-gvi")) {
573 np = of_find_node_by_name(rk628->dev->of_node, "rk628-gvi");
574 ret = rk628_gvi_parse(rk628, np);
575 } else if (of_find_node_by_name(rk628->dev->of_node, "rk628-bt1120")) {
576 rk628->output_mode = OUTPUT_MODE_BT1120;
577 } else {
578 if (of_property_read_bool(rk628->dev->of_node, "rk628,hdmi-out"))
579 rk628->output_mode = OUTPUT_MODE_HDMI;
580 else if (of_property_read_bool(rk628->dev->of_node, "rk628,csi-out"))
581 rk628->output_mode = OUTPUT_MODE_CSI;
582 }
583
584 if (of_property_read_u32(rk628->dev->of_node, "mode-sync-pol", &val) < 0)
585 rk628->sync_pol = MODE_FLAG_PSYNC;
586 else
587 rk628->sync_pol = (!val ? MODE_FLAG_NSYNC : MODE_FLAG_PSYNC);
588
589 if (rk628_input_is_rgb(rk628) && rk628->output_mode == OUTPUT_MODE_RGB)
590 return -EINVAL;
591
592 return ret;
593 }
594
595 static void
rk628_display_mode_from_videomode(const struct rk628_videomode * vm,struct rk628_display_mode * dmode)596 rk628_display_mode_from_videomode(const struct rk628_videomode *vm,
597 struct rk628_display_mode *dmode)
598 {
599 dmode->hdisplay = vm->hactive;
600 dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
601 dmode->hsync_end = dmode->hsync_start + vm->hsync_len;
602 dmode->htotal = dmode->hsync_end + vm->hback_porch;
603
604 dmode->vdisplay = vm->vactive;
605 dmode->vsync_start = dmode->vdisplay + vm->vfront_porch;
606 dmode->vsync_end = dmode->vsync_start + vm->vsync_len;
607 dmode->vtotal = dmode->vsync_end + vm->vback_porch;
608
609 dmode->clock = vm->pixelclock / 1000;
610 dmode->flags = vm->flags;
611 }
612
613 static void
of_parse_rk628_display_timing(struct device_node * np,struct rk628_videomode * vm)614 of_parse_rk628_display_timing(struct device_node *np, struct rk628_videomode *vm)
615 {
616 u8 val;
617
618 of_property_read_u32(np, "clock-frequency", &vm->pixelclock);
619 of_property_read_u32(np, "hactive", &vm->hactive);
620 of_property_read_u32(np, "hfront-porch", &vm->hfront_porch);
621 of_property_read_u32(np, "hback-porch", &vm->hback_porch);
622 of_property_read_u32(np, "hsync-len", &vm->hsync_len);
623
624 of_property_read_u32(np, "vactive", &vm->vactive);
625 of_property_read_u32(np, "vfront-porch", &vm->vfront_porch);
626 of_property_read_u32(np, "vback-porch", &vm->vback_porch);
627 of_property_read_u32(np, "vsync-len", &vm->vsync_len);
628
629 vm->flags = 0;
630 of_property_read_u8(np, "hsync-active", &val);
631 vm->flags |= val ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
632
633 of_property_read_u8(np, "vsync-active", &val);
634 vm->flags |= val ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
635 }
636
rk628_get_video_mode(struct rk628 * rk628)637 static int rk628_get_video_mode(struct rk628 *rk628)
638 {
639
640 struct device_node *timings_np, *src_np, *dst_np;
641 struct rk628_videomode vm;
642
643 timings_np = of_get_child_by_name(rk628->dev->of_node, "display-timings");
644 if (!timings_np) {
645 dev_info(rk628->dev, "failed to found display timings\n");
646 return -EINVAL;
647 }
648
649 src_np = of_get_child_by_name(timings_np, "src-timing");
650 if (!src_np) {
651 dev_info(rk628->dev, "failed to found src timing\n");
652 of_node_put(timings_np);
653 return -EINVAL;
654 }
655
656 of_parse_rk628_display_timing(src_np, &vm);
657 rk628_display_mode_from_videomode(&vm, &rk628->src_mode);
658 dev_info(rk628->dev, "src mode: %d %d %d %d %d %d %d %d %d 0x%x\n",
659 rk628->src_mode.clock, rk628->src_mode.hdisplay, rk628->src_mode.hsync_start,
660 rk628->src_mode.hsync_end, rk628->src_mode.htotal, rk628->src_mode.vdisplay,
661 rk628->src_mode.vsync_start, rk628->src_mode.vsync_end, rk628->src_mode.vtotal,
662 rk628->src_mode.flags);
663
664 dst_np = of_get_child_by_name(timings_np, "dst-timing");
665 if (!dst_np) {
666 dev_info(rk628->dev, "failed to found dst timing\n");
667 of_node_put(timings_np);
668 of_node_put(src_np);
669 return -EINVAL;
670 }
671
672 of_parse_rk628_display_timing(dst_np, &vm);
673 rk628_display_mode_from_videomode(&vm, &rk628->dst_mode);
674 dev_info(rk628->dev, "dst mode: %d %d %d %d %d %d %d %d %d 0x%x\n",
675 rk628->dst_mode.clock, rk628->dst_mode.hdisplay, rk628->dst_mode.hsync_start,
676 rk628->dst_mode.hsync_end, rk628->dst_mode.htotal, rk628->dst_mode.vdisplay,
677 rk628->dst_mode.vsync_start, rk628->dst_mode.vsync_end, rk628->dst_mode.vtotal,
678 rk628->dst_mode.flags);
679
680 of_node_put(timings_np);
681 of_node_put(src_np);
682 of_node_put(dst_np);
683
684 return 0;
685 }
686
rk628_display_timings_get(struct rk628 * rk628)687 static int rk628_display_timings_get(struct rk628 *rk628)
688 {
689 int ret;
690
691 ret = rk628_get_video_mode(rk628);
692
693 return ret;
694
695 }
696
697 #define DEBUG_PRINT(args...) \
698 do { \
699 if (s) \
700 seq_printf(s, args); \
701 else \
702 pr_info(args); \
703 } while (0)
704
rk628_debugfs_dump(struct seq_file * s,void * data)705 static int rk628_debugfs_dump(struct seq_file *s, void *data)
706 {
707 struct rk628 *rk628 = s->private;
708
709 u32 val;
710 u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
711 u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
712 u32 src_hactive, src_hoffset, src_htotal, src_hs_end;
713 u32 src_vactive, src_voffset, src_vtotal, src_vs_end;
714
715 u32 input_mode, output_mode;
716 char input_s[10];
717 char output_s[13];
718
719 bool r2y, y2r;
720 char csc_mode_r2y_s[10];
721 char csc_mode_y2r_s[10];
722 u32 csc;
723 enum csc_mode {
724 BT601_L,
725 BT709_L,
726 BT601_F,
727 BT2020
728 };
729
730 int sw_hsync_pol, sw_vsync_pol;
731 u32 dsp_frame_v_start, dsp_frame_h_start;
732
733 int sclk_vop_sel = 0;
734 u32 sclk_vop_div;
735 u64 sclk_vop;
736 u32 reg_v;
737 u32 fps;
738
739 u32 imodet_clk;
740 u32 imodet_clk_sel;
741 u32 imodet_clk_div;
742
743 int clk_rx_read_sel = 0;
744 u32 clk_rx_read_div;
745 u64 clk_rx_read;
746
747 u32 tdms_clk_div;
748 u32 tdms_clk;
749 u32 common_tdms_clk[19] = {
750 25170, 27000, 33750, 40000, 59400,
751 65000, 68250, 74250, 83500, 85500,
752 88750, 92812, 101000, 108000, 119000,
753 135000, 148500, 162000, 297000,
754 };
755
756 //get sclk vop
757 rk628_i2c_read(rk628, 0xc0088, ®_v);
758 sclk_vop_sel = (reg_v & 0x20) ? 1 : 0;
759 rk628_i2c_read(rk628, 0xc00b4, ®_v);
760 if (reg_v)
761 sclk_vop_div = reg_v;
762 else
763 sclk_vop_div = 0x10002;
764 /* gpll 983.04MHz */
765 /* cpll 1188MHz */
766 if (sclk_vop_sel)
767 sclk_vop = (u64)983040 * ((sclk_vop_div & 0xffff0000) >> 16);
768 else
769 sclk_vop = (u64)1188000 * ((sclk_vop_div & 0xffff0000) >> 16);
770 do_div(sclk_vop, sclk_vop_div & 0xffff);
771
772 //get rx read clk
773 rk628_i2c_read(rk628, 0xc0088, ®_v);
774 clk_rx_read_sel = (reg_v & 0x10) ? 1 : 0;
775 rk628_i2c_read(rk628, 0xc00b8, ®_v);
776 if (reg_v)
777 clk_rx_read_div = reg_v;
778 else
779 clk_rx_read_div = 0x10002;
780 /* gpll 983.04MHz */
781 /* cpll 1188MHz */
782 if (clk_rx_read_sel)
783 clk_rx_read = (u64)983040 * ((clk_rx_read_div & 0xffff0000) >> 16);
784 else
785 clk_rx_read = (u64)1188000 * ((clk_rx_read_div & 0xffff0000) >> 16);
786 do_div(clk_rx_read, clk_rx_read_div & 0xffff);
787
788 //get imodet clk
789 rk628_i2c_read(rk628, 0xc0094, ®_v);
790 imodet_clk_sel = (reg_v & 0x20) ? 1 : 0;
791
792 if (reg_v)
793 imodet_clk_div = (reg_v & 0x1f) + 1;
794 else
795 imodet_clk_div = 0x18;
796 /* gpll 983.04MHz */
797 /* cpll 1188MHz */
798 if (imodet_clk_sel)
799 imodet_clk = 983040 / imodet_clk_div;
800 else
801 imodet_clk = 1188000 / imodet_clk_div;
802
803 //get input interface type
804 rk628_i2c_read(rk628, GRF_SYSTEM_CON0, &val);
805 input_mode = val & 0x7;
806 output_mode = (val & 0xf8) >> 3;
807 sw_hsync_pol = (val & 0x4000000) ? 1 : 0;
808 sw_vsync_pol = (val & 0x2000000) ? 1 : 0;
809 switch (input_mode) {
810 case 0:
811 strcpy(input_s, "HDMI");
812 break;
813 case 1:
814 strcpy(input_s, "reserved");
815 break;
816 case 2:
817 strcpy(input_s, "BT1120");
818 break;
819 case 3:
820 strcpy(input_s, "RGB");
821 break;
822 case 4:
823 strcpy(input_s, "YUV");
824 break;
825 default:
826 strcpy(input_s, "unknown");
827 }
828 DEBUG_PRINT("input:%s\n", input_s);
829 if (input_mode == 0) {
830 //get tdms clk
831 rk628_i2c_read(rk628, 0x16654, ®_v);
832 reg_v = (reg_v & 0x3f0000) >> 16;
833 if (reg_v >= 0 && reg_v <= 19)
834 tdms_clk = common_tdms_clk[reg_v];
835 else
836 tdms_clk = 148500;
837
838 rk628_i2c_read(rk628, 0x166a8, ®_v);
839 reg_v = (reg_v & 0xf00) >> 8;
840 if (reg_v == 0x6)
841 tdms_clk_div = 1;
842 else if (reg_v == 0x0)
843 tdms_clk_div = 2;
844 else
845 tdms_clk_div = 1;
846
847 //get input hdmi timing
848 //get horizon timing
849 rk628_i2c_read(rk628, 0x30150, ®_v);
850 src_hactive = reg_v & 0xffff;
851
852 rk628_i2c_read(rk628, 0x3014c, ®_v);
853 src_hoffset = (reg_v & 0xffff);
854
855 src_hactive *= tdms_clk_div;
856 src_hoffset *= tdms_clk_div;
857
858 src_htotal = (reg_v & 0xffff0000)>>16;
859 src_htotal *= tdms_clk_div;
860
861 rk628_i2c_read(rk628, 0x30148, ®_v);
862 reg_v = reg_v & 0xffff;
863 src_hs_end = reg_v * tdms_clk * tdms_clk_div / imodet_clk;
864
865 //get vertical timing
866 rk628_i2c_read(rk628, 0x30168, ®_v);
867 src_vactive = reg_v & 0xffff;
868 rk628_i2c_read(rk628, 0x30170, ®_v);
869 src_vtotal = reg_v & 0xffff;
870 rk628_i2c_read(rk628, 0x30164, ®_v);
871 src_voffset = (reg_v & 0xffff);
872
873 rk628_i2c_read(rk628, 0x3015c, ®_v);
874 reg_v = reg_v & 0xffff;
875 src_vs_end = reg_v * clk_rx_read;
876 do_div(src_vs_end, imodet_clk * src_htotal);
877
878 //get fps and print
879 fps = clk_rx_read * 1000;
880 do_div(fps, src_htotal * src_vtotal);
881 DEBUG_PRINT(" Display mode: %dx%dp%d,dclk[%llu],tdms_clk[%d]\n",
882 src_hactive, src_vactive, fps, clk_rx_read, tdms_clk);
883
884 DEBUG_PRINT("\tH: %d %d %d %d\n", src_hactive, src_htotal - src_hoffset,
885 src_htotal - src_hoffset + src_hs_end, src_htotal);
886
887 DEBUG_PRINT("\tV: %d %d %d %d\n", src_vactive,
888 src_vtotal - src_voffset - src_vs_end,
889 src_vtotal - src_voffset, src_vtotal);
890 } else if (input_mode == 2 || input_mode == 3 || input_mode == 4) {
891 //get timing
892 rk628_i2c_read(rk628, 0x130, ®_v);
893 src_hactive = reg_v & 0xffff;
894
895 rk628_i2c_read(rk628, 0x12c, ®_v);
896 src_vactive = (reg_v & 0xffff);
897
898 rk628_i2c_read(rk628, 0x134, ®_v);
899 src_htotal = (reg_v & 0xffff0000) >> 16;
900 src_vtotal = reg_v & 0xffff;
901
902 //get fps and print
903 fps = clk_rx_read * 1000;
904 do_div(fps, src_htotal * src_vtotal);
905 DEBUG_PRINT(" Display mode: %dx%dp%d,dclk[%llu]\n",
906 src_hactive, src_vactive, fps, clk_rx_read);
907
908 DEBUG_PRINT("\tH-total: %d\n", src_htotal);
909
910 DEBUG_PRINT("\tV-total: %d\n", src_vtotal);
911 }
912 //get output interface type
913 switch (output_mode & 0x7) {
914 case 1:
915 strcpy(output_s, "GVI");
916 break;
917 case 2:
918 strcpy(output_s, "LVDS");
919 break;
920 case 3:
921 strcpy(output_s, "HDMI");
922 break;
923 case 4:
924 strcpy(output_s, "CSI");
925 break;
926 case 5:
927 strcpy(output_s, "DSI");
928 break;
929 default:
930 strcpy(output_s, "");
931 }
932 strcpy(output_s + 4, " ");
933 switch (output_mode >> 2) {
934 case 0:
935 strcpy(output_s + 5, "");
936 break;
937 case 1:
938 strcpy(output_s + 5, "BT1120");
939 break;
940 case 2:
941 strcpy(output_s + 5, "RGB");
942 break;
943 case 3:
944 strcpy(output_s + 5, "YUV");
945 break;
946 default:
947 strcpy(output_s + 5, "unknown");
948 }
949 DEBUG_PRINT("output:%s\n", output_s);
950
951 //get output timing
952 rk628_i2c_read(rk628, GRF_SCALER_CON3, &val);
953 dsp_htotal = val & 0xffff;
954 dsp_hs_end = (val & 0xff0000) >> 16;
955
956 rk628_i2c_read(rk628, GRF_SCALER_CON4, &val);
957 dsp_hact_end = val & 0xffff;
958 dsp_hact_st = (val & 0xfff0000) >> 16;
959
960 rk628_i2c_read(rk628, GRF_SCALER_CON5, &val);
961 dsp_vtotal = val & 0xfff;
962 dsp_vs_end = (val & 0xff0000) >> 16;
963
964 rk628_i2c_read(rk628, GRF_SCALER_CON6, &val);
965 dsp_vact_st = (val & 0xfff0000) >> 16;
966 dsp_vact_end = val & 0xfff;
967
968 fps = sclk_vop * 1000;
969 do_div(fps, dsp_vtotal * dsp_htotal);
970
971 DEBUG_PRINT(" Display mode: %dx%dp%d,dclk[%llu]\n",
972 dsp_hact_end - dsp_hact_st, dsp_vact_end - dsp_vact_st, fps, sclk_vop);
973 DEBUG_PRINT("\tH: %d %d %d %d\n", dsp_hact_end - dsp_hact_st,
974 dsp_htotal - dsp_hact_st, dsp_htotal - dsp_hact_st + dsp_hs_end, dsp_htotal);
975 DEBUG_PRINT("\tV: %d %d %d %d\n", dsp_vact_end - dsp_vact_st,
976 dsp_vtotal - dsp_vact_st, dsp_vtotal - dsp_vact_st + dsp_vs_end, dsp_vtotal);
977
978 //get csc and system information
979 rk628_i2c_read(rk628, GRF_CSC_CTRL_CON, &val);
980 r2y = ((val & 0x10) == 0x10);
981 y2r = ((val & 0x1) == 0x1);
982 csc = (val & 0xc0) >> 6;
983 switch (csc) {
984 case BT601_L:
985 strcpy(csc_mode_r2y_s, "BT601_L");
986 break;
987 case BT601_F:
988 strcpy(csc_mode_r2y_s, "BT601_F");
989 break;
990 case BT709_L:
991 strcpy(csc_mode_r2y_s, "BT709_L");
992 break;
993 case BT2020:
994 strcpy(csc_mode_r2y_s, "BT2020");
995 break;
996 }
997
998 csc = (val & 0xc) >> 2;
999 switch (csc) {
1000 case BT601_L:
1001 strcpy(csc_mode_y2r_s, "BT601_L");
1002 break;
1003 case BT601_F:
1004 strcpy(csc_mode_y2r_s, "BT601_F");
1005 break;
1006 case BT709_L:
1007 strcpy(csc_mode_y2r_s, "BT709_L");
1008 break;
1009 case BT2020:
1010 strcpy(csc_mode_y2r_s, "BT2020");
1011 break;
1012
1013 }
1014 DEBUG_PRINT("csc:\n");
1015
1016 if (r2y)
1017 DEBUG_PRINT("\tr2y[1],csc mode:%s\n", csc_mode_r2y_s);
1018 else if (y2r)
1019 DEBUG_PRINT("\ty2r[1],csc mode:%s\n", csc_mode_y2r_s);
1020 else
1021 DEBUG_PRINT("\tnot open\n");
1022
1023 rk628_i2c_read(rk628, GRF_SCALER_CON2, &val);
1024 dsp_frame_h_start = val & 0xffff;
1025 dsp_frame_v_start = (val & 0xffff0000) >> 16;
1026
1027 DEBUG_PRINT("system:\n");
1028 DEBUG_PRINT("\tsw_hsync_pol:%d, sw_vsync_pol:%d\n", sw_hsync_pol, sw_vsync_pol);
1029 DEBUG_PRINT("\tdsp_frame_h_start:%d, dsp_frame_v_start:%d\n",
1030 dsp_frame_h_start, dsp_frame_v_start);
1031
1032 return 0;
1033 }
1034
rk628_debugfs_open(struct inode * inode,struct file * file)1035 static int rk628_debugfs_open(struct inode *inode, struct file *file)
1036 {
1037 struct rk628 *rk628 = inode->i_private;
1038
1039 return single_open(file, rk628_debugfs_dump, rk628);
1040 }
1041
1042
1043 static const struct file_operations rk628_debugfs_summary_fops = {
1044 .owner = THIS_MODULE,
1045 .open = rk628_debugfs_open,
1046 .read = seq_read,
1047 .llseek = seq_lseek,
1048 .release = single_release,
1049
1050 };
1051
1052 static int
rk628_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)1053 rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
1054 {
1055 struct device *dev = &client->dev;
1056 struct rk628 *rk628;
1057 int i, ret;
1058 int err;
1059 unsigned long irq_flags;
1060 struct dentry *debug_dir;
1061
1062 dev_info(dev, "RK628 misc driver version: %s\n", DRIVER_VERSION);
1063
1064 rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
1065 if (!rk628)
1066 return -ENOMEM;
1067
1068 rk628->dev = dev;
1069 rk628->client = client;
1070 i2c_set_clientdata(client, rk628);
1071 rk628->hdmirx_irq = client->irq;
1072
1073 ret = rk628_display_route_info_parse(rk628);
1074 if (ret) {
1075 dev_err(dev, "display route err\n");
1076 return ret;
1077 }
1078
1079 if (rk628->output_mode != OUTPUT_MODE_HDMI &&
1080 rk628->output_mode != OUTPUT_MODE_CSI) {
1081 ret = rk628_display_timings_get(rk628);
1082 if (ret) {
1083 dev_info(dev, "display timings err\n");
1084 return ret;
1085 }
1086 }
1087
1088 rk628->soc_24M = devm_clk_get(dev, "soc_24M");
1089 if (rk628->soc_24M == ERR_PTR(-ENOENT))
1090 rk628->soc_24M = NULL;
1091
1092 if (IS_ERR(rk628->soc_24M)) {
1093 ret = PTR_ERR(rk628->soc_24M);
1094 dev_err(dev, "Unable to get soc_24M: %d\n", ret);
1095 return ret;
1096 }
1097
1098 clk_prepare_enable(rk628->soc_24M);
1099
1100 rk628->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1101 GPIOD_OUT_LOW);
1102 if (IS_ERR(rk628->enable_gpio)) {
1103 ret = PTR_ERR(rk628->enable_gpio);
1104 dev_err(dev, "failed to request enable GPIO: %d\n", ret);
1105 return ret;
1106 }
1107
1108 rk628->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1109 if (IS_ERR(rk628->reset_gpio)) {
1110 ret = PTR_ERR(rk628->reset_gpio);
1111 dev_err(dev, "failed to request reset GPIO: %d\n", ret);
1112 return ret;
1113 }
1114
1115 rk628->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1116 GPIOD_IN);
1117 if (IS_ERR(rk628->plugin_det_gpio)) {
1118 dev_err(rk628->dev, "failed to get hdmirx det gpio\n");
1119 ret = PTR_ERR(rk628->plugin_det_gpio);
1120 return ret;
1121 }
1122
1123 gpiod_set_value(rk628->enable_gpio, 1);
1124 usleep_range(10000, 11000);
1125 gpiod_set_value(rk628->reset_gpio, 0);
1126 usleep_range(10000, 11000);
1127 gpiod_set_value(rk628->reset_gpio, 1);
1128 usleep_range(10000, 11000);
1129 gpiod_set_value(rk628->reset_gpio, 0);
1130 usleep_range(10000, 11000);
1131
1132 for (i = 0; i < RK628_DEV_MAX; i++) {
1133 const struct regmap_config *config = &rk628_regmap_config[i];
1134
1135 if (!config->name)
1136 continue;
1137
1138 rk628->regmap[i] = devm_regmap_init_i2c(client, config);
1139 if (IS_ERR(rk628->regmap[i])) {
1140 ret = PTR_ERR(rk628->regmap[i]);
1141 dev_err(dev, "failed to allocate register map %d: %d\n",
1142 i, ret);
1143 return ret;
1144 }
1145 }
1146
1147 /* selete int io function */
1148 ret = rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, 0x30002000);
1149 if (ret) {
1150 dev_err(dev, "failed to access register: %d\n", ret);
1151 return ret;
1152 }
1153
1154 rk628->monitor_wq = alloc_ordered_workqueue("%s",
1155 WQ_MEM_RECLAIM | WQ_FREEZABLE, "rk628-monitor-wq");
1156 INIT_DELAYED_WORK(&rk628->delay_work, rk628_display_work);
1157
1158 if (rk628->output_mode == OUTPUT_MODE_DSI) {
1159 rk628->dsi_wq = alloc_ordered_workqueue("%s",
1160 WQ_MEM_RECLAIM | WQ_FREEZABLE, "rk628-dsi-wq");
1161 INIT_DELAYED_WORK(&rk628->dsi_delay_work, rk628_dsi_work);
1162 }
1163
1164 rk628_cru_init(rk628);
1165
1166 if (rk628->output_mode == OUTPUT_MODE_CSI)
1167 rk628_csi_init(rk628);
1168
1169 if (rk628->input_mode == INPUT_MODE_HDMI) {
1170 if (rk628->plugin_det_gpio) {
1171 rk628->plugin_irq = gpiod_to_irq(rk628->plugin_det_gpio);
1172 if (rk628->plugin_irq < 0) {
1173 dev_err(rk628->dev, "failed to get plugin det irq\n");
1174 err = rk628->plugin_irq;
1175 return err;
1176 }
1177
1178 err = devm_request_threaded_irq(dev, rk628->plugin_irq, NULL,
1179 rk628_hdmirx_plugin_irq, IRQF_TRIGGER_FALLING |
1180 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rk628_hdmirx", rk628);
1181 if (err) {
1182 dev_err(rk628->dev, "failed to register plugin det irq (%d)\n",
1183 err);
1184 return err;
1185 }
1186
1187 if (rk628->hdmirx_irq) {
1188 irq_flags =
1189 irqd_get_trigger_type(irq_get_irq_data(rk628->hdmirx_irq));
1190 dev_dbg(rk628->dev, "cfg hdmirx irq, flags: %lu!\n", irq_flags);
1191 err = devm_request_threaded_irq(dev, rk628->hdmirx_irq, NULL,
1192 rk628_hdmirx_plugin_irq, irq_flags |
1193 IRQF_ONESHOT, "rk628", rk628);
1194 if (err) {
1195 dev_err(rk628->dev, "request rk628 irq failed! err:%d\n",
1196 err);
1197 return err;
1198 }
1199 /* hdmirx int en */
1200 rk628_i2c_write(rk628, GRF_INTR0_EN, 0x01000100);
1201 rk628_display_enable(rk628);
1202 queue_delayed_work(rk628->monitor_wq, &rk628->delay_work,
1203 msecs_to_jiffies(20));
1204 }
1205 } else {
1206 rk628_display_enable(rk628);
1207 queue_delayed_work(rk628->monitor_wq, &rk628->delay_work,
1208 msecs_to_jiffies(50));
1209 }
1210 } else {
1211 rk628_display_enable(rk628);
1212 }
1213
1214 pm_runtime_enable(dev);
1215 debug_dir = debugfs_create_dir(rk628->dev->driver->name, NULL);
1216 if (!debug_dir)
1217 return 0;
1218
1219 debugfs_create_file("summary", 0400, debug_dir, rk628, &rk628_debugfs_summary_fops);
1220
1221 return 0;
1222 }
1223
rk628_i2c_remove(struct i2c_client * client)1224 static int rk628_i2c_remove(struct i2c_client *client)
1225 {
1226 struct rk628 *rk628 = i2c_get_clientdata(client);
1227 struct device *dev = &client->dev;
1228
1229 if (rk628->output_mode == OUTPUT_MODE_DSI) {
1230 cancel_delayed_work_sync(&rk628->dsi_delay_work);
1231 destroy_workqueue(rk628->dsi_wq);
1232 }
1233
1234 cancel_delayed_work_sync(&rk628->delay_work);
1235 destroy_workqueue(rk628->monitor_wq);
1236 pm_runtime_disable(dev);
1237
1238 return 0;
1239 }
1240
1241 #ifdef CONFIG_PM_SLEEP
rk628_suspend(struct device * dev)1242 static int rk628_suspend(struct device *dev)
1243 {
1244 struct rk628 *rk628 = dev_get_drvdata(dev);
1245
1246 rk628_display_disable(rk628);
1247
1248 return 0;
1249 }
1250
rk628_resume(struct device * dev)1251 static int rk628_resume(struct device *dev)
1252 {
1253 struct rk628 *rk628 = dev_get_drvdata(dev);
1254
1255 rk628_display_resume(rk628);
1256
1257 return 0;
1258 }
1259 #endif
1260
1261 static const struct dev_pm_ops rk628_pm_ops = {
1262 #ifdef CONFIG_PM_SLEEP
1263 .suspend = rk628_suspend,
1264 .resume = rk628_resume,
1265 #endif
1266 };
1267 static const struct of_device_id rk628_of_match[] = {
1268 { .compatible = "rockchip,rk628", },
1269 {}
1270 };
1271 MODULE_DEVICE_TABLE(of, rk628_of_match);
1272
1273 static const struct i2c_device_id rk628_i2c_id[] = {
1274 { "rk628", 0 },
1275 {}
1276 };
1277 MODULE_DEVICE_TABLE(i2c, rk628_i2c_id);
1278
1279 static struct i2c_driver rk628_i2c_driver = {
1280 .driver = {
1281 .name = "rk628",
1282 .of_match_table = of_match_ptr(rk628_of_match),
1283 .pm = &rk628_pm_ops,
1284 },
1285 .probe = rk628_i2c_probe,
1286 .remove = rk628_i2c_remove,
1287 .id_table = rk628_i2c_id,
1288 };
1289
1290 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_RK628
rk628_i2c_driver_init(void)1291 static int __init rk628_i2c_driver_init(void)
1292 {
1293 i2c_add_driver(&rk628_i2c_driver);
1294
1295 return 0;
1296 }
1297 subsys_initcall_sync(rk628_i2c_driver_init);
1298
rk628_i2c_driver_exit(void)1299 static void __exit rk628_i2c_driver_exit(void)
1300 {
1301 i2c_del_driver(&rk628_i2c_driver);
1302 }
1303 module_exit(rk628_i2c_driver_exit);
1304 #else
1305 module_i2c_driver(rk628_i2c_driver);
1306 #endif
1307
1308 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
1309 MODULE_DESCRIPTION("Rockchip RK628 MFD driver");
1310 MODULE_LICENSE("GPL");
1311