1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013-2016, Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * Intel Management Engine Interface (Intel MEI) Linux driver 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MEI_HW_TXE_H_ 8*4882a593Smuzhiyun #define _MEI_HW_TXE_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/irqreturn.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "hw.h" 13*4882a593Smuzhiyun #include "hw-txe-regs.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MEI_TXI_RPM_TIMEOUT 500 /* ms */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Flatten Hierarchy interrupt cause */ 18*4882a593Smuzhiyun #define TXE_INTR_READINESS_BIT 0 /* HISR_INT_0_STS */ 19*4882a593Smuzhiyun #define TXE_INTR_READINESS HISR_INT_0_STS 20*4882a593Smuzhiyun #define TXE_INTR_ALIVENESS_BIT 1 /* HISR_INT_1_STS */ 21*4882a593Smuzhiyun #define TXE_INTR_ALIVENESS HISR_INT_1_STS 22*4882a593Smuzhiyun #define TXE_INTR_OUT_DB_BIT 2 /* HISR_INT_2_STS */ 23*4882a593Smuzhiyun #define TXE_INTR_OUT_DB HISR_INT_2_STS 24*4882a593Smuzhiyun #define TXE_INTR_IN_READY_BIT 8 /* beyond HISR */ 25*4882a593Smuzhiyun #define TXE_INTR_IN_READY BIT(8) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /** 28*4882a593Smuzhiyun * struct mei_txe_hw - txe hardware specifics 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * @mem_addr: SeC and BRIDGE bars 31*4882a593Smuzhiyun * @aliveness: aliveness (power gating) state of the hardware 32*4882a593Smuzhiyun * @readiness: readiness state of the hardware 33*4882a593Smuzhiyun * @slots: number of empty slots 34*4882a593Smuzhiyun * @wait_aliveness_resp: aliveness wait queue 35*4882a593Smuzhiyun * @intr_cause: translated interrupt cause 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun struct mei_txe_hw { 38*4882a593Smuzhiyun void __iomem * const *mem_addr; 39*4882a593Smuzhiyun u32 aliveness; 40*4882a593Smuzhiyun u32 readiness; 41*4882a593Smuzhiyun u32 slots; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun wait_queue_head_t wait_aliveness_resp; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun unsigned long intr_cause; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw) 49*4882a593Smuzhiyun hw_txe_to_mei(struct mei_txe_hw * hw)50*4882a593Smuzhiyunstatic inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw) 51*4882a593Smuzhiyun { 52*4882a593Smuzhiyun return container_of((void *)hw, struct mei_device, hw); 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct mei_device *mei_txe_dev_init(struct pci_dev *pdev); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id); 58*4882a593Smuzhiyun irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* _MEI_HW_TXE_H_ */ 66