1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2012-2020, Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * Intel Management Engine Interface (Intel MEI) Linux driver 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MEI_INTERFACE_H_ 8*4882a593Smuzhiyun #define _MEI_INTERFACE_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/irqreturn.h> 11*4882a593Smuzhiyun #include <linux/pci.h> 12*4882a593Smuzhiyun #include <linux/mei.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "mei_dev.h" 15*4882a593Smuzhiyun #include "client.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * mei_cfg - mei device configuration 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * @fw_status: FW status 21*4882a593Smuzhiyun * @quirk_probe: device exclusion quirk 22*4882a593Smuzhiyun * @kind: MEI head kind 23*4882a593Smuzhiyun * @dma_size: device DMA buffers size 24*4882a593Smuzhiyun * @fw_ver_supported: is fw version retrievable from FW 25*4882a593Smuzhiyun * @hw_trc_supported: does the hw support trc register 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun struct mei_cfg { 28*4882a593Smuzhiyun const struct mei_fw_status fw_status; 29*4882a593Smuzhiyun bool (*quirk_probe)(const struct pci_dev *pdev); 30*4882a593Smuzhiyun const char *kind; 31*4882a593Smuzhiyun size_t dma_size[DMA_DSCR_NUM]; 32*4882a593Smuzhiyun u32 fw_ver_supported:1; 33*4882a593Smuzhiyun u32 hw_trc_supported:1; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MEI_PCI_DEVICE(dev, cfg) \ 38*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ 39*4882a593Smuzhiyun .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 40*4882a593Smuzhiyun .driver_data = (kernel_ulong_t)(cfg), 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define MEI_ME_RPM_TIMEOUT 500 /* ms */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /** 45*4882a593Smuzhiyun * struct mei_me_hw - me hw specific data 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * @cfg: per device generation config and ops 48*4882a593Smuzhiyun * @mem_addr: io memory address 49*4882a593Smuzhiyun * @irq: irq number 50*4882a593Smuzhiyun * @pg_state: power gating state 51*4882a593Smuzhiyun * @d0i3_supported: di03 support 52*4882a593Smuzhiyun * @hbuf_depth: depth of hardware host/write buffer in slots 53*4882a593Smuzhiyun * @read_fws: read FW status register handler 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun struct mei_me_hw { 56*4882a593Smuzhiyun const struct mei_cfg *cfg; 57*4882a593Smuzhiyun void __iomem *mem_addr; 58*4882a593Smuzhiyun int irq; 59*4882a593Smuzhiyun enum mei_pg_state pg_state; 60*4882a593Smuzhiyun bool d0i3_supported; 61*4882a593Smuzhiyun u8 hbuf_depth; 62*4882a593Smuzhiyun int (*read_fws)(const struct mei_device *dev, int where, u32 *val); 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /** 68*4882a593Smuzhiyun * enum mei_cfg_idx - indices to platform specific configurations. 69*4882a593Smuzhiyun * 70*4882a593Smuzhiyun * Note: has to be synchronized with mei_cfg_list[] 71*4882a593Smuzhiyun * 72*4882a593Smuzhiyun * @MEI_ME_UNDEF_CFG: Lower sentinel. 73*4882a593Smuzhiyun * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices. 74*4882a593Smuzhiyun * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10 75*4882a593Smuzhiyun * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6). 76*4882a593Smuzhiyun * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7). 77*4882a593Smuzhiyun * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations 78*4882a593Smuzhiyun * with quirk for Node Manager exclusion. 79*4882a593Smuzhiyun * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer 80*4882a593Smuzhiyun * client platforms. 81*4882a593Smuzhiyun * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer 82*4882a593Smuzhiyun * client platforms (iTouch). 83*4882a593Smuzhiyun * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer 84*4882a593Smuzhiyun * servers platforms with quirk for 85*4882a593Smuzhiyun * SPS firmware exclusion. 86*4882a593Smuzhiyun * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer 87*4882a593Smuzhiyun * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0 88*4882a593Smuzhiyun * servers platforms with quirk for 89*4882a593Smuzhiyun * SPS firmware exclusion. 90*4882a593Smuzhiyun * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer 91*4882a593Smuzhiyun * servers platforms with quirk for 92*4882a593Smuzhiyun * SPS firmware exclusion. 93*4882a593Smuzhiyun * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer 94*4882a593Smuzhiyun * @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer 95*4882a593Smuzhiyun * servers platforms with quirk for 96*4882a593Smuzhiyun * SPS firmware exclusion. 97*4882a593Smuzhiyun * @MEI_ME_NUM_CFG: Upper Sentinel. 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun enum mei_cfg_idx { 100*4882a593Smuzhiyun MEI_ME_UNDEF_CFG, 101*4882a593Smuzhiyun MEI_ME_ICH_CFG, 102*4882a593Smuzhiyun MEI_ME_ICH10_CFG, 103*4882a593Smuzhiyun MEI_ME_PCH6_CFG, 104*4882a593Smuzhiyun MEI_ME_PCH7_CFG, 105*4882a593Smuzhiyun MEI_ME_PCH_CPT_PBG_CFG, 106*4882a593Smuzhiyun MEI_ME_PCH8_CFG, 107*4882a593Smuzhiyun MEI_ME_PCH8_ITOUCH_CFG, 108*4882a593Smuzhiyun MEI_ME_PCH8_SPS_4_CFG, 109*4882a593Smuzhiyun MEI_ME_PCH12_CFG, 110*4882a593Smuzhiyun MEI_ME_PCH12_SPS_4_CFG, 111*4882a593Smuzhiyun MEI_ME_PCH12_SPS_CFG, 112*4882a593Smuzhiyun MEI_ME_PCH12_SPS_ITOUCH_CFG, 113*4882a593Smuzhiyun MEI_ME_PCH15_CFG, 114*4882a593Smuzhiyun MEI_ME_PCH15_SPS_CFG, 115*4882a593Smuzhiyun MEI_ME_NUM_CFG, 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct mei_device *mei_me_dev_init(struct device *parent, 121*4882a593Smuzhiyun const struct mei_cfg *cfg); 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun int mei_me_pg_enter_sync(struct mei_device *dev); 124*4882a593Smuzhiyun int mei_me_pg_exit_sync(struct mei_device *dev); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); 127*4882a593Smuzhiyun irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif /* _MEI_INTERFACE_H_ */ 130