xref: /OK3568_Linux_fs/kernel/drivers/misc/ics932s401.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * A driver for the Integrated Circuits ICS932S401
4*4882a593Smuzhiyun  * Copyright (C) 2008 IBM
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Author: Darrick J. Wong <darrick.wong@oracle.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/jiffies.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/log2.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* Addresses to scan */
19*4882a593Smuzhiyun static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END };
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* ICS932S401 registers */
22*4882a593Smuzhiyun #define ICS932S401_REG_CFG2			0x01
23*4882a593Smuzhiyun #define		ICS932S401_CFG1_SPREAD		0x01
24*4882a593Smuzhiyun #define ICS932S401_REG_CFG7			0x06
25*4882a593Smuzhiyun #define		ICS932S401_FS_MASK		0x07
26*4882a593Smuzhiyun #define	ICS932S401_REG_VENDOR_REV		0x07
27*4882a593Smuzhiyun #define		ICS932S401_VENDOR		1
28*4882a593Smuzhiyun #define		ICS932S401_VENDOR_MASK		0x0F
29*4882a593Smuzhiyun #define		ICS932S401_REV			4
30*4882a593Smuzhiyun #define		ICS932S401_REV_SHIFT		4
31*4882a593Smuzhiyun #define ICS932S401_REG_DEVICE			0x09
32*4882a593Smuzhiyun #define		ICS932S401_DEVICE		11
33*4882a593Smuzhiyun #define	ICS932S401_REG_CTRL			0x0A
34*4882a593Smuzhiyun #define		ICS932S401_MN_ENABLED		0x80
35*4882a593Smuzhiyun #define		ICS932S401_CPU_ALT		0x04
36*4882a593Smuzhiyun #define		ICS932S401_SRC_ALT		0x08
37*4882a593Smuzhiyun #define ICS932S401_REG_CPU_M_CTRL		0x0B
38*4882a593Smuzhiyun #define		ICS932S401_M_MASK		0x3F
39*4882a593Smuzhiyun #define	ICS932S401_REG_CPU_N_CTRL		0x0C
40*4882a593Smuzhiyun #define	ICS932S401_REG_CPU_SPREAD1		0x0D
41*4882a593Smuzhiyun #define ICS932S401_REG_CPU_SPREAD2		0x0E
42*4882a593Smuzhiyun #define		ICS932S401_SPREAD_MASK		0x7FFF
43*4882a593Smuzhiyun #define ICS932S401_REG_SRC_M_CTRL		0x0F
44*4882a593Smuzhiyun #define ICS932S401_REG_SRC_N_CTRL		0x10
45*4882a593Smuzhiyun #define	ICS932S401_REG_SRC_SPREAD1		0x11
46*4882a593Smuzhiyun #define ICS932S401_REG_SRC_SPREAD2		0x12
47*4882a593Smuzhiyun #define ICS932S401_REG_CPU_DIVISOR		0x13
48*4882a593Smuzhiyun #define		ICS932S401_CPU_DIVISOR_SHIFT	4
49*4882a593Smuzhiyun #define ICS932S401_REG_PCISRC_DIVISOR		0x14
50*4882a593Smuzhiyun #define		ICS932S401_SRC_DIVISOR_MASK	0x0F
51*4882a593Smuzhiyun #define		ICS932S401_PCI_DIVISOR_SHIFT	4
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /* Base clock is 14.318MHz */
54*4882a593Smuzhiyun #define BASE_CLOCK				14318
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define NUM_REGS				21
57*4882a593Smuzhiyun #define NUM_MIRRORED_REGS			15
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static int regs_to_copy[NUM_MIRRORED_REGS] = {
60*4882a593Smuzhiyun 	ICS932S401_REG_CFG2,
61*4882a593Smuzhiyun 	ICS932S401_REG_CFG7,
62*4882a593Smuzhiyun 	ICS932S401_REG_VENDOR_REV,
63*4882a593Smuzhiyun 	ICS932S401_REG_DEVICE,
64*4882a593Smuzhiyun 	ICS932S401_REG_CTRL,
65*4882a593Smuzhiyun 	ICS932S401_REG_CPU_M_CTRL,
66*4882a593Smuzhiyun 	ICS932S401_REG_CPU_N_CTRL,
67*4882a593Smuzhiyun 	ICS932S401_REG_CPU_SPREAD1,
68*4882a593Smuzhiyun 	ICS932S401_REG_CPU_SPREAD2,
69*4882a593Smuzhiyun 	ICS932S401_REG_SRC_M_CTRL,
70*4882a593Smuzhiyun 	ICS932S401_REG_SRC_N_CTRL,
71*4882a593Smuzhiyun 	ICS932S401_REG_SRC_SPREAD1,
72*4882a593Smuzhiyun 	ICS932S401_REG_SRC_SPREAD2,
73*4882a593Smuzhiyun 	ICS932S401_REG_CPU_DIVISOR,
74*4882a593Smuzhiyun 	ICS932S401_REG_PCISRC_DIVISOR,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* How often do we reread sensors values? (In jiffies) */
78*4882a593Smuzhiyun #define SENSOR_REFRESH_INTERVAL	(2 * HZ)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* How often do we reread sensor limit values? (In jiffies) */
81*4882a593Smuzhiyun #define LIMIT_REFRESH_INTERVAL	(60 * HZ)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun struct ics932s401_data {
84*4882a593Smuzhiyun 	struct attribute_group	attrs;
85*4882a593Smuzhiyun 	struct mutex		lock;
86*4882a593Smuzhiyun 	char			sensors_valid;
87*4882a593Smuzhiyun 	unsigned long		sensors_last_updated;	/* In jiffies */
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	u8			regs[NUM_REGS];
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun static int ics932s401_probe(struct i2c_client *client,
93*4882a593Smuzhiyun 			 const struct i2c_device_id *id);
94*4882a593Smuzhiyun static int ics932s401_detect(struct i2c_client *client,
95*4882a593Smuzhiyun 			  struct i2c_board_info *info);
96*4882a593Smuzhiyun static int ics932s401_remove(struct i2c_client *client);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun static const struct i2c_device_id ics932s401_id[] = {
99*4882a593Smuzhiyun 	{ "ics932s401", 0 },
100*4882a593Smuzhiyun 	{ }
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ics932s401_id);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static struct i2c_driver ics932s401_driver = {
105*4882a593Smuzhiyun 	.class		= I2C_CLASS_HWMON,
106*4882a593Smuzhiyun 	.driver = {
107*4882a593Smuzhiyun 		.name	= "ics932s401",
108*4882a593Smuzhiyun 	},
109*4882a593Smuzhiyun 	.probe		= ics932s401_probe,
110*4882a593Smuzhiyun 	.remove		= ics932s401_remove,
111*4882a593Smuzhiyun 	.id_table	= ics932s401_id,
112*4882a593Smuzhiyun 	.detect		= ics932s401_detect,
113*4882a593Smuzhiyun 	.address_list	= normal_i2c,
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
ics932s401_update_device(struct device * dev)116*4882a593Smuzhiyun static struct ics932s401_data *ics932s401_update_device(struct device *dev)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
119*4882a593Smuzhiyun 	struct ics932s401_data *data = i2c_get_clientdata(client);
120*4882a593Smuzhiyun 	unsigned long local_jiffies = jiffies;
121*4882a593Smuzhiyun 	int i, temp;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	mutex_lock(&data->lock);
124*4882a593Smuzhiyun 	if (time_before(local_jiffies, data->sensors_last_updated +
125*4882a593Smuzhiyun 		SENSOR_REFRESH_INTERVAL)
126*4882a593Smuzhiyun 		&& data->sensors_valid)
127*4882a593Smuzhiyun 		goto out;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/*
130*4882a593Smuzhiyun 	 * Each register must be read as a word and then right shifted 8 bits.
131*4882a593Smuzhiyun 	 * Not really sure why this is; setting the "byte count programming"
132*4882a593Smuzhiyun 	 * register to 1 does not fix this problem.
133*4882a593Smuzhiyun 	 */
134*4882a593Smuzhiyun 	for (i = 0; i < NUM_MIRRORED_REGS; i++) {
135*4882a593Smuzhiyun 		temp = i2c_smbus_read_word_data(client, regs_to_copy[i]);
136*4882a593Smuzhiyun 		if (temp < 0)
137*4882a593Smuzhiyun 			temp = 0;
138*4882a593Smuzhiyun 		data->regs[regs_to_copy[i]] = temp >> 8;
139*4882a593Smuzhiyun 	}
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	data->sensors_last_updated = local_jiffies;
142*4882a593Smuzhiyun 	data->sensors_valid = 1;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun out:
145*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
146*4882a593Smuzhiyun 	return data;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
show_spread_enabled(struct device * dev,struct device_attribute * devattr,char * buf)149*4882a593Smuzhiyun static ssize_t show_spread_enabled(struct device *dev,
150*4882a593Smuzhiyun 				   struct device_attribute *devattr,
151*4882a593Smuzhiyun 				   char *buf)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)
156*4882a593Smuzhiyun 		return sprintf(buf, "1\n");
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	return sprintf(buf, "0\n");
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /* bit to cpu khz map */
162*4882a593Smuzhiyun static const int fs_speeds[] = {
163*4882a593Smuzhiyun 	266666,
164*4882a593Smuzhiyun 	133333,
165*4882a593Smuzhiyun 	200000,
166*4882a593Smuzhiyun 	166666,
167*4882a593Smuzhiyun 	333333,
168*4882a593Smuzhiyun 	100000,
169*4882a593Smuzhiyun 	400000,
170*4882a593Smuzhiyun 	0,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /* clock divisor map */
174*4882a593Smuzhiyun static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16,
175*4882a593Smuzhiyun 			       24, 40, 120};
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun /* Calculate CPU frequency from the M/N registers. */
calculate_cpu_freq(struct ics932s401_data * data)178*4882a593Smuzhiyun static int calculate_cpu_freq(struct ics932s401_data *data)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	int m, n, freq;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK;
183*4882a593Smuzhiyun 	n = data->regs[ICS932S401_REG_CPU_N_CTRL];
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	/* Pull in bits 8 & 9 from the M register */
186*4882a593Smuzhiyun 	n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1;
187*4882a593Smuzhiyun 	n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	freq = BASE_CLOCK * (n + 8) / (m + 2);
190*4882a593Smuzhiyun 	freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >>
191*4882a593Smuzhiyun 			 ICS932S401_CPU_DIVISOR_SHIFT];
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	return freq;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun 
show_cpu_clock(struct device * dev,struct device_attribute * devattr,char * buf)196*4882a593Smuzhiyun static ssize_t show_cpu_clock(struct device *dev,
197*4882a593Smuzhiyun 			      struct device_attribute *devattr,
198*4882a593Smuzhiyun 			      char *buf)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", calculate_cpu_freq(data));
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
show_cpu_clock_sel(struct device * dev,struct device_attribute * devattr,char * buf)205*4882a593Smuzhiyun static ssize_t show_cpu_clock_sel(struct device *dev,
206*4882a593Smuzhiyun 				  struct device_attribute *devattr,
207*4882a593Smuzhiyun 				  char *buf)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
210*4882a593Smuzhiyun 	int freq;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
213*4882a593Smuzhiyun 		freq = calculate_cpu_freq(data);
214*4882a593Smuzhiyun 	else {
215*4882a593Smuzhiyun 		/* Freq is neatly wrapped up for us */
216*4882a593Smuzhiyun 		int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		freq = fs_speeds[fid];
219*4882a593Smuzhiyun 		if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) {
220*4882a593Smuzhiyun 			switch (freq) {
221*4882a593Smuzhiyun 			case 166666:
222*4882a593Smuzhiyun 				freq = 160000;
223*4882a593Smuzhiyun 				break;
224*4882a593Smuzhiyun 			case 333333:
225*4882a593Smuzhiyun 				freq = 320000;
226*4882a593Smuzhiyun 				break;
227*4882a593Smuzhiyun 			}
228*4882a593Smuzhiyun 		}
229*4882a593Smuzhiyun 	}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", freq);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* Calculate SRC frequency from the M/N registers. */
calculate_src_freq(struct ics932s401_data * data)235*4882a593Smuzhiyun static int calculate_src_freq(struct ics932s401_data *data)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	int m, n, freq;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
240*4882a593Smuzhiyun 	n = data->regs[ICS932S401_REG_SRC_N_CTRL];
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	/* Pull in bits 8 & 9 from the M register */
243*4882a593Smuzhiyun 	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
244*4882a593Smuzhiyun 	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	freq = BASE_CLOCK * (n + 8) / (m + 2);
247*4882a593Smuzhiyun 	freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] &
248*4882a593Smuzhiyun 			 ICS932S401_SRC_DIVISOR_MASK];
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	return freq;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun 
show_src_clock(struct device * dev,struct device_attribute * devattr,char * buf)253*4882a593Smuzhiyun static ssize_t show_src_clock(struct device *dev,
254*4882a593Smuzhiyun 			      struct device_attribute *devattr,
255*4882a593Smuzhiyun 			      char *buf)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", calculate_src_freq(data));
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
show_src_clock_sel(struct device * dev,struct device_attribute * devattr,char * buf)262*4882a593Smuzhiyun static ssize_t show_src_clock_sel(struct device *dev,
263*4882a593Smuzhiyun 				  struct device_attribute *devattr,
264*4882a593Smuzhiyun 				  char *buf)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
267*4882a593Smuzhiyun 	int freq;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
270*4882a593Smuzhiyun 		freq = calculate_src_freq(data);
271*4882a593Smuzhiyun 	else
272*4882a593Smuzhiyun 		/* Freq is neatly wrapped up for us */
273*4882a593Smuzhiyun 		if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT &&
274*4882a593Smuzhiyun 		    data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT)
275*4882a593Smuzhiyun 			freq = 96000;
276*4882a593Smuzhiyun 		else
277*4882a593Smuzhiyun 			freq = 100000;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", freq);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun /* Calculate PCI frequency from the SRC M/N registers. */
calculate_pci_freq(struct ics932s401_data * data)283*4882a593Smuzhiyun static int calculate_pci_freq(struct ics932s401_data *data)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	int m, n, freq;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
288*4882a593Smuzhiyun 	n = data->regs[ICS932S401_REG_SRC_N_CTRL];
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	/* Pull in bits 8 & 9 from the M register */
291*4882a593Smuzhiyun 	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
292*4882a593Smuzhiyun 	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	freq = BASE_CLOCK * (n + 8) / (m + 2);
295*4882a593Smuzhiyun 	freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >>
296*4882a593Smuzhiyun 			 ICS932S401_PCI_DIVISOR_SHIFT];
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	return freq;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
show_pci_clock(struct device * dev,struct device_attribute * devattr,char * buf)301*4882a593Smuzhiyun static ssize_t show_pci_clock(struct device *dev,
302*4882a593Smuzhiyun 			      struct device_attribute *devattr,
303*4882a593Smuzhiyun 			      char *buf)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", calculate_pci_freq(data));
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun 
show_pci_clock_sel(struct device * dev,struct device_attribute * devattr,char * buf)310*4882a593Smuzhiyun static ssize_t show_pci_clock_sel(struct device *dev,
311*4882a593Smuzhiyun 				  struct device_attribute *devattr,
312*4882a593Smuzhiyun 				  char *buf)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
315*4882a593Smuzhiyun 	int freq;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
318*4882a593Smuzhiyun 		freq = calculate_pci_freq(data);
319*4882a593Smuzhiyun 	else
320*4882a593Smuzhiyun 		freq = 33333;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", freq);
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun static ssize_t show_value(struct device *dev,
326*4882a593Smuzhiyun 			  struct device_attribute *devattr,
327*4882a593Smuzhiyun 			  char *buf);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun static ssize_t show_spread(struct device *dev,
330*4882a593Smuzhiyun 			   struct device_attribute *devattr,
331*4882a593Smuzhiyun 			   char *buf);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL);
334*4882a593Smuzhiyun static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL);
335*4882a593Smuzhiyun static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL);
336*4882a593Smuzhiyun static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL);
337*4882a593Smuzhiyun static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL);
338*4882a593Smuzhiyun static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL);
339*4882a593Smuzhiyun static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL);
340*4882a593Smuzhiyun static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL);
341*4882a593Smuzhiyun static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL);
342*4882a593Smuzhiyun static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL);
343*4882a593Smuzhiyun static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun static struct attribute *ics932s401_attr[] = {
346*4882a593Smuzhiyun 	&dev_attr_spread_enabled.attr,
347*4882a593Smuzhiyun 	&dev_attr_cpu_clock_selection.attr,
348*4882a593Smuzhiyun 	&dev_attr_cpu_clock.attr,
349*4882a593Smuzhiyun 	&dev_attr_src_clock_selection.attr,
350*4882a593Smuzhiyun 	&dev_attr_src_clock.attr,
351*4882a593Smuzhiyun 	&dev_attr_pci_clock_selection.attr,
352*4882a593Smuzhiyun 	&dev_attr_pci_clock.attr,
353*4882a593Smuzhiyun 	&dev_attr_usb_clock.attr,
354*4882a593Smuzhiyun 	&dev_attr_ref_clock.attr,
355*4882a593Smuzhiyun 	&dev_attr_cpu_spread.attr,
356*4882a593Smuzhiyun 	&dev_attr_src_spread.attr,
357*4882a593Smuzhiyun 	NULL
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun 
show_value(struct device * dev,struct device_attribute * devattr,char * buf)360*4882a593Smuzhiyun static ssize_t show_value(struct device *dev,
361*4882a593Smuzhiyun 			  struct device_attribute *devattr,
362*4882a593Smuzhiyun 			  char *buf)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun 	int x;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	if (devattr == &dev_attr_usb_clock)
367*4882a593Smuzhiyun 		x = 48000;
368*4882a593Smuzhiyun 	else if (devattr == &dev_attr_ref_clock)
369*4882a593Smuzhiyun 		x = BASE_CLOCK;
370*4882a593Smuzhiyun 	else
371*4882a593Smuzhiyun 		BUG();
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", x);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun 
show_spread(struct device * dev,struct device_attribute * devattr,char * buf)376*4882a593Smuzhiyun static ssize_t show_spread(struct device *dev,
377*4882a593Smuzhiyun 			   struct device_attribute *devattr,
378*4882a593Smuzhiyun 			   char *buf)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun 	struct ics932s401_data *data = ics932s401_update_device(dev);
381*4882a593Smuzhiyun 	int reg;
382*4882a593Smuzhiyun 	unsigned long val;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD))
385*4882a593Smuzhiyun 		return sprintf(buf, "0%%\n");
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	if (devattr == &dev_attr_src_spread)
388*4882a593Smuzhiyun 		reg = ICS932S401_REG_SRC_SPREAD1;
389*4882a593Smuzhiyun 	else if (devattr == &dev_attr_cpu_spread)
390*4882a593Smuzhiyun 		reg = ICS932S401_REG_CPU_SPREAD1;
391*4882a593Smuzhiyun 	else
392*4882a593Smuzhiyun 		BUG();
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	val = data->regs[reg] | (data->regs[reg + 1] << 8);
395*4882a593Smuzhiyun 	val &= ICS932S401_SPREAD_MASK;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	/* Scale 0..2^14 to -0.5. */
398*4882a593Smuzhiyun 	val = 500000 * val / 16384;
399*4882a593Smuzhiyun 	return sprintf(buf, "-0.%lu%%\n", val);
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun /* Return 0 if detection is successful, -ENODEV otherwise */
ics932s401_detect(struct i2c_client * client,struct i2c_board_info * info)403*4882a593Smuzhiyun static int ics932s401_detect(struct i2c_client *client,
404*4882a593Smuzhiyun 			  struct i2c_board_info *info)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun 	struct i2c_adapter *adapter = client->adapter;
407*4882a593Smuzhiyun 	int vendor, device, revision;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
410*4882a593Smuzhiyun 		return -ENODEV;
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	vendor = i2c_smbus_read_word_data(client, ICS932S401_REG_VENDOR_REV);
413*4882a593Smuzhiyun 	vendor >>= 8;
414*4882a593Smuzhiyun 	revision = vendor >> ICS932S401_REV_SHIFT;
415*4882a593Smuzhiyun 	vendor &= ICS932S401_VENDOR_MASK;
416*4882a593Smuzhiyun 	if (vendor != ICS932S401_VENDOR)
417*4882a593Smuzhiyun 		return -ENODEV;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	device = i2c_smbus_read_word_data(client, ICS932S401_REG_DEVICE);
420*4882a593Smuzhiyun 	device >>= 8;
421*4882a593Smuzhiyun 	if (device != ICS932S401_DEVICE)
422*4882a593Smuzhiyun 		return -ENODEV;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	if (revision != ICS932S401_REV)
425*4882a593Smuzhiyun 		dev_info(&adapter->dev, "Unknown revision %d\n", revision);
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	strlcpy(info->type, "ics932s401", I2C_NAME_SIZE);
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	return 0;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun 
ics932s401_probe(struct i2c_client * client,const struct i2c_device_id * id)432*4882a593Smuzhiyun static int ics932s401_probe(struct i2c_client *client,
433*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun 	struct ics932s401_data *data;
436*4882a593Smuzhiyun 	int err;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL);
439*4882a593Smuzhiyun 	if (!data) {
440*4882a593Smuzhiyun 		err = -ENOMEM;
441*4882a593Smuzhiyun 		goto exit;
442*4882a593Smuzhiyun 	}
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	i2c_set_clientdata(client, data);
445*4882a593Smuzhiyun 	mutex_init(&data->lock);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	dev_info(&client->dev, "%s chip found\n", client->name);
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	/* Register sysfs hooks */
450*4882a593Smuzhiyun 	data->attrs.attrs = ics932s401_attr;
451*4882a593Smuzhiyun 	err = sysfs_create_group(&client->dev.kobj, &data->attrs);
452*4882a593Smuzhiyun 	if (err)
453*4882a593Smuzhiyun 		goto exit_free;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	return 0;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun exit_free:
458*4882a593Smuzhiyun 	kfree(data);
459*4882a593Smuzhiyun exit:
460*4882a593Smuzhiyun 	return err;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun 
ics932s401_remove(struct i2c_client * client)463*4882a593Smuzhiyun static int ics932s401_remove(struct i2c_client *client)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun 	struct ics932s401_data *data = i2c_get_clientdata(client);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	sysfs_remove_group(&client->dev.kobj, &data->attrs);
468*4882a593Smuzhiyun 	kfree(data);
469*4882a593Smuzhiyun 	return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun module_i2c_driver(ics932s401_driver);
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun MODULE_AUTHOR("Darrick J. Wong <darrick.wong@oracle.com>");
475*4882a593Smuzhiyun MODULE_DESCRIPTION("ICS932S401 driver");
476*4882a593Smuzhiyun MODULE_LICENSE("GPL");
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun /* IBM IntelliStation Z30 */
479*4882a593Smuzhiyun MODULE_ALIAS("dmi:bvnIBM:*:rn9228:*");
480*4882a593Smuzhiyun MODULE_ALIAS("dmi:bvnIBM:*:rn9232:*");
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun /* IBM x3650/x3550 */
483*4882a593Smuzhiyun MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650*");
484*4882a593Smuzhiyun MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550*");
485