1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * IBM ASM Service Processor Device Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) IBM Corporation, 2004
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Max Asböck <amax@us.ibm.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /* Condor service processor specific hardware definitions */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef __IBMASM_CONDOR_H__
13*4882a593Smuzhiyun #define __IBMASM_CONDOR_H__
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define VENDORID_IBM 0x1014
18*4882a593Smuzhiyun #define DEVICEID_RSA 0x010F
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define GET_MFA_ADDR(x) (x & 0xFFFFFF00)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define MAILBOX_FULL(x) (x & 0x00000001)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define NO_MFAS_AVAILABLE 0xFFFFFFFF
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define INBOUND_QUEUE_PORT 0x40 /* contains address of next free MFA */
28*4882a593Smuzhiyun #define OUTBOUND_QUEUE_PORT 0x44 /* contains address of posted MFA */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define SP_INTR_MASK 0x00000008
31*4882a593Smuzhiyun #define UART_INTR_MASK 0x00000010
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define INTR_STATUS_REGISTER 0x13A0
34*4882a593Smuzhiyun #define INTR_CONTROL_REGISTER 0x13A4
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define SCOUT_COM_A_BASE 0x0000
37*4882a593Smuzhiyun #define SCOUT_COM_B_BASE 0x0100
38*4882a593Smuzhiyun #define SCOUT_COM_C_BASE 0x0200
39*4882a593Smuzhiyun #define SCOUT_COM_D_BASE 0x0300
40*4882a593Smuzhiyun
sp_interrupt_pending(void __iomem * base_address)41*4882a593Smuzhiyun static inline int sp_interrupt_pending(void __iomem *base_address)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
uart_interrupt_pending(void __iomem * base_address)46*4882a593Smuzhiyun static inline int uart_interrupt_pending(void __iomem *base_address)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
ibmasm_enable_interrupts(void __iomem * base_address,int mask)51*4882a593Smuzhiyun static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
54*4882a593Smuzhiyun writel( readl(ctrl_reg) & ~mask, ctrl_reg);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
ibmasm_disable_interrupts(void __iomem * base_address,int mask)57*4882a593Smuzhiyun static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
60*4882a593Smuzhiyun writel( readl(ctrl_reg) | mask, ctrl_reg);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
enable_sp_interrupts(void __iomem * base_address)63*4882a593Smuzhiyun static inline void enable_sp_interrupts(void __iomem *base_address)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun ibmasm_enable_interrupts(base_address, SP_INTR_MASK);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
disable_sp_interrupts(void __iomem * base_address)68*4882a593Smuzhiyun static inline void disable_sp_interrupts(void __iomem *base_address)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun ibmasm_disable_interrupts(base_address, SP_INTR_MASK);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
enable_uart_interrupts(void __iomem * base_address)73*4882a593Smuzhiyun static inline void enable_uart_interrupts(void __iomem *base_address)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun ibmasm_enable_interrupts(base_address, UART_INTR_MASK);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
disable_uart_interrupts(void __iomem * base_address)78*4882a593Smuzhiyun static inline void disable_uart_interrupts(void __iomem *base_address)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun ibmasm_disable_interrupts(base_address, UART_INTR_MASK);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define valid_mfa(mfa) ( (mfa) != NO_MFAS_AVAILABLE )
84*4882a593Smuzhiyun
get_mfa_outbound(void __iomem * base_address)85*4882a593Smuzhiyun static inline u32 get_mfa_outbound(void __iomem *base_address)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun int retry;
88*4882a593Smuzhiyun u32 mfa;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun for (retry=0; retry<=10; retry++) {
91*4882a593Smuzhiyun mfa = readl(base_address + OUTBOUND_QUEUE_PORT);
92*4882a593Smuzhiyun if (valid_mfa(mfa))
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun return mfa;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
set_mfa_outbound(void __iomem * base_address,u32 mfa)98*4882a593Smuzhiyun static inline void set_mfa_outbound(void __iomem *base_address, u32 mfa)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
get_mfa_inbound(void __iomem * base_address)103*4882a593Smuzhiyun static inline u32 get_mfa_inbound(void __iomem *base_address)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (MAILBOX_FULL(mfa))
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return mfa;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
set_mfa_inbound(void __iomem * base_address,u32 mfa)113*4882a593Smuzhiyun static inline void set_mfa_inbound(void __iomem *base_address, u32 mfa)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun writel(mfa, base_address + INBOUND_QUEUE_PORT);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
get_i2o_message(void __iomem * base_address,u32 mfa)118*4882a593Smuzhiyun static inline struct i2o_message *get_i2o_message(void __iomem *base_address, u32 mfa)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return (struct i2o_message *)(GET_MFA_ADDR(mfa) + base_address);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #endif /* __IBMASM_CONDOR_H__ */
124