1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright 2017-2018 HabanaLabs, Ltd. 4*4882a593Smuzhiyun * All Rights Reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef GOYA_PACKETS_H 9*4882a593Smuzhiyun #define GOYA_PACKETS_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PACKET_HEADER_PACKET_ID_SHIFT 56 14*4882a593Smuzhiyun #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum packet_id { 17*4882a593Smuzhiyun PACKET_WREG_32 = 0x1, 18*4882a593Smuzhiyun PACKET_WREG_BULK = 0x2, 19*4882a593Smuzhiyun PACKET_MSG_LONG = 0x3, 20*4882a593Smuzhiyun PACKET_MSG_SHORT = 0x4, 21*4882a593Smuzhiyun PACKET_CP_DMA = 0x5, 22*4882a593Smuzhiyun PACKET_MSG_PROT = 0x7, 23*4882a593Smuzhiyun PACKET_FENCE = 0x8, 24*4882a593Smuzhiyun PACKET_LIN_DMA = 0x9, 25*4882a593Smuzhiyun PACKET_NOP = 0xA, 26*4882a593Smuzhiyun PACKET_STOP = 0xB, 27*4882a593Smuzhiyun MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> 28*4882a593Smuzhiyun PACKET_HEADER_PACKET_ID_SHIFT) + 1 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum goya_dma_direction { 32*4882a593Smuzhiyun DMA_HOST_TO_DRAM, 33*4882a593Smuzhiyun DMA_HOST_TO_SRAM, 34*4882a593Smuzhiyun DMA_DRAM_TO_SRAM, 35*4882a593Smuzhiyun DMA_SRAM_TO_DRAM, 36*4882a593Smuzhiyun DMA_SRAM_TO_HOST, 37*4882a593Smuzhiyun DMA_DRAM_TO_HOST, 38*4882a593Smuzhiyun DMA_DRAM_TO_DRAM, 39*4882a593Smuzhiyun DMA_SRAM_TO_SRAM, 40*4882a593Smuzhiyun DMA_ENUM_MAX 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define GOYA_PKT_CTL_OPCODE_SHIFT 24 44*4882a593Smuzhiyun #define GOYA_PKT_CTL_OPCODE_MASK 0x1F000000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define GOYA_PKT_CTL_EB_SHIFT 29 47*4882a593Smuzhiyun #define GOYA_PKT_CTL_EB_MASK 0x20000000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define GOYA_PKT_CTL_RB_SHIFT 30 50*4882a593Smuzhiyun #define GOYA_PKT_CTL_RB_MASK 0x40000000 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define GOYA_PKT_CTL_MB_SHIFT 31 53*4882a593Smuzhiyun #define GOYA_PKT_CTL_MB_MASK 0x80000000 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* All packets have, at least, an 8-byte header, which contains 56*4882a593Smuzhiyun * the packet type. The kernel driver uses the packet header for packet 57*4882a593Smuzhiyun * validation and to perform any necessary required preparation before 58*4882a593Smuzhiyun * sending them off to the hardware. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun struct goya_packet { 61*4882a593Smuzhiyun __le64 header; 62*4882a593Smuzhiyun /* The rest of the packet data follows. Use the corresponding 63*4882a593Smuzhiyun * packet_XXX struct to deference the data, based on packet type 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun u8 contents[0]; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct packet_nop { 69*4882a593Smuzhiyun __le32 reserved; 70*4882a593Smuzhiyun __le32 ctl; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct packet_stop { 74*4882a593Smuzhiyun __le32 reserved; 75*4882a593Smuzhiyun __le32 ctl; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define GOYA_PKT_WREG32_CTL_REG_OFFSET_SHIFT 0 79*4882a593Smuzhiyun #define GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK 0x0000FFFF 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct packet_wreg32 { 82*4882a593Smuzhiyun __le32 value; 83*4882a593Smuzhiyun __le32 ctl; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct packet_wreg_bulk { 87*4882a593Smuzhiyun __le32 size64; 88*4882a593Smuzhiyun __le32 ctl; 89*4882a593Smuzhiyun __le64 values[0]; /* data starts here */ 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct packet_msg_long { 93*4882a593Smuzhiyun __le32 value; 94*4882a593Smuzhiyun __le32 ctl; 95*4882a593Smuzhiyun __le64 addr; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct packet_msg_short { 99*4882a593Smuzhiyun __le32 value; 100*4882a593Smuzhiyun __le32 ctl; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct packet_msg_prot { 104*4882a593Smuzhiyun __le32 value; 105*4882a593Smuzhiyun __le32 ctl; 106*4882a593Smuzhiyun __le64 addr; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun struct packet_fence { 110*4882a593Smuzhiyun __le32 cfg; 111*4882a593Smuzhiyun __le32 ctl; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_WO_SHIFT 0 115*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_WO_MASK 0x00000001 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_RDCOMP_SHIFT 1 118*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK 0x00000002 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_WRCOMP_SHIFT 2 121*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK 0x00000004 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT 6 124*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000040 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT 20 127*4882a593Smuzhiyun #define GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK 0x00700000 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun struct packet_lin_dma { 130*4882a593Smuzhiyun __le32 tsize; 131*4882a593Smuzhiyun __le32 ctl; 132*4882a593Smuzhiyun __le64 src_addr; 133*4882a593Smuzhiyun __le64 dst_addr; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun struct packet_cp_dma { 137*4882a593Smuzhiyun __le32 tsize; 138*4882a593Smuzhiyun __le32 ctl; 139*4882a593Smuzhiyun __le64 src_addr; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* GOYA_PACKETS_H */ 143