1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright 2018-2020 HabanaLabs, Ltd. 4*4882a593Smuzhiyun * All Rights Reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef GAUDI_H 9*4882a593Smuzhiyun #define GAUDI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SRAM_BAR_ID 0 12*4882a593Smuzhiyun #define CFG_BAR_ID 2 13*4882a593Smuzhiyun #define HBM_BAR_ID 4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */ 16*4882a593Smuzhiyun #define CFG_BAR_SIZE 0x8000000ull /* 128MB */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CFG_BASE 0x7FFC000000ull 19*4882a593Smuzhiyun #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SRAM_BASE_ADDR 0x7FF0000000ull 22*4882a593Smuzhiyun #define SRAM_SIZE 0x1400000 /* 20MB */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define SPI_FLASH_BASE_ADDR 0x7FF8000000ull 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull 27*4882a593Smuzhiyun #define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull 30*4882a593Smuzhiyun #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define DRAM_PHYS_BASE 0x0ull 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ 35*4882a593Smuzhiyun #define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define GAUDI_MSI_ENTRIES 32 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MAX_ASID 1024 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define PROT_BITS_OFFS 0xF80 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MME_NUMBER_OF_MASTER_ENGINES 2 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MME_NUMBER_OF_SLAVE_ENGINES 2 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define TPC_NUMBER_OF_ENGINES 8 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define DMA_NUMBER_OF_CHANNELS 8 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define NIC_NUMBER_OF_MACROS 5 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define NUMBER_OF_IF 8 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define DEVICE_CACHE_LINE_SIZE 128 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* GAUDI_H */ 62