1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * at24.c - handle most I2C EEPROMs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2005-2007 David Brownell
6*4882a593Smuzhiyun * Copyright (C) 2008 Wolfram Sang, Pengutronix
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/acpi.h>
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/capability.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/jiffies.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/mutex.h>
20*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
21*4882a593Smuzhiyun #include <linux/of_device.h>
22*4882a593Smuzhiyun #include <linux/pm_runtime.h>
23*4882a593Smuzhiyun #include <linux/property.h>
24*4882a593Smuzhiyun #include <linux/regmap.h>
25*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Address pointer is 16 bit. */
29*4882a593Smuzhiyun #define AT24_FLAG_ADDR16 BIT(7)
30*4882a593Smuzhiyun /* sysfs-entry will be read-only. */
31*4882a593Smuzhiyun #define AT24_FLAG_READONLY BIT(6)
32*4882a593Smuzhiyun /* sysfs-entry will be world-readable. */
33*4882a593Smuzhiyun #define AT24_FLAG_IRUGO BIT(5)
34*4882a593Smuzhiyun /* Take always 8 addresses (24c00). */
35*4882a593Smuzhiyun #define AT24_FLAG_TAKE8ADDR BIT(4)
36*4882a593Smuzhiyun /* Factory-programmed serial number. */
37*4882a593Smuzhiyun #define AT24_FLAG_SERIAL BIT(3)
38*4882a593Smuzhiyun /* Factory-programmed mac address. */
39*4882a593Smuzhiyun #define AT24_FLAG_MAC BIT(2)
40*4882a593Smuzhiyun /* Does not auto-rollover reads to the next slave address. */
41*4882a593Smuzhiyun #define AT24_FLAG_NO_RDROL BIT(1)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
45*4882a593Smuzhiyun * Differences between different vendor product lines (like Atmel AT24C or
46*4882a593Smuzhiyun * MicroChip 24LC, etc) won't much matter for typical read/write access.
47*4882a593Smuzhiyun * There are also I2C RAM chips, likewise interchangeable. One example
48*4882a593Smuzhiyun * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes).
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * However, misconfiguration can lose data. "Set 16-bit memory address"
51*4882a593Smuzhiyun * to a part with 8-bit addressing will overwrite data. Writing with too
52*4882a593Smuzhiyun * big a page size also loses data. And it's not safe to assume that the
53*4882a593Smuzhiyun * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC
54*4882a593Smuzhiyun * uses 0x51, for just one example.
55*4882a593Smuzhiyun *
56*4882a593Smuzhiyun * Accordingly, explicit board-specific configuration data should be used
57*4882a593Smuzhiyun * in almost all cases. (One partial exception is an SMBus used to access
58*4882a593Smuzhiyun * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.)
59*4882a593Smuzhiyun *
60*4882a593Smuzhiyun * So this driver uses "new style" I2C driver binding, expecting to be
61*4882a593Smuzhiyun * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or
62*4882a593Smuzhiyun * similar kernel-resident tables; or, configuration data coming from
63*4882a593Smuzhiyun * a bootloader.
64*4882a593Smuzhiyun *
65*4882a593Smuzhiyun * Other than binding model, current differences from "eeprom" driver are
66*4882a593Smuzhiyun * that this one handles write access and isn't restricted to 24c02 devices.
67*4882a593Smuzhiyun * It also handles larger devices (32 kbit and up) with two-byte addresses,
68*4882a593Smuzhiyun * which won't work on pure SMBus systems.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct at24_client {
72*4882a593Smuzhiyun struct i2c_client *client;
73*4882a593Smuzhiyun struct regmap *regmap;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct at24_data {
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * Lock protects against activities from other Linux tasks,
79*4882a593Smuzhiyun * but not from changes by other I2C masters.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun struct mutex lock;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun unsigned int write_max;
84*4882a593Smuzhiyun unsigned int num_addresses;
85*4882a593Smuzhiyun unsigned int offset_adj;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun u32 byte_len;
88*4882a593Smuzhiyun u16 page_size;
89*4882a593Smuzhiyun u8 flags;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct nvmem_device *nvmem;
92*4882a593Smuzhiyun struct regulator *vcc_reg;
93*4882a593Smuzhiyun void (*read_post)(unsigned int off, char *buf, size_t count);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * Some chips tie up multiple I2C addresses; dummy devices reserve
97*4882a593Smuzhiyun * them for us, and we'll use them with SMBus calls.
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun struct at24_client client[];
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * This parameter is to help this driver avoid blocking other drivers out
104*4882a593Smuzhiyun * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C
105*4882a593Smuzhiyun * clock, one 256 byte read takes about 1/43 second which is excessive;
106*4882a593Smuzhiyun * but the 1/170 second it takes at 400 kHz may be quite reasonable; and
107*4882a593Smuzhiyun * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible.
108*4882a593Smuzhiyun *
109*4882a593Smuzhiyun * This value is forced to be a power of two so that writes align on pages.
110*4882a593Smuzhiyun */
111*4882a593Smuzhiyun static unsigned int at24_io_limit = 128;
112*4882a593Smuzhiyun module_param_named(io_limit, at24_io_limit, uint, 0);
113*4882a593Smuzhiyun MODULE_PARM_DESC(at24_io_limit, "Maximum bytes per I/O (default 128)");
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * Specs often allow 5 msec for a page write, sometimes 20 msec;
117*4882a593Smuzhiyun * it's important to recover from write timeouts.
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun static unsigned int at24_write_timeout = 25;
120*4882a593Smuzhiyun module_param_named(write_timeout, at24_write_timeout, uint, 0);
121*4882a593Smuzhiyun MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)");
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct at24_chip_data {
124*4882a593Smuzhiyun u32 byte_len;
125*4882a593Smuzhiyun u8 flags;
126*4882a593Smuzhiyun void (*read_post)(unsigned int off, char *buf, size_t count);
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define AT24_CHIP_DATA(_name, _len, _flags) \
130*4882a593Smuzhiyun static const struct at24_chip_data _name = { \
131*4882a593Smuzhiyun .byte_len = _len, .flags = _flags, \
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \
135*4882a593Smuzhiyun static const struct at24_chip_data _name = { \
136*4882a593Smuzhiyun .byte_len = _len, .flags = _flags, \
137*4882a593Smuzhiyun .read_post = _read_post, \
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
at24_read_post_vaio(unsigned int off,char * buf,size_t count)140*4882a593Smuzhiyun static void at24_read_post_vaio(unsigned int off, char *buf, size_t count)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun int i;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (capable(CAP_SYS_ADMIN))
145*4882a593Smuzhiyun return;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * Hide VAIO private settings to regular users:
149*4882a593Smuzhiyun * - BIOS passwords: bytes 0x00 to 0x0f
150*4882a593Smuzhiyun * - UUID: bytes 0x10 to 0x1f
151*4882a593Smuzhiyun * - Serial number: 0xc0 to 0xdf
152*4882a593Smuzhiyun */
153*4882a593Smuzhiyun for (i = 0; i < count; i++) {
154*4882a593Smuzhiyun if ((off + i <= 0x1f) ||
155*4882a593Smuzhiyun (off + i >= 0xc0 && off + i <= 0xdf))
156*4882a593Smuzhiyun buf[i] = 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* needs 8 addresses as A0-A2 are ignored */
161*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR);
162*4882a593Smuzhiyun /* old variants can't be handled with this generic entry! */
163*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0);
164*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs01, 16,
165*4882a593Smuzhiyun AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
166*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0);
167*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs02, 16,
168*4882a593Smuzhiyun AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
169*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24mac402, 48 / 8,
170*4882a593Smuzhiyun AT24_FLAG_MAC | AT24_FLAG_READONLY);
171*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24mac602, 64 / 8,
172*4882a593Smuzhiyun AT24_FLAG_MAC | AT24_FLAG_READONLY);
173*4882a593Smuzhiyun /* spd is a 24c02 in memory DIMMs */
174*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_spd, 2048 / 8,
175*4882a593Smuzhiyun AT24_FLAG_READONLY | AT24_FLAG_IRUGO);
176*4882a593Smuzhiyun /* 24c02_vaio is a 24c02 on some Sony laptops */
177*4882a593Smuzhiyun AT24_CHIP_DATA_CB(at24_data_24c02_vaio, 2048 / 8,
178*4882a593Smuzhiyun AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
179*4882a593Smuzhiyun at24_read_post_vaio);
180*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0);
181*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs04, 16,
182*4882a593Smuzhiyun AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
183*4882a593Smuzhiyun /* 24rf08 quirk is handled at i2c-core */
184*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0);
185*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs08, 16,
186*4882a593Smuzhiyun AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
187*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0);
188*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs16, 16,
189*4882a593Smuzhiyun AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
190*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16);
191*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs32, 16,
192*4882a593Smuzhiyun AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
193*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16);
194*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24cs64, 16,
195*4882a593Smuzhiyun AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
196*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16);
197*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16);
198*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16);
199*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16);
200*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16);
201*4882a593Smuzhiyun /* identical to 24c08 ? */
202*4882a593Smuzhiyun AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct i2c_device_id at24_ids[] = {
205*4882a593Smuzhiyun { "24c00", (kernel_ulong_t)&at24_data_24c00 },
206*4882a593Smuzhiyun { "24c01", (kernel_ulong_t)&at24_data_24c01 },
207*4882a593Smuzhiyun { "24cs01", (kernel_ulong_t)&at24_data_24cs01 },
208*4882a593Smuzhiyun { "24c02", (kernel_ulong_t)&at24_data_24c02 },
209*4882a593Smuzhiyun { "24cs02", (kernel_ulong_t)&at24_data_24cs02 },
210*4882a593Smuzhiyun { "24mac402", (kernel_ulong_t)&at24_data_24mac402 },
211*4882a593Smuzhiyun { "24mac602", (kernel_ulong_t)&at24_data_24mac602 },
212*4882a593Smuzhiyun { "spd", (kernel_ulong_t)&at24_data_spd },
213*4882a593Smuzhiyun { "24c02-vaio", (kernel_ulong_t)&at24_data_24c02_vaio },
214*4882a593Smuzhiyun { "24c04", (kernel_ulong_t)&at24_data_24c04 },
215*4882a593Smuzhiyun { "24cs04", (kernel_ulong_t)&at24_data_24cs04 },
216*4882a593Smuzhiyun { "24c08", (kernel_ulong_t)&at24_data_24c08 },
217*4882a593Smuzhiyun { "24cs08", (kernel_ulong_t)&at24_data_24cs08 },
218*4882a593Smuzhiyun { "24c16", (kernel_ulong_t)&at24_data_24c16 },
219*4882a593Smuzhiyun { "24cs16", (kernel_ulong_t)&at24_data_24cs16 },
220*4882a593Smuzhiyun { "24c32", (kernel_ulong_t)&at24_data_24c32 },
221*4882a593Smuzhiyun { "24cs32", (kernel_ulong_t)&at24_data_24cs32 },
222*4882a593Smuzhiyun { "24c64", (kernel_ulong_t)&at24_data_24c64 },
223*4882a593Smuzhiyun { "24cs64", (kernel_ulong_t)&at24_data_24cs64 },
224*4882a593Smuzhiyun { "24c128", (kernel_ulong_t)&at24_data_24c128 },
225*4882a593Smuzhiyun { "24c256", (kernel_ulong_t)&at24_data_24c256 },
226*4882a593Smuzhiyun { "24c512", (kernel_ulong_t)&at24_data_24c512 },
227*4882a593Smuzhiyun { "24c1024", (kernel_ulong_t)&at24_data_24c1024 },
228*4882a593Smuzhiyun { "24c2048", (kernel_ulong_t)&at24_data_24c2048 },
229*4882a593Smuzhiyun { "at24", 0 },
230*4882a593Smuzhiyun { /* END OF LIST */ }
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, at24_ids);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun static const struct of_device_id at24_of_match[] = {
235*4882a593Smuzhiyun { .compatible = "atmel,24c00", .data = &at24_data_24c00 },
236*4882a593Smuzhiyun { .compatible = "atmel,24c01", .data = &at24_data_24c01 },
237*4882a593Smuzhiyun { .compatible = "atmel,24cs01", .data = &at24_data_24cs01 },
238*4882a593Smuzhiyun { .compatible = "atmel,24c02", .data = &at24_data_24c02 },
239*4882a593Smuzhiyun { .compatible = "atmel,24cs02", .data = &at24_data_24cs02 },
240*4882a593Smuzhiyun { .compatible = "atmel,24mac402", .data = &at24_data_24mac402 },
241*4882a593Smuzhiyun { .compatible = "atmel,24mac602", .data = &at24_data_24mac602 },
242*4882a593Smuzhiyun { .compatible = "atmel,spd", .data = &at24_data_spd },
243*4882a593Smuzhiyun { .compatible = "atmel,24c04", .data = &at24_data_24c04 },
244*4882a593Smuzhiyun { .compatible = "atmel,24cs04", .data = &at24_data_24cs04 },
245*4882a593Smuzhiyun { .compatible = "atmel,24c08", .data = &at24_data_24c08 },
246*4882a593Smuzhiyun { .compatible = "atmel,24cs08", .data = &at24_data_24cs08 },
247*4882a593Smuzhiyun { .compatible = "atmel,24c16", .data = &at24_data_24c16 },
248*4882a593Smuzhiyun { .compatible = "atmel,24cs16", .data = &at24_data_24cs16 },
249*4882a593Smuzhiyun { .compatible = "atmel,24c32", .data = &at24_data_24c32 },
250*4882a593Smuzhiyun { .compatible = "atmel,24cs32", .data = &at24_data_24cs32 },
251*4882a593Smuzhiyun { .compatible = "atmel,24c64", .data = &at24_data_24c64 },
252*4882a593Smuzhiyun { .compatible = "atmel,24cs64", .data = &at24_data_24cs64 },
253*4882a593Smuzhiyun { .compatible = "atmel,24c128", .data = &at24_data_24c128 },
254*4882a593Smuzhiyun { .compatible = "atmel,24c256", .data = &at24_data_24c256 },
255*4882a593Smuzhiyun { .compatible = "atmel,24c512", .data = &at24_data_24c512 },
256*4882a593Smuzhiyun { .compatible = "atmel,24c1024", .data = &at24_data_24c1024 },
257*4882a593Smuzhiyun { .compatible = "atmel,24c2048", .data = &at24_data_24c2048 },
258*4882a593Smuzhiyun { /* END OF LIST */ },
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, at24_of_match);
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const struct acpi_device_id __maybe_unused at24_acpi_ids[] = {
263*4882a593Smuzhiyun { "INT3499", (kernel_ulong_t)&at24_data_INT3499 },
264*4882a593Smuzhiyun { "TPF0001", (kernel_ulong_t)&at24_data_24c1024 },
265*4882a593Smuzhiyun { /* END OF LIST */ }
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, at24_acpi_ids);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /*
270*4882a593Smuzhiyun * This routine supports chips which consume multiple I2C addresses. It
271*4882a593Smuzhiyun * computes the addressing information to be used for a given r/w request.
272*4882a593Smuzhiyun * Assumes that sanity checks for offset happened at sysfs-layer.
273*4882a593Smuzhiyun *
274*4882a593Smuzhiyun * Slave address and byte offset derive from the offset. Always
275*4882a593Smuzhiyun * set the byte address; on a multi-master board, another master
276*4882a593Smuzhiyun * may have changed the chip's "current" address pointer.
277*4882a593Smuzhiyun */
at24_translate_offset(struct at24_data * at24,unsigned int * offset)278*4882a593Smuzhiyun static struct at24_client *at24_translate_offset(struct at24_data *at24,
279*4882a593Smuzhiyun unsigned int *offset)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun unsigned int i;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun if (at24->flags & AT24_FLAG_ADDR16) {
284*4882a593Smuzhiyun i = *offset >> 16;
285*4882a593Smuzhiyun *offset &= 0xffff;
286*4882a593Smuzhiyun } else {
287*4882a593Smuzhiyun i = *offset >> 8;
288*4882a593Smuzhiyun *offset &= 0xff;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun return &at24->client[i];
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
at24_base_client_dev(struct at24_data * at24)294*4882a593Smuzhiyun static struct device *at24_base_client_dev(struct at24_data *at24)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun return &at24->client[0].client->dev;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
at24_adjust_read_count(struct at24_data * at24,unsigned int offset,size_t count)299*4882a593Smuzhiyun static size_t at24_adjust_read_count(struct at24_data *at24,
300*4882a593Smuzhiyun unsigned int offset, size_t count)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun unsigned int bits;
303*4882a593Smuzhiyun size_t remainder;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /*
306*4882a593Smuzhiyun * In case of multi-address chips that don't rollover reads to
307*4882a593Smuzhiyun * the next slave address: truncate the count to the slave boundary,
308*4882a593Smuzhiyun * so that the read never straddles slaves.
309*4882a593Smuzhiyun */
310*4882a593Smuzhiyun if (at24->flags & AT24_FLAG_NO_RDROL) {
311*4882a593Smuzhiyun bits = (at24->flags & AT24_FLAG_ADDR16) ? 16 : 8;
312*4882a593Smuzhiyun remainder = BIT(bits) - offset;
313*4882a593Smuzhiyun if (count > remainder)
314*4882a593Smuzhiyun count = remainder;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (count > at24_io_limit)
318*4882a593Smuzhiyun count = at24_io_limit;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return count;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
at24_regmap_read(struct at24_data * at24,char * buf,unsigned int offset,size_t count)323*4882a593Smuzhiyun static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
324*4882a593Smuzhiyun unsigned int offset, size_t count)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun unsigned long timeout, read_time;
327*4882a593Smuzhiyun struct at24_client *at24_client;
328*4882a593Smuzhiyun struct i2c_client *client;
329*4882a593Smuzhiyun struct regmap *regmap;
330*4882a593Smuzhiyun int ret;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun at24_client = at24_translate_offset(at24, &offset);
333*4882a593Smuzhiyun regmap = at24_client->regmap;
334*4882a593Smuzhiyun client = at24_client->client;
335*4882a593Smuzhiyun count = at24_adjust_read_count(at24, offset, count);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* adjust offset for mac and serial read ops */
338*4882a593Smuzhiyun offset += at24->offset_adj;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(at24_write_timeout);
341*4882a593Smuzhiyun do {
342*4882a593Smuzhiyun /*
343*4882a593Smuzhiyun * The timestamp shall be taken before the actual operation
344*4882a593Smuzhiyun * to avoid a premature timeout in case of high CPU load.
345*4882a593Smuzhiyun */
346*4882a593Smuzhiyun read_time = jiffies;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun ret = regmap_bulk_read(regmap, offset, buf, count);
349*4882a593Smuzhiyun dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n",
350*4882a593Smuzhiyun count, offset, ret, jiffies);
351*4882a593Smuzhiyun if (!ret)
352*4882a593Smuzhiyun return count;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun usleep_range(1000, 1500);
355*4882a593Smuzhiyun } while (time_before(read_time, timeout));
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun return -ETIMEDOUT;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun /*
361*4882a593Smuzhiyun * Note that if the hardware write-protect pin is pulled high, the whole
362*4882a593Smuzhiyun * chip is normally write protected. But there are plenty of product
363*4882a593Smuzhiyun * variants here, including OTP fuses and partial chip protect.
364*4882a593Smuzhiyun *
365*4882a593Smuzhiyun * We only use page mode writes; the alternative is sloooow. These routines
366*4882a593Smuzhiyun * write at most one page.
367*4882a593Smuzhiyun */
368*4882a593Smuzhiyun
at24_adjust_write_count(struct at24_data * at24,unsigned int offset,size_t count)369*4882a593Smuzhiyun static size_t at24_adjust_write_count(struct at24_data *at24,
370*4882a593Smuzhiyun unsigned int offset, size_t count)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun unsigned int next_page;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /* write_max is at most a page */
375*4882a593Smuzhiyun if (count > at24->write_max)
376*4882a593Smuzhiyun count = at24->write_max;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* Never roll over backwards, to the start of this page */
379*4882a593Smuzhiyun next_page = roundup(offset + 1, at24->page_size);
380*4882a593Smuzhiyun if (offset + count > next_page)
381*4882a593Smuzhiyun count = next_page - offset;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun return count;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
at24_regmap_write(struct at24_data * at24,const char * buf,unsigned int offset,size_t count)386*4882a593Smuzhiyun static ssize_t at24_regmap_write(struct at24_data *at24, const char *buf,
387*4882a593Smuzhiyun unsigned int offset, size_t count)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun unsigned long timeout, write_time;
390*4882a593Smuzhiyun struct at24_client *at24_client;
391*4882a593Smuzhiyun struct i2c_client *client;
392*4882a593Smuzhiyun struct regmap *regmap;
393*4882a593Smuzhiyun int ret;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun at24_client = at24_translate_offset(at24, &offset);
396*4882a593Smuzhiyun regmap = at24_client->regmap;
397*4882a593Smuzhiyun client = at24_client->client;
398*4882a593Smuzhiyun count = at24_adjust_write_count(at24, offset, count);
399*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(at24_write_timeout);
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun do {
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun * The timestamp shall be taken before the actual operation
404*4882a593Smuzhiyun * to avoid a premature timeout in case of high CPU load.
405*4882a593Smuzhiyun */
406*4882a593Smuzhiyun write_time = jiffies;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun ret = regmap_bulk_write(regmap, offset, buf, count);
409*4882a593Smuzhiyun dev_dbg(&client->dev, "write %zu@%d --> %d (%ld)\n",
410*4882a593Smuzhiyun count, offset, ret, jiffies);
411*4882a593Smuzhiyun if (!ret)
412*4882a593Smuzhiyun return count;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun usleep_range(1000, 1500);
415*4882a593Smuzhiyun } while (time_before(write_time, timeout));
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun return -ETIMEDOUT;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
at24_read(void * priv,unsigned int off,void * val,size_t count)420*4882a593Smuzhiyun static int at24_read(void *priv, unsigned int off, void *val, size_t count)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun struct at24_data *at24;
423*4882a593Smuzhiyun struct device *dev;
424*4882a593Smuzhiyun char *buf = val;
425*4882a593Smuzhiyun int i, ret;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun at24 = priv;
428*4882a593Smuzhiyun dev = at24_base_client_dev(at24);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (unlikely(!count))
431*4882a593Smuzhiyun return count;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (off + count > at24->byte_len)
434*4882a593Smuzhiyun return -EINVAL;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
437*4882a593Smuzhiyun if (ret < 0) {
438*4882a593Smuzhiyun pm_runtime_put_noidle(dev);
439*4882a593Smuzhiyun return ret;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun * Read data from chip, protecting against concurrent updates
444*4882a593Smuzhiyun * from this host, but not from other I2C masters.
445*4882a593Smuzhiyun */
446*4882a593Smuzhiyun mutex_lock(&at24->lock);
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun for (i = 0; count; i += ret, count -= ret) {
449*4882a593Smuzhiyun ret = at24_regmap_read(at24, buf + i, off + i, count);
450*4882a593Smuzhiyun if (ret < 0) {
451*4882a593Smuzhiyun mutex_unlock(&at24->lock);
452*4882a593Smuzhiyun pm_runtime_put(dev);
453*4882a593Smuzhiyun return ret;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun mutex_unlock(&at24->lock);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun pm_runtime_put(dev);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (unlikely(at24->read_post))
462*4882a593Smuzhiyun at24->read_post(off, buf, i);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun return 0;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
at24_write(void * priv,unsigned int off,void * val,size_t count)467*4882a593Smuzhiyun static int at24_write(void *priv, unsigned int off, void *val, size_t count)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun struct at24_data *at24;
470*4882a593Smuzhiyun struct device *dev;
471*4882a593Smuzhiyun char *buf = val;
472*4882a593Smuzhiyun int ret;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun at24 = priv;
475*4882a593Smuzhiyun dev = at24_base_client_dev(at24);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (unlikely(!count))
478*4882a593Smuzhiyun return -EINVAL;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun if (off + count > at24->byte_len)
481*4882a593Smuzhiyun return -EINVAL;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
484*4882a593Smuzhiyun if (ret < 0) {
485*4882a593Smuzhiyun pm_runtime_put_noidle(dev);
486*4882a593Smuzhiyun return ret;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /*
490*4882a593Smuzhiyun * Write data to chip, protecting against concurrent updates
491*4882a593Smuzhiyun * from this host, but not from other I2C masters.
492*4882a593Smuzhiyun */
493*4882a593Smuzhiyun mutex_lock(&at24->lock);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun while (count) {
496*4882a593Smuzhiyun ret = at24_regmap_write(at24, buf, off, count);
497*4882a593Smuzhiyun if (ret < 0) {
498*4882a593Smuzhiyun mutex_unlock(&at24->lock);
499*4882a593Smuzhiyun pm_runtime_put(dev);
500*4882a593Smuzhiyun return ret;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun buf += ret;
503*4882a593Smuzhiyun off += ret;
504*4882a593Smuzhiyun count -= ret;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun mutex_unlock(&at24->lock);
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun pm_runtime_put(dev);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun return 0;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
at24_get_chip_data(struct device * dev)514*4882a593Smuzhiyun static const struct at24_chip_data *at24_get_chip_data(struct device *dev)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun struct device_node *of_node = dev->of_node;
517*4882a593Smuzhiyun const struct at24_chip_data *cdata;
518*4882a593Smuzhiyun const struct i2c_device_id *id;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun id = i2c_match_id(at24_ids, to_i2c_client(dev));
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun /*
523*4882a593Smuzhiyun * The I2C core allows OF nodes compatibles to match against the
524*4882a593Smuzhiyun * I2C device ID table as a fallback, so check not only if an OF
525*4882a593Smuzhiyun * node is present but also if it matches an OF device ID entry.
526*4882a593Smuzhiyun */
527*4882a593Smuzhiyun if (of_node && of_match_device(at24_of_match, dev))
528*4882a593Smuzhiyun cdata = of_device_get_match_data(dev);
529*4882a593Smuzhiyun else if (id)
530*4882a593Smuzhiyun cdata = (void *)id->driver_data;
531*4882a593Smuzhiyun else
532*4882a593Smuzhiyun cdata = acpi_device_get_match_data(dev);
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun if (!cdata)
535*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun return cdata;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
at24_make_dummy_client(struct at24_data * at24,unsigned int index,struct regmap_config * regmap_config)540*4882a593Smuzhiyun static int at24_make_dummy_client(struct at24_data *at24, unsigned int index,
541*4882a593Smuzhiyun struct regmap_config *regmap_config)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun struct i2c_client *base_client, *dummy_client;
544*4882a593Smuzhiyun struct regmap *regmap;
545*4882a593Smuzhiyun struct device *dev;
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun base_client = at24->client[0].client;
548*4882a593Smuzhiyun dev = &base_client->dev;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun dummy_client = devm_i2c_new_dummy_device(dev, base_client->adapter,
551*4882a593Smuzhiyun base_client->addr + index);
552*4882a593Smuzhiyun if (IS_ERR(dummy_client))
553*4882a593Smuzhiyun return PTR_ERR(dummy_client);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(dummy_client, regmap_config);
556*4882a593Smuzhiyun if (IS_ERR(regmap))
557*4882a593Smuzhiyun return PTR_ERR(regmap);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun at24->client[index].client = dummy_client;
560*4882a593Smuzhiyun at24->client[index].regmap = regmap;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun return 0;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
at24_get_offset_adj(u8 flags,unsigned int byte_len)565*4882a593Smuzhiyun static unsigned int at24_get_offset_adj(u8 flags, unsigned int byte_len)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun if (flags & AT24_FLAG_MAC) {
568*4882a593Smuzhiyun /* EUI-48 starts from 0x9a, EUI-64 from 0x98 */
569*4882a593Smuzhiyun return 0xa0 - byte_len;
570*4882a593Smuzhiyun } else if (flags & AT24_FLAG_SERIAL && flags & AT24_FLAG_ADDR16) {
571*4882a593Smuzhiyun /*
572*4882a593Smuzhiyun * For 16 bit address pointers, the word address must contain
573*4882a593Smuzhiyun * a '10' sequence in bits 11 and 10 regardless of the
574*4882a593Smuzhiyun * intended position of the address pointer.
575*4882a593Smuzhiyun */
576*4882a593Smuzhiyun return 0x0800;
577*4882a593Smuzhiyun } else if (flags & AT24_FLAG_SERIAL) {
578*4882a593Smuzhiyun /*
579*4882a593Smuzhiyun * Otherwise the word address must begin with a '10' sequence,
580*4882a593Smuzhiyun * regardless of the intended address.
581*4882a593Smuzhiyun */
582*4882a593Smuzhiyun return 0x0080;
583*4882a593Smuzhiyun } else {
584*4882a593Smuzhiyun return 0;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
at24_probe(struct i2c_client * client)588*4882a593Smuzhiyun static int at24_probe(struct i2c_client *client)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun struct regmap_config regmap_config = { };
591*4882a593Smuzhiyun struct nvmem_config nvmem_config = { };
592*4882a593Smuzhiyun u32 byte_len, page_size, flags, addrw;
593*4882a593Smuzhiyun const struct at24_chip_data *cdata;
594*4882a593Smuzhiyun struct device *dev = &client->dev;
595*4882a593Smuzhiyun bool i2c_fn_i2c, i2c_fn_block;
596*4882a593Smuzhiyun unsigned int i, num_addresses;
597*4882a593Smuzhiyun struct at24_data *at24;
598*4882a593Smuzhiyun struct regmap *regmap;
599*4882a593Smuzhiyun bool writable;
600*4882a593Smuzhiyun u8 test_byte;
601*4882a593Smuzhiyun int err;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C);
604*4882a593Smuzhiyun i2c_fn_block = i2c_check_functionality(client->adapter,
605*4882a593Smuzhiyun I2C_FUNC_SMBUS_WRITE_I2C_BLOCK);
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun cdata = at24_get_chip_data(dev);
608*4882a593Smuzhiyun if (IS_ERR(cdata))
609*4882a593Smuzhiyun return PTR_ERR(cdata);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun err = device_property_read_u32(dev, "pagesize", &page_size);
612*4882a593Smuzhiyun if (err)
613*4882a593Smuzhiyun /*
614*4882a593Smuzhiyun * This is slow, but we can't know all eeproms, so we better
615*4882a593Smuzhiyun * play safe. Specifying custom eeprom-types via device tree
616*4882a593Smuzhiyun * or properties is recommended anyhow.
617*4882a593Smuzhiyun */
618*4882a593Smuzhiyun page_size = 1;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun flags = cdata->flags;
621*4882a593Smuzhiyun if (device_property_present(dev, "read-only"))
622*4882a593Smuzhiyun flags |= AT24_FLAG_READONLY;
623*4882a593Smuzhiyun if (device_property_present(dev, "no-read-rollover"))
624*4882a593Smuzhiyun flags |= AT24_FLAG_NO_RDROL;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun err = device_property_read_u32(dev, "address-width", &addrw);
627*4882a593Smuzhiyun if (!err) {
628*4882a593Smuzhiyun switch (addrw) {
629*4882a593Smuzhiyun case 8:
630*4882a593Smuzhiyun if (flags & AT24_FLAG_ADDR16)
631*4882a593Smuzhiyun dev_warn(dev,
632*4882a593Smuzhiyun "Override address width to be 8, while default is 16\n");
633*4882a593Smuzhiyun flags &= ~AT24_FLAG_ADDR16;
634*4882a593Smuzhiyun break;
635*4882a593Smuzhiyun case 16:
636*4882a593Smuzhiyun flags |= AT24_FLAG_ADDR16;
637*4882a593Smuzhiyun break;
638*4882a593Smuzhiyun default:
639*4882a593Smuzhiyun dev_warn(dev, "Bad \"address-width\" property: %u\n",
640*4882a593Smuzhiyun addrw);
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun err = device_property_read_u32(dev, "size", &byte_len);
645*4882a593Smuzhiyun if (err)
646*4882a593Smuzhiyun byte_len = cdata->byte_len;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun if (!i2c_fn_i2c && !i2c_fn_block)
649*4882a593Smuzhiyun page_size = 1;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun if (!page_size) {
652*4882a593Smuzhiyun dev_err(dev, "page_size must not be 0!\n");
653*4882a593Smuzhiyun return -EINVAL;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun if (!is_power_of_2(page_size))
657*4882a593Smuzhiyun dev_warn(dev, "page_size looks suspicious (no power of 2)!\n");
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun err = device_property_read_u32(dev, "num-addresses", &num_addresses);
660*4882a593Smuzhiyun if (err) {
661*4882a593Smuzhiyun if (flags & AT24_FLAG_TAKE8ADDR)
662*4882a593Smuzhiyun num_addresses = 8;
663*4882a593Smuzhiyun else
664*4882a593Smuzhiyun num_addresses = DIV_ROUND_UP(byte_len,
665*4882a593Smuzhiyun (flags & AT24_FLAG_ADDR16) ? 65536 : 256);
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) {
669*4882a593Smuzhiyun dev_err(dev,
670*4882a593Smuzhiyun "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC.");
671*4882a593Smuzhiyun return -EINVAL;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun regmap_config.val_bits = 8;
675*4882a593Smuzhiyun regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8;
676*4882a593Smuzhiyun regmap_config.disable_locking = true;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(client, ®map_config);
679*4882a593Smuzhiyun if (IS_ERR(regmap))
680*4882a593Smuzhiyun return PTR_ERR(regmap);
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun at24 = devm_kzalloc(dev, struct_size(at24, client, num_addresses),
683*4882a593Smuzhiyun GFP_KERNEL);
684*4882a593Smuzhiyun if (!at24)
685*4882a593Smuzhiyun return -ENOMEM;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun mutex_init(&at24->lock);
688*4882a593Smuzhiyun at24->byte_len = byte_len;
689*4882a593Smuzhiyun at24->page_size = page_size;
690*4882a593Smuzhiyun at24->flags = flags;
691*4882a593Smuzhiyun at24->read_post = cdata->read_post;
692*4882a593Smuzhiyun at24->num_addresses = num_addresses;
693*4882a593Smuzhiyun at24->offset_adj = at24_get_offset_adj(flags, byte_len);
694*4882a593Smuzhiyun at24->client[0].client = client;
695*4882a593Smuzhiyun at24->client[0].regmap = regmap;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun at24->vcc_reg = devm_regulator_get(dev, "vcc");
698*4882a593Smuzhiyun if (IS_ERR(at24->vcc_reg))
699*4882a593Smuzhiyun return PTR_ERR(at24->vcc_reg);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun writable = !(flags & AT24_FLAG_READONLY);
702*4882a593Smuzhiyun if (writable) {
703*4882a593Smuzhiyun at24->write_max = min_t(unsigned int,
704*4882a593Smuzhiyun page_size, at24_io_limit);
705*4882a593Smuzhiyun if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX)
706*4882a593Smuzhiyun at24->write_max = I2C_SMBUS_BLOCK_MAX;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun /* use dummy devices for multiple-address chips */
710*4882a593Smuzhiyun for (i = 1; i < num_addresses; i++) {
711*4882a593Smuzhiyun err = at24_make_dummy_client(at24, i, ®map_config);
712*4882a593Smuzhiyun if (err)
713*4882a593Smuzhiyun return err;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun /*
717*4882a593Smuzhiyun * We initialize nvmem_config.id to NVMEM_DEVID_AUTO even if the
718*4882a593Smuzhiyun * label property is set as some platform can have multiple eeproms
719*4882a593Smuzhiyun * with same label and we can not register each of those with same
720*4882a593Smuzhiyun * label. Failing to register those eeproms trigger cascade failure
721*4882a593Smuzhiyun * on such platform.
722*4882a593Smuzhiyun */
723*4882a593Smuzhiyun nvmem_config.id = NVMEM_DEVID_AUTO;
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun if (device_property_present(dev, "label")) {
726*4882a593Smuzhiyun err = device_property_read_string(dev, "label",
727*4882a593Smuzhiyun &nvmem_config.name);
728*4882a593Smuzhiyun if (err)
729*4882a593Smuzhiyun return err;
730*4882a593Smuzhiyun } else {
731*4882a593Smuzhiyun nvmem_config.name = dev_name(dev);
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun nvmem_config.type = NVMEM_TYPE_EEPROM;
735*4882a593Smuzhiyun nvmem_config.dev = dev;
736*4882a593Smuzhiyun nvmem_config.read_only = !writable;
737*4882a593Smuzhiyun nvmem_config.root_only = !(flags & AT24_FLAG_IRUGO);
738*4882a593Smuzhiyun nvmem_config.owner = THIS_MODULE;
739*4882a593Smuzhiyun nvmem_config.compat = true;
740*4882a593Smuzhiyun nvmem_config.base_dev = dev;
741*4882a593Smuzhiyun nvmem_config.reg_read = at24_read;
742*4882a593Smuzhiyun nvmem_config.reg_write = at24_write;
743*4882a593Smuzhiyun nvmem_config.priv = at24;
744*4882a593Smuzhiyun nvmem_config.stride = 1;
745*4882a593Smuzhiyun nvmem_config.word_size = 1;
746*4882a593Smuzhiyun nvmem_config.size = byte_len;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun i2c_set_clientdata(client, at24);
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun err = regulator_enable(at24->vcc_reg);
751*4882a593Smuzhiyun if (err) {
752*4882a593Smuzhiyun dev_err(dev, "Failed to enable vcc regulator\n");
753*4882a593Smuzhiyun return err;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun /* enable runtime pm */
757*4882a593Smuzhiyun pm_runtime_set_active(dev);
758*4882a593Smuzhiyun pm_runtime_enable(dev);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun at24->nvmem = devm_nvmem_register(dev, &nvmem_config);
761*4882a593Smuzhiyun if (IS_ERR(at24->nvmem)) {
762*4882a593Smuzhiyun pm_runtime_disable(dev);
763*4882a593Smuzhiyun if (!pm_runtime_status_suspended(dev))
764*4882a593Smuzhiyun regulator_disable(at24->vcc_reg);
765*4882a593Smuzhiyun return PTR_ERR(at24->nvmem);
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun /*
769*4882a593Smuzhiyun * Perform a one-byte test read to verify that the
770*4882a593Smuzhiyun * chip is functional.
771*4882a593Smuzhiyun */
772*4882a593Smuzhiyun err = at24_read(at24, 0, &test_byte, 1);
773*4882a593Smuzhiyun if (err) {
774*4882a593Smuzhiyun pm_runtime_disable(dev);
775*4882a593Smuzhiyun if (!pm_runtime_status_suspended(dev))
776*4882a593Smuzhiyun regulator_disable(at24->vcc_reg);
777*4882a593Smuzhiyun return -ENODEV;
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun pm_runtime_idle(dev);
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun if (writable)
783*4882a593Smuzhiyun dev_info(dev, "%u byte %s EEPROM, writable, %u bytes/write\n",
784*4882a593Smuzhiyun byte_len, client->name, at24->write_max);
785*4882a593Smuzhiyun else
786*4882a593Smuzhiyun dev_info(dev, "%u byte %s EEPROM, read-only\n",
787*4882a593Smuzhiyun byte_len, client->name);
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun return 0;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
at24_remove(struct i2c_client * client)792*4882a593Smuzhiyun static int at24_remove(struct i2c_client *client)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun struct at24_data *at24 = i2c_get_clientdata(client);
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
797*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
798*4882a593Smuzhiyun regulator_disable(at24->vcc_reg);
799*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun return 0;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
at24_suspend(struct device * dev)804*4882a593Smuzhiyun static int __maybe_unused at24_suspend(struct device *dev)
805*4882a593Smuzhiyun {
806*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
807*4882a593Smuzhiyun struct at24_data *at24 = i2c_get_clientdata(client);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun return regulator_disable(at24->vcc_reg);
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
at24_resume(struct device * dev)812*4882a593Smuzhiyun static int __maybe_unused at24_resume(struct device *dev)
813*4882a593Smuzhiyun {
814*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
815*4882a593Smuzhiyun struct at24_data *at24 = i2c_get_clientdata(client);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun return regulator_enable(at24->vcc_reg);
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun static const struct dev_pm_ops at24_pm_ops = {
821*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
822*4882a593Smuzhiyun pm_runtime_force_resume)
823*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(at24_suspend, at24_resume, NULL)
824*4882a593Smuzhiyun };
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun static struct i2c_driver at24_driver = {
827*4882a593Smuzhiyun .driver = {
828*4882a593Smuzhiyun .name = "at24",
829*4882a593Smuzhiyun .pm = &at24_pm_ops,
830*4882a593Smuzhiyun .of_match_table = at24_of_match,
831*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(at24_acpi_ids),
832*4882a593Smuzhiyun },
833*4882a593Smuzhiyun .probe_new = at24_probe,
834*4882a593Smuzhiyun .remove = at24_remove,
835*4882a593Smuzhiyun .id_table = at24_ids,
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun
at24_init(void)838*4882a593Smuzhiyun static int __init at24_init(void)
839*4882a593Smuzhiyun {
840*4882a593Smuzhiyun if (!at24_io_limit) {
841*4882a593Smuzhiyun pr_err("at24: at24_io_limit must not be 0!\n");
842*4882a593Smuzhiyun return -EINVAL;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun at24_io_limit = rounddown_pow_of_two(at24_io_limit);
846*4882a593Smuzhiyun return i2c_add_driver(&at24_driver);
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun module_init(at24_init);
849*4882a593Smuzhiyun
at24_exit(void)850*4882a593Smuzhiyun static void __exit at24_exit(void)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun i2c_del_driver(&at24_driver);
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun module_exit(at24_exit);
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for most I2C EEPROMs");
857*4882a593Smuzhiyun MODULE_AUTHOR("David Brownell and Wolfram Sang");
858*4882a593Smuzhiyun MODULE_LICENSE("GPL");
859