1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /* Driver for Realtek PCI-Express card reader
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author:
7*4882a593Smuzhiyun * Wei WANG <wei_wang@realsil.com.cn>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef __RTSX_PCR_H
11*4882a593Smuzhiyun #define __RTSX_PCR_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/rtsx_pci.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define MIN_DIV_N_PCR 80
16*4882a593Smuzhiyun #define MAX_DIV_N_PCR 208
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define RTS522A_PM_CTRL3 0xFF7E
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define RTS524A_PME_FORCE_CTL 0xFF78
21*4882a593Smuzhiyun #define REG_EFUSE_BYPASS 0x08
22*4882a593Smuzhiyun #define REG_EFUSE_POR 0x04
23*4882a593Smuzhiyun #define REG_EFUSE_POWER_MASK 0x03
24*4882a593Smuzhiyun #define REG_EFUSE_POWERON 0x03
25*4882a593Smuzhiyun #define REG_EFUSE_POWEROFF 0x00
26*4882a593Smuzhiyun #define RTS5250_CLK_CFG3 0xFF79
27*4882a593Smuzhiyun #define RTS525A_CFG_MEM_PD 0xF0
28*4882a593Smuzhiyun #define RTS524A_PM_CTRL3 0xFF7E
29*4882a593Smuzhiyun #define RTS525A_BIOS_CFG 0xFF2D
30*4882a593Smuzhiyun #define RTS525A_LOAD_BIOS_FLAG 0x01
31*4882a593Smuzhiyun #define RTS525A_CLEAR_BIOS_FLAG 0x00
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RTS525A_EFUSE_CTL 0xFC32
34*4882a593Smuzhiyun #define REG_EFUSE_ENABLE 0x80
35*4882a593Smuzhiyun #define REG_EFUSE_MODE 0x40
36*4882a593Smuzhiyun #define RTS525A_EFUSE_ADD 0xFC33
37*4882a593Smuzhiyun #define REG_EFUSE_ADD_MASK 0x3F
38*4882a593Smuzhiyun #define RTS525A_EFUSE_DATA 0xFC35
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define LTR_ACTIVE_LATENCY_DEF 0x883C
41*4882a593Smuzhiyun #define LTR_IDLE_LATENCY_DEF 0x892C
42*4882a593Smuzhiyun #define LTR_L1OFF_LATENCY_DEF 0x9003
43*4882a593Smuzhiyun #define L1_SNOOZE_DELAY_DEF 1
44*4882a593Smuzhiyun #define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF
45*4882a593Smuzhiyun #define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF
46*4882a593Smuzhiyun #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
47*4882a593Smuzhiyun #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
48*4882a593Smuzhiyun #define CMD_TIMEOUT_DEF 100
49*4882a593Smuzhiyun #define MASK_8_BIT_DEF 0xFF
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define SSC_CLOCK_STABLE_WAIT 130
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define RTS524A_OCP_THD_800 0x04
54*4882a593Smuzhiyun #define RTS525A_OCP_THD_800 0x05
55*4882a593Smuzhiyun #define RTS522A_OCP_THD_800 0x06
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
59*4882a593Smuzhiyun int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun void rts5209_init_params(struct rtsx_pcr *pcr);
62*4882a593Smuzhiyun void rts5229_init_params(struct rtsx_pcr *pcr);
63*4882a593Smuzhiyun void rtl8411_init_params(struct rtsx_pcr *pcr);
64*4882a593Smuzhiyun void rtl8402_init_params(struct rtsx_pcr *pcr);
65*4882a593Smuzhiyun void rts5227_init_params(struct rtsx_pcr *pcr);
66*4882a593Smuzhiyun void rts522a_init_params(struct rtsx_pcr *pcr);
67*4882a593Smuzhiyun void rts5249_init_params(struct rtsx_pcr *pcr);
68*4882a593Smuzhiyun void rts524a_init_params(struct rtsx_pcr *pcr);
69*4882a593Smuzhiyun void rts525a_init_params(struct rtsx_pcr *pcr);
70*4882a593Smuzhiyun void rtl8411b_init_params(struct rtsx_pcr *pcr);
71*4882a593Smuzhiyun void rts5260_init_params(struct rtsx_pcr *pcr);
72*4882a593Smuzhiyun void rts5261_init_params(struct rtsx_pcr *pcr);
73*4882a593Smuzhiyun void rts5228_init_params(struct rtsx_pcr *pcr);
74*4882a593Smuzhiyun
map_sd_drive(int idx)75*4882a593Smuzhiyun static inline u8 map_sd_drive(int idx)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun u8 sd_drive[4] = {
78*4882a593Smuzhiyun 0x01, /* Type D */
79*4882a593Smuzhiyun 0x02, /* Type C */
80*4882a593Smuzhiyun 0x05, /* Type A */
81*4882a593Smuzhiyun 0x03 /* Type B */
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return sd_drive[idx];
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
88*4882a593Smuzhiyun #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
89*4882a593Smuzhiyun #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define rtsx_check_mmc_support(reg) ((reg) & 0x10)
92*4882a593Smuzhiyun #define rtsx_reg_to_rtd3(reg) ((reg) & 0x02)
93*4882a593Smuzhiyun #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
94*4882a593Smuzhiyun #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
95*4882a593Smuzhiyun #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
96*4882a593Smuzhiyun #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
97*4882a593Smuzhiyun #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
98*4882a593Smuzhiyun #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
99*4882a593Smuzhiyun #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
100*4882a593Smuzhiyun #define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
101*4882a593Smuzhiyun #define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
102*4882a593Smuzhiyun #define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
103*4882a593Smuzhiyun #define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
104*4882a593Smuzhiyun #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun #define set_pull_ctrl_tables(pcr, __device) \
107*4882a593Smuzhiyun do { \
108*4882a593Smuzhiyun pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \
109*4882a593Smuzhiyun pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
110*4882a593Smuzhiyun pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \
111*4882a593Smuzhiyun pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
112*4882a593Smuzhiyun } while (0)
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* generic operations */
115*4882a593Smuzhiyun int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
116*4882a593Smuzhiyun int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
117*4882a593Smuzhiyun int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
118*4882a593Smuzhiyun void rtsx_pci_init_ocp(struct rtsx_pcr *pcr);
119*4882a593Smuzhiyun void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr);
120*4882a593Smuzhiyun void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr);
121*4882a593Smuzhiyun int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val);
122*4882a593Smuzhiyun void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr);
123*4882a593Smuzhiyun void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr);
124*4882a593Smuzhiyun void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr);
125*4882a593Smuzhiyun int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr);
126*4882a593Smuzhiyun int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #endif
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