1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* Driver for Realtek PCI-Express card reader 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: 7*4882a593Smuzhiyun * Rui FENG <rui_feng@realsil.com.cn> 8*4882a593Smuzhiyun * Wei WANG <wei_wang@realsil.com.cn> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef RTS5261_H 11*4882a593Smuzhiyun #define RTS5261_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /*New add*/ 14*4882a593Smuzhiyun #define rts5261_vendor_setting_valid(reg) ((reg) & 0x010000) 15*4882a593Smuzhiyun #define rts5261_reg_to_aspm(reg) (((reg) >> 28) ^ 0x03) 16*4882a593Smuzhiyun #define rts5261_reg_check_reverse_socket(reg) ((reg) & 0x04) 17*4882a593Smuzhiyun #define rts5261_reg_to_card_drive_sel(reg) ((((reg) >> 6) & 0x01) << 6) 18*4882a593Smuzhiyun #define rts5261_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) ^ 0x03) 19*4882a593Smuzhiyun #define rts5261_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) ^ 0x03) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define RTS5261_AUTOLOAD_CFG0 0xFF7B 23*4882a593Smuzhiyun #define RTS5261_AUTOLOAD_CFG1 0xFF7C 24*4882a593Smuzhiyun #define RTS5261_AUTOLOAD_CFG2 0xFF7D 25*4882a593Smuzhiyun #define RTS5261_AUTOLOAD_CFG3 0xFF7E 26*4882a593Smuzhiyun #define RTS5261_AUTOLOAD_CFG4 0xFF7F 27*4882a593Smuzhiyun #define RTS5261_FORCE_PRSNT_LOW (1 << 6) 28*4882a593Smuzhiyun #define RTS5261_AUX_CLK_16M_EN (1 << 5) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define RTS5261_REG_VREF 0xFE97 31*4882a593Smuzhiyun #define RTS5261_PWD_SUSPND_EN (1 << 4) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define RTS5261_PAD_H3L1 0xFF79 34*4882a593Smuzhiyun #define PAD_GPIO_H3L1 (1 << 3) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* SSC_CTL2 0xFC12 */ 37*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_MASK 0x07 38*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_DISALBE 0x00 39*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_8M 0x01 40*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_4M 0x02 41*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_2M 0x03 42*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_1M 0x04 43*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_512K 0x05 44*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_256K 0x06 45*4882a593Smuzhiyun #define RTS5261_SSC_DEPTH_128K 0x07 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* efuse control register*/ 48*4882a593Smuzhiyun #define RTS5261_EFUSE_CTL 0xFC30 49*4882a593Smuzhiyun #define RTS5261_EFUSE_ENABLE 0x80 50*4882a593Smuzhiyun /* EFUSE_MODE: 0=READ 1=PROGRAM */ 51*4882a593Smuzhiyun #define RTS5261_EFUSE_MODE_MASK 0x40 52*4882a593Smuzhiyun #define RTS5261_EFUSE_PROGRAM 0x40 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define RTS5261_EFUSE_ADDR 0xFC31 55*4882a593Smuzhiyun #define RTS5261_EFUSE_ADDR_MASK 0x3F 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define RTS5261_EFUSE_WRITE_DATA 0xFC32 58*4882a593Smuzhiyun #define RTS5261_EFUSE_READ_DATA 0xFC34 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* DMACTL 0xFE2C */ 61*4882a593Smuzhiyun #define RTS5261_DMA_PACK_SIZE_MASK 0xF0 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* FW config info register */ 64*4882a593Smuzhiyun #define RTS5261_FW_CFG_INFO0 0xFF50 65*4882a593Smuzhiyun #define RTS5261_FW_EXPRESS_TEST_MASK (0x01<<0) 66*4882a593Smuzhiyun #define RTS5261_FW_EA_MODE_MASK (0x01<<5) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* FW config register */ 69*4882a593Smuzhiyun #define RTS5261_FW_CFG0 0xFF54 70*4882a593Smuzhiyun #define RTS5261_FW_ENTER_EXPRESS (0x01<<0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define RTS5261_FW_CFG1 0xFF55 73*4882a593Smuzhiyun #define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01<<7) 74*4882a593Smuzhiyun #define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01<<6) 75*4882a593Smuzhiyun #define RTS5261_FAKE_MCU_CLOCK_GATING (0x01<<5) 76*4882a593Smuzhiyun /*MCU_bus_mode_sel: 0=real 8051 1=fake mcu*/ 77*4882a593Smuzhiyun #define RTS5261_MCU_BUS_SEL_MASK (0x01<<4) 78*4882a593Smuzhiyun /*MCU_clock_sel:VerA 00=aux16M 01=aux400K 1x=REFCLK100M*/ 79*4882a593Smuzhiyun /*MCU_clock_sel:VerB 00=aux400K 01=aux16M 10=REFCLK100M*/ 80*4882a593Smuzhiyun #define RTS5261_MCU_CLOCK_SEL_MASK (0x03<<2) 81*4882a593Smuzhiyun #define RTS5261_MCU_CLOCK_SEL_16M (0x01<<2) 82*4882a593Smuzhiyun #define RTS5261_MCU_CLOCK_GATING (0x01<<1) 83*4882a593Smuzhiyun #define RTS5261_DRIVER_ENABLE_FW (0x01<<0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* FW status register */ 86*4882a593Smuzhiyun #define RTS5261_FW_STATUS 0xFF56 87*4882a593Smuzhiyun #define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* FW control register */ 90*4882a593Smuzhiyun #define RTS5261_FW_CTL 0xFF5F 91*4882a593Smuzhiyun #define RTS5261_INFORM_RTD3_COLD (0x01<<5) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define RTS5261_REG_FPDCTL 0xFF60 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define RTS5261_REG_LDO12_CFG 0xFF6E 96*4882a593Smuzhiyun #define RTS5261_LDO12_VO_TUNE_MASK (0x07<<1) 97*4882a593Smuzhiyun #define RTS5261_LDO12_115 (0x03<<1) 98*4882a593Smuzhiyun #define RTS5261_LDO12_120 (0x04<<1) 99*4882a593Smuzhiyun #define RTS5261_LDO12_125 (0x05<<1) 100*4882a593Smuzhiyun #define RTS5261_LDO12_130 (0x06<<1) 101*4882a593Smuzhiyun #define RTS5261_LDO12_135 (0x07<<1) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* LDO control register */ 104*4882a593Smuzhiyun #define RTS5261_CARD_PWR_CTL 0xFD50 105*4882a593Smuzhiyun #define RTS5261_SD_CLK_ISO (0x01<<7) 106*4882a593Smuzhiyun #define RTS5261_PAD_SD_DAT_FW_CTRL (0x01<<6) 107*4882a593Smuzhiyun #define RTS5261_PUPDC (0x01<<5) 108*4882a593Smuzhiyun #define RTS5261_SD_CMD_ISO (0x01<<4) 109*4882a593Smuzhiyun #define RTS5261_SD_DAT_ISO_MASK (0x0F<<0) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define RTS5261_LDO1233318_POW_CTL 0xFF70 112*4882a593Smuzhiyun #define RTS5261_LDO3318_POWERON (0x01<<3) 113*4882a593Smuzhiyun #define RTS5261_LDO3_POWERON (0x01<<2) 114*4882a593Smuzhiyun #define RTS5261_LDO2_POWERON (0x01<<1) 115*4882a593Smuzhiyun #define RTS5261_LDO1_POWERON (0x01<<0) 116*4882a593Smuzhiyun #define RTS5261_LDO_POWERON_MASK (0x0F<<0) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define RTS5261_DV3318_CFG 0xFF71 119*4882a593Smuzhiyun #define RTS5261_DV3318_TUNE_MASK (0x07<<4) 120*4882a593Smuzhiyun #define RTS5261_DV3318_18 (0x02<<4) 121*4882a593Smuzhiyun #define RTS5261_DV3318_19 (0x04<<4) 122*4882a593Smuzhiyun #define RTS5261_DV3318_33 (0x07<<4) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define RTS5261_LDO1_CFG0 0xFF72 125*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_MASK (0x07<<5) 126*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_EN (0x01<<4) 127*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03<<2) 128*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_LMT_EN (0x01<<1) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* CRD6603-433 190319 request changed */ 131*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_740 (0x00<<5) 132*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_800 (0x01<<5) 133*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_860 (0x02<<5) 134*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_920 (0x03<<5) 135*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_980 (0x04<<5) 136*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_1040 (0x05<<5) 137*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_1100 (0x06<<5) 138*4882a593Smuzhiyun #define RTS5261_LDO1_OCP_THD_1160 (0x07<<5) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define RTS5261_LDO1_LMT_THD_450 (0x00<<2) 141*4882a593Smuzhiyun #define RTS5261_LDO1_LMT_THD_1000 (0x01<<2) 142*4882a593Smuzhiyun #define RTS5261_LDO1_LMT_THD_1500 (0x02<<2) 143*4882a593Smuzhiyun #define RTS5261_LDO1_LMT_THD_2000 (0x03<<2) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define RTS5261_LDO1_CFG1 0xFF73 146*4882a593Smuzhiyun #define RTS5261_LDO1_TUNE_MASK (0x07<<1) 147*4882a593Smuzhiyun #define RTS5261_LDO1_18 (0x05<<1) 148*4882a593Smuzhiyun #define RTS5261_LDO1_33 (0x07<<1) 149*4882a593Smuzhiyun #define RTS5261_LDO1_PWD_MASK (0x01<<0) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define RTS5261_LDO2_CFG0 0xFF74 152*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_MASK (0x07<<5) 153*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_EN (0x01<<4) 154*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_LMT_THD_MASK (0x03<<2) 155*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_LMT_EN (0x01<<1) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_620 (0x00<<5) 158*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_650 (0x01<<5) 159*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_680 (0x02<<5) 160*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_720 (0x03<<5) 161*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_750 (0x04<<5) 162*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_780 (0x05<<5) 163*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_810 (0x06<<5) 164*4882a593Smuzhiyun #define RTS5261_LDO2_OCP_THD_840 (0x07<<5) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define RTS5261_LDO2_CFG1 0xFF75 167*4882a593Smuzhiyun #define RTS5261_LDO2_TUNE_MASK (0x07<<1) 168*4882a593Smuzhiyun #define RTS5261_LDO2_18 (0x05<<1) 169*4882a593Smuzhiyun #define RTS5261_LDO2_33 (0x07<<1) 170*4882a593Smuzhiyun #define RTS5261_LDO2_PWD_MASK (0x01<<0) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define RTS5261_LDO3_CFG0 0xFF76 173*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_MASK (0x07<<5) 174*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_EN (0x01<<4) 175*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_LMT_THD_MASK (0x03<<2) 176*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_LMT_EN (0x01<<1) 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_620 (0x00<<5) 179*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_650 (0x01<<5) 180*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_680 (0x02<<5) 181*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_720 (0x03<<5) 182*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_750 (0x04<<5) 183*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_780 (0x05<<5) 184*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_810 (0x06<<5) 185*4882a593Smuzhiyun #define RTS5261_LDO3_OCP_THD_840 (0x07<<5) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define RTS5261_LDO3_CFG1 0xFF77 188*4882a593Smuzhiyun #define RTS5261_LDO3_TUNE_MASK (0x07<<1) 189*4882a593Smuzhiyun #define RTS5261_LDO3_18 (0x05<<1) 190*4882a593Smuzhiyun #define RTS5261_LDO3_33 (0x07<<1) 191*4882a593Smuzhiyun #define RTS5261_LDO3_PWD_MASK (0x01<<0) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define RTS5261_REG_PME_FORCE_CTL 0xFF78 194*4882a593Smuzhiyun #define FORCE_PM_CONTROL 0x20 195*4882a593Smuzhiyun #define FORCE_PM_VALUE 0x10 196*4882a593Smuzhiyun #define REG_EFUSE_BYPASS 0x08 197*4882a593Smuzhiyun #define REG_EFUSE_POR 0x04 198*4882a593Smuzhiyun #define REG_EFUSE_POWER_MASK 0x03 199*4882a593Smuzhiyun #define REG_EFUSE_POWERON 0x03 200*4882a593Smuzhiyun #define REG_EFUSE_POWEROFF 0x00 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Single LUN, support SD/SD EXPRESS */ 204*4882a593Smuzhiyun #define DEFAULT_SINGLE 0 205*4882a593Smuzhiyun #define SD_LUN 1 206*4882a593Smuzhiyun #define SD_EXPRESS_LUN 2 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* For Change_FPGA_SSCClock Function */ 209*4882a593Smuzhiyun #define MULTIPLY_BY_1 0x00 210*4882a593Smuzhiyun #define MULTIPLY_BY_2 0x01 211*4882a593Smuzhiyun #define MULTIPLY_BY_3 0x02 212*4882a593Smuzhiyun #define MULTIPLY_BY_4 0x03 213*4882a593Smuzhiyun #define MULTIPLY_BY_5 0x04 214*4882a593Smuzhiyun #define MULTIPLY_BY_6 0x05 215*4882a593Smuzhiyun #define MULTIPLY_BY_7 0x06 216*4882a593Smuzhiyun #define MULTIPLY_BY_8 0x07 217*4882a593Smuzhiyun #define MULTIPLY_BY_9 0x08 218*4882a593Smuzhiyun #define MULTIPLY_BY_10 0x09 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #define DIVIDE_BY_2 0x01 221*4882a593Smuzhiyun #define DIVIDE_BY_3 0x02 222*4882a593Smuzhiyun #define DIVIDE_BY_4 0x03 223*4882a593Smuzhiyun #define DIVIDE_BY_5 0x04 224*4882a593Smuzhiyun #define DIVIDE_BY_6 0x05 225*4882a593Smuzhiyun #define DIVIDE_BY_7 0x06 226*4882a593Smuzhiyun #define DIVIDE_BY_8 0x07 227*4882a593Smuzhiyun #define DIVIDE_BY_9 0x08 228*4882a593Smuzhiyun #define DIVIDE_BY_10 0x09 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 231*4882a593Smuzhiyun u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #endif /* RTS5261_H */ 234