1*4882a593Smuzhiyun #ifndef __RTS5260_H__ 2*4882a593Smuzhiyun #define __RTS5260_H__ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define RTS5260_DVCC_CTRL 0xFF73 5*4882a593Smuzhiyun #define RTS5260_DVCC_OCP_EN (0x01 << 7) 6*4882a593Smuzhiyun #define RTS5260_DVCC_OCP_THD_MASK (0x07 << 4) 7*4882a593Smuzhiyun #define RTS5260_DVCC_POWERON (0x01 << 3) 8*4882a593Smuzhiyun #define RTS5260_DVCC_OCP_CL_EN (0x01 << 2) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define RTS5260_DVIO_CTRL 0xFF75 11*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_EN (0x01 << 7) 12*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_MASK (0x07 << 4) 13*4882a593Smuzhiyun #define RTS5260_DVIO_POWERON (0x01 << 3) 14*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_CL_EN (0x01 << 2) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define RTS5260_DV331812_CFG 0xFF71 17*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_EN (0x01 << 7) 18*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_MASK (0x07 << 4) 19*4882a593Smuzhiyun #define RTS5260_DV331812_POWERON (0x01 << 3) 20*4882a593Smuzhiyun #define RTS5260_DV331812_SEL (0x01 << 2) 21*4882a593Smuzhiyun #define RTS5260_DV331812_VDD1 (0x01 << 2) 22*4882a593Smuzhiyun #define RTS5260_DV331812_VDD2 (0x00 << 2) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_120 (0x00 << 4) 25*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_140 (0x01 << 4) 26*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_160 (0x02 << 4) 27*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_180 (0x03 << 4) 28*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_210 (0x04 << 4) 29*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_240 (0x05 << 4) 30*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_270 (0x06 << 4) 31*4882a593Smuzhiyun #define RTS5260_DV331812_OCP_THD_300 (0x07 << 4) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_250 (0x00 << 4) 34*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_300 (0x01 << 4) 35*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_350 (0x02 << 4) 36*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_400 (0x03 << 4) 37*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_450 (0x04 << 4) 38*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_500 (0x05 << 4) 39*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_550 (0x06 << 4) 40*4882a593Smuzhiyun #define RTS5260_DVIO_OCP_THD_600 (0x07 << 4) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define RTS5260_DVCC_OCP_THD_550 (0x00 << 4) 43*4882a593Smuzhiyun #define RTS5260_DVCC_OCP_THD_970 (0x05 << 4) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46