1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /* Driver for Realtek PCI-Express card reader
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author:
7*4882a593Smuzhiyun * Wei WANG <wei_wang@realsil.com.cn>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/rtsx_pci.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "rtsx_pcr.h"
15*4882a593Smuzhiyun
rts5229_get_ic_version(struct rtsx_pcr * pcr)16*4882a593Smuzhiyun static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun u8 val;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
21*4882a593Smuzhiyun return val & 0x0F;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
rts5229_fetch_vendor_settings(struct rtsx_pcr * pcr)24*4882a593Smuzhiyun static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct pci_dev *pdev = pcr->pci;
27*4882a593Smuzhiyun u32 reg;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
30*4882a593Smuzhiyun pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun if (!rtsx_vendor_setting_valid(reg))
33*4882a593Smuzhiyun return;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun pcr->aspm_en = rtsx_reg_to_aspm(reg);
36*4882a593Smuzhiyun pcr->sd30_drive_sel_1v8 =
37*4882a593Smuzhiyun map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
38*4882a593Smuzhiyun pcr->card_drive_sel &= 0x3F;
39*4882a593Smuzhiyun pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
42*4882a593Smuzhiyun pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
43*4882a593Smuzhiyun pcr->sd30_drive_sel_3v3 =
44*4882a593Smuzhiyun map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg));
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
rts5229_force_power_down(struct rtsx_pcr * pcr,u8 pm_state)47*4882a593Smuzhiyun static void rts5229_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
rts5229_extra_init_hw(struct rtsx_pcr * pcr)52*4882a593Smuzhiyun static int rts5229_extra_init_hw(struct rtsx_pcr *pcr)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun rtsx_pci_init_cmd(pcr);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Configure GPIO as output */
57*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
58*4882a593Smuzhiyun /* Reset ASPM state to default value */
59*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
60*4882a593Smuzhiyun /* Force CLKREQ# PIN to drive 0 to request clock */
61*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
62*4882a593Smuzhiyun /* Switch LDO3318 source from DV33 to card_3v3 */
63*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
64*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
65*4882a593Smuzhiyun /* LED shine disabled, set initial shine cycle period */
66*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
67*4882a593Smuzhiyun /* Configure driving */
68*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
69*4882a593Smuzhiyun 0xFF, pcr->sd30_drive_sel_3v3);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return rtsx_pci_send_cmd(pcr, 100);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
rts5229_optimize_phy(struct rtsx_pcr * pcr)74*4882a593Smuzhiyun static int rts5229_optimize_phy(struct rtsx_pcr *pcr)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun /* Optimize RX sensitivity */
77*4882a593Smuzhiyun return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
rts5229_turn_on_led(struct rtsx_pcr * pcr)80*4882a593Smuzhiyun static int rts5229_turn_on_led(struct rtsx_pcr *pcr)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
rts5229_turn_off_led(struct rtsx_pcr * pcr)85*4882a593Smuzhiyun static int rts5229_turn_off_led(struct rtsx_pcr *pcr)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
rts5229_enable_auto_blink(struct rtsx_pcr * pcr)90*4882a593Smuzhiyun static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
rts5229_disable_auto_blink(struct rtsx_pcr * pcr)95*4882a593Smuzhiyun static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
rts5229_card_power_on(struct rtsx_pcr * pcr,int card)100*4882a593Smuzhiyun static int rts5229_card_power_on(struct rtsx_pcr *pcr, int card)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun int err;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun rtsx_pci_init_cmd(pcr);
105*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
106*4882a593Smuzhiyun SD_POWER_MASK, SD_PARTIAL_POWER_ON);
107*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
108*4882a593Smuzhiyun LDO3318_PWR_MASK, 0x02);
109*4882a593Smuzhiyun err = rtsx_pci_send_cmd(pcr, 100);
110*4882a593Smuzhiyun if (err < 0)
111*4882a593Smuzhiyun return err;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* To avoid too large in-rush current */
114*4882a593Smuzhiyun udelay(150);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun rtsx_pci_init_cmd(pcr);
117*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
118*4882a593Smuzhiyun SD_POWER_MASK, SD_POWER_ON);
119*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
120*4882a593Smuzhiyun LDO3318_PWR_MASK, 0x06);
121*4882a593Smuzhiyun return rtsx_pci_send_cmd(pcr, 100);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
rts5229_card_power_off(struct rtsx_pcr * pcr,int card)124*4882a593Smuzhiyun static int rts5229_card_power_off(struct rtsx_pcr *pcr, int card)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun rtsx_pci_init_cmd(pcr);
127*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
128*4882a593Smuzhiyun SD_POWER_MASK | PMOS_STRG_MASK,
129*4882a593Smuzhiyun SD_POWER_OFF | PMOS_STRG_400mA);
130*4882a593Smuzhiyun rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
131*4882a593Smuzhiyun LDO3318_PWR_MASK, 0x00);
132*4882a593Smuzhiyun return rtsx_pci_send_cmd(pcr, 100);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
rts5229_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)135*4882a593Smuzhiyun static int rts5229_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun int err;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (voltage == OUTPUT_3V3) {
140*4882a593Smuzhiyun err = rtsx_pci_write_register(pcr,
141*4882a593Smuzhiyun SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
142*4882a593Smuzhiyun if (err < 0)
143*4882a593Smuzhiyun return err;
144*4882a593Smuzhiyun err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
145*4882a593Smuzhiyun if (err < 0)
146*4882a593Smuzhiyun return err;
147*4882a593Smuzhiyun } else if (voltage == OUTPUT_1V8) {
148*4882a593Smuzhiyun err = rtsx_pci_write_register(pcr,
149*4882a593Smuzhiyun SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
150*4882a593Smuzhiyun if (err < 0)
151*4882a593Smuzhiyun return err;
152*4882a593Smuzhiyun err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
153*4882a593Smuzhiyun if (err < 0)
154*4882a593Smuzhiyun return err;
155*4882a593Smuzhiyun } else {
156*4882a593Smuzhiyun return -EINVAL;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return 0;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct pcr_ops rts5229_pcr_ops = {
163*4882a593Smuzhiyun .fetch_vendor_settings = rts5229_fetch_vendor_settings,
164*4882a593Smuzhiyun .extra_init_hw = rts5229_extra_init_hw,
165*4882a593Smuzhiyun .optimize_phy = rts5229_optimize_phy,
166*4882a593Smuzhiyun .turn_on_led = rts5229_turn_on_led,
167*4882a593Smuzhiyun .turn_off_led = rts5229_turn_off_led,
168*4882a593Smuzhiyun .enable_auto_blink = rts5229_enable_auto_blink,
169*4882a593Smuzhiyun .disable_auto_blink = rts5229_disable_auto_blink,
170*4882a593Smuzhiyun .card_power_on = rts5229_card_power_on,
171*4882a593Smuzhiyun .card_power_off = rts5229_card_power_off,
172*4882a593Smuzhiyun .switch_output_voltage = rts5229_switch_output_voltage,
173*4882a593Smuzhiyun .cd_deglitch = NULL,
174*4882a593Smuzhiyun .conv_clk_and_div_n = NULL,
175*4882a593Smuzhiyun .force_power_down = rts5229_force_power_down,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /* SD Pull Control Enable:
179*4882a593Smuzhiyun * SD_DAT[3:0] ==> pull up
180*4882a593Smuzhiyun * SD_CD ==> pull up
181*4882a593Smuzhiyun * SD_WP ==> pull up
182*4882a593Smuzhiyun * SD_CMD ==> pull up
183*4882a593Smuzhiyun * SD_CLK ==> pull down
184*4882a593Smuzhiyun */
185*4882a593Smuzhiyun static const u32 rts5229_sd_pull_ctl_enable_tbl1[] = {
186*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
187*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
188*4882a593Smuzhiyun 0,
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* For RTS5229 version C */
192*4882a593Smuzhiyun static const u32 rts5229_sd_pull_ctl_enable_tbl2[] = {
193*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
194*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD9),
195*4882a593Smuzhiyun 0,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* SD Pull Control Disable:
199*4882a593Smuzhiyun * SD_DAT[3:0] ==> pull down
200*4882a593Smuzhiyun * SD_CD ==> pull up
201*4882a593Smuzhiyun * SD_WP ==> pull down
202*4882a593Smuzhiyun * SD_CMD ==> pull down
203*4882a593Smuzhiyun * SD_CLK ==> pull down
204*4882a593Smuzhiyun */
205*4882a593Smuzhiyun static const u32 rts5229_sd_pull_ctl_disable_tbl1[] = {
206*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
207*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
208*4882a593Smuzhiyun 0,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* For RTS5229 version C */
212*4882a593Smuzhiyun static const u32 rts5229_sd_pull_ctl_disable_tbl2[] = {
213*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
214*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE5),
215*4882a593Smuzhiyun 0,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* MS Pull Control Enable:
219*4882a593Smuzhiyun * MS CD ==> pull up
220*4882a593Smuzhiyun * others ==> pull down
221*4882a593Smuzhiyun */
222*4882a593Smuzhiyun static const u32 rts5229_ms_pull_ctl_enable_tbl[] = {
223*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
224*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
225*4882a593Smuzhiyun 0,
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* MS Pull Control Disable:
229*4882a593Smuzhiyun * MS CD ==> pull up
230*4882a593Smuzhiyun * others ==> pull down
231*4882a593Smuzhiyun */
232*4882a593Smuzhiyun static const u32 rts5229_ms_pull_ctl_disable_tbl[] = {
233*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
234*4882a593Smuzhiyun RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
235*4882a593Smuzhiyun 0,
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
rts5229_init_params(struct rtsx_pcr * pcr)238*4882a593Smuzhiyun void rts5229_init_params(struct rtsx_pcr *pcr)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
241*4882a593Smuzhiyun pcr->num_slots = 2;
242*4882a593Smuzhiyun pcr->ops = &rts5229_pcr_ops;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun pcr->flags = 0;
245*4882a593Smuzhiyun pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
246*4882a593Smuzhiyun pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
247*4882a593Smuzhiyun pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
248*4882a593Smuzhiyun pcr->aspm_en = ASPM_L1_EN;
249*4882a593Smuzhiyun pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
250*4882a593Smuzhiyun pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun pcr->ic_version = rts5229_get_ic_version(pcr);
253*4882a593Smuzhiyun if (pcr->ic_version == IC_VER_C) {
254*4882a593Smuzhiyun pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl2;
255*4882a593Smuzhiyun pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl2;
256*4882a593Smuzhiyun } else {
257*4882a593Smuzhiyun pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl1;
258*4882a593Smuzhiyun pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl1;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun pcr->ms_pull_ctl_enable_tbl = rts5229_ms_pull_ctl_enable_tbl;
261*4882a593Smuzhiyun pcr->ms_pull_ctl_disable_tbl = rts5229_ms_pull_ctl_disable_tbl;
262*4882a593Smuzhiyun }
263