xref: /OK3568_Linux_fs/kernel/drivers/misc/cardreader/rts5209.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /* Driver for Realtek PCI-Express card reader
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Author:
7*4882a593Smuzhiyun  *   Wei WANG <wei_wang@realsil.com.cn>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/rtsx_pci.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include "rtsx_pcr.h"
15*4882a593Smuzhiyun 
rts5209_get_ic_version(struct rtsx_pcr * pcr)16*4882a593Smuzhiyun static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun 	u8 val;
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun 	val = rtsx_pci_readb(pcr, 0x1C);
21*4882a593Smuzhiyun 	return val & 0x0F;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun 
rts5209_fetch_vendor_settings(struct rtsx_pcr * pcr)24*4882a593Smuzhiyun static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	struct pci_dev *pdev = pcr->pci;
27*4882a593Smuzhiyun 	u32 reg;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
30*4882a593Smuzhiyun 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	if (rts5209_vendor_setting1_valid(reg)) {
33*4882a593Smuzhiyun 		if (rts5209_reg_check_ms_pmos(reg))
34*4882a593Smuzhiyun 			pcr->flags |= PCR_MS_PMOS;
35*4882a593Smuzhiyun 		pcr->aspm_en = rts5209_reg_to_aspm(reg);
36*4882a593Smuzhiyun 	}
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
39*4882a593Smuzhiyun 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	if (rts5209_vendor_setting2_valid(reg)) {
42*4882a593Smuzhiyun 		pcr->sd30_drive_sel_1v8 =
43*4882a593Smuzhiyun 			rts5209_reg_to_sd30_drive_sel_1v8(reg);
44*4882a593Smuzhiyun 		pcr->sd30_drive_sel_3v3 =
45*4882a593Smuzhiyun 			rts5209_reg_to_sd30_drive_sel_3v3(reg);
46*4882a593Smuzhiyun 		pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg);
47*4882a593Smuzhiyun 	}
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
rts5209_force_power_down(struct rtsx_pcr * pcr,u8 pm_state)50*4882a593Smuzhiyun static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
rts5209_extra_init_hw(struct rtsx_pcr * pcr)55*4882a593Smuzhiyun static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	rtsx_pci_init_cmd(pcr);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	/* Turn off LED */
60*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
61*4882a593Smuzhiyun 	/* Reset ASPM state to default value */
62*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
63*4882a593Smuzhiyun 	/* Force CLKREQ# PIN to drive 0 to request clock */
64*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
65*4882a593Smuzhiyun 	/* Configure GPIO as output */
66*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
67*4882a593Smuzhiyun 	/* Configure driving */
68*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
69*4882a593Smuzhiyun 			0xFF, pcr->sd30_drive_sel_3v3);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	return rtsx_pci_send_cmd(pcr, 100);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
rts5209_optimize_phy(struct rtsx_pcr * pcr)74*4882a593Smuzhiyun static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
rts5209_turn_on_led(struct rtsx_pcr * pcr)79*4882a593Smuzhiyun static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
rts5209_turn_off_led(struct rtsx_pcr * pcr)84*4882a593Smuzhiyun static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
rts5209_enable_auto_blink(struct rtsx_pcr * pcr)89*4882a593Smuzhiyun static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
rts5209_disable_auto_blink(struct rtsx_pcr * pcr)94*4882a593Smuzhiyun static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun 	return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
rts5209_card_power_on(struct rtsx_pcr * pcr,int card)99*4882a593Smuzhiyun static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	int err;
102*4882a593Smuzhiyun 	u8 pwr_mask, partial_pwr_on, pwr_on;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	pwr_mask = SD_POWER_MASK;
105*4882a593Smuzhiyun 	partial_pwr_on = SD_PARTIAL_POWER_ON;
106*4882a593Smuzhiyun 	pwr_on = SD_POWER_ON;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
109*4882a593Smuzhiyun 		pwr_mask = MS_POWER_MASK;
110*4882a593Smuzhiyun 		partial_pwr_on = MS_PARTIAL_POWER_ON;
111*4882a593Smuzhiyun 		pwr_on = MS_POWER_ON;
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	rtsx_pci_init_cmd(pcr);
115*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
116*4882a593Smuzhiyun 			pwr_mask, partial_pwr_on);
117*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
118*4882a593Smuzhiyun 			LDO3318_PWR_MASK, 0x04);
119*4882a593Smuzhiyun 	err = rtsx_pci_send_cmd(pcr, 100);
120*4882a593Smuzhiyun 	if (err < 0)
121*4882a593Smuzhiyun 		return err;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* To avoid too large in-rush current */
124*4882a593Smuzhiyun 	udelay(150);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	rtsx_pci_init_cmd(pcr);
127*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
128*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
129*4882a593Smuzhiyun 			LDO3318_PWR_MASK, 0x00);
130*4882a593Smuzhiyun 	return rtsx_pci_send_cmd(pcr, 100);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
rts5209_card_power_off(struct rtsx_pcr * pcr,int card)133*4882a593Smuzhiyun static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	u8 pwr_mask, pwr_off;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	pwr_mask = SD_POWER_MASK;
138*4882a593Smuzhiyun 	pwr_off = SD_POWER_OFF;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
141*4882a593Smuzhiyun 		pwr_mask = MS_POWER_MASK;
142*4882a593Smuzhiyun 		pwr_off = MS_POWER_OFF;
143*4882a593Smuzhiyun 	}
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	rtsx_pci_init_cmd(pcr);
146*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
147*4882a593Smuzhiyun 			pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA);
148*4882a593Smuzhiyun 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
149*4882a593Smuzhiyun 			LDO3318_PWR_MASK, 0x06);
150*4882a593Smuzhiyun 	return rtsx_pci_send_cmd(pcr, 100);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
rts5209_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)153*4882a593Smuzhiyun static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	int err;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	if (voltage == OUTPUT_3V3) {
158*4882a593Smuzhiyun 		err = rtsx_pci_write_register(pcr,
159*4882a593Smuzhiyun 				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
160*4882a593Smuzhiyun 		if (err < 0)
161*4882a593Smuzhiyun 			return err;
162*4882a593Smuzhiyun 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
163*4882a593Smuzhiyun 		if (err < 0)
164*4882a593Smuzhiyun 			return err;
165*4882a593Smuzhiyun 	} else if (voltage == OUTPUT_1V8) {
166*4882a593Smuzhiyun 		err = rtsx_pci_write_register(pcr,
167*4882a593Smuzhiyun 				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
168*4882a593Smuzhiyun 		if (err < 0)
169*4882a593Smuzhiyun 			return err;
170*4882a593Smuzhiyun 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
171*4882a593Smuzhiyun 		if (err < 0)
172*4882a593Smuzhiyun 			return err;
173*4882a593Smuzhiyun 	} else {
174*4882a593Smuzhiyun 		return -EINVAL;
175*4882a593Smuzhiyun 	}
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	return 0;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun static const struct pcr_ops rts5209_pcr_ops = {
181*4882a593Smuzhiyun 	.fetch_vendor_settings = rts5209_fetch_vendor_settings,
182*4882a593Smuzhiyun 	.extra_init_hw = rts5209_extra_init_hw,
183*4882a593Smuzhiyun 	.optimize_phy = rts5209_optimize_phy,
184*4882a593Smuzhiyun 	.turn_on_led = rts5209_turn_on_led,
185*4882a593Smuzhiyun 	.turn_off_led = rts5209_turn_off_led,
186*4882a593Smuzhiyun 	.enable_auto_blink = rts5209_enable_auto_blink,
187*4882a593Smuzhiyun 	.disable_auto_blink = rts5209_disable_auto_blink,
188*4882a593Smuzhiyun 	.card_power_on = rts5209_card_power_on,
189*4882a593Smuzhiyun 	.card_power_off = rts5209_card_power_off,
190*4882a593Smuzhiyun 	.switch_output_voltage = rts5209_switch_output_voltage,
191*4882a593Smuzhiyun 	.cd_deglitch = NULL,
192*4882a593Smuzhiyun 	.conv_clk_and_div_n = NULL,
193*4882a593Smuzhiyun 	.force_power_down = rts5209_force_power_down,
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /* SD Pull Control Enable:
197*4882a593Smuzhiyun  *     SD_DAT[3:0] ==> pull up
198*4882a593Smuzhiyun  *     SD_CD       ==> pull up
199*4882a593Smuzhiyun  *     SD_WP       ==> pull up
200*4882a593Smuzhiyun  *     SD_CMD      ==> pull up
201*4882a593Smuzhiyun  *     SD_CLK      ==> pull down
202*4882a593Smuzhiyun  */
203*4882a593Smuzhiyun static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
204*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
205*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
206*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
207*4882a593Smuzhiyun 	0,
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun /* SD Pull Control Disable:
211*4882a593Smuzhiyun  *     SD_DAT[3:0] ==> pull down
212*4882a593Smuzhiyun  *     SD_CD       ==> pull up
213*4882a593Smuzhiyun  *     SD_WP       ==> pull down
214*4882a593Smuzhiyun  *     SD_CMD      ==> pull down
215*4882a593Smuzhiyun  *     SD_CLK      ==> pull down
216*4882a593Smuzhiyun  */
217*4882a593Smuzhiyun static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
218*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
219*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
220*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
221*4882a593Smuzhiyun 	0,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /* MS Pull Control Enable:
225*4882a593Smuzhiyun  *     MS CD       ==> pull up
226*4882a593Smuzhiyun  *     others      ==> pull down
227*4882a593Smuzhiyun  */
228*4882a593Smuzhiyun static const u32 rts5209_ms_pull_ctl_enable_tbl[] = {
229*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
230*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
231*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
232*4882a593Smuzhiyun 	0,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun /* MS Pull Control Disable:
236*4882a593Smuzhiyun  *     MS CD       ==> pull up
237*4882a593Smuzhiyun  *     others      ==> pull down
238*4882a593Smuzhiyun  */
239*4882a593Smuzhiyun static const u32 rts5209_ms_pull_ctl_disable_tbl[] = {
240*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
241*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
242*4882a593Smuzhiyun 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
243*4882a593Smuzhiyun 	0,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
rts5209_init_params(struct rtsx_pcr * pcr)246*4882a593Smuzhiyun void rts5209_init_params(struct rtsx_pcr *pcr)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
249*4882a593Smuzhiyun 		EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
250*4882a593Smuzhiyun 	pcr->num_slots = 2;
251*4882a593Smuzhiyun 	pcr->ops = &rts5209_pcr_ops;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	pcr->flags = 0;
254*4882a593Smuzhiyun 	pcr->card_drive_sel = RTS5209_CARD_DRIVE_DEFAULT;
255*4882a593Smuzhiyun 	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
256*4882a593Smuzhiyun 	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
257*4882a593Smuzhiyun 	pcr->aspm_en = ASPM_L1_EN;
258*4882a593Smuzhiyun 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
259*4882a593Smuzhiyun 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	pcr->ic_version = rts5209_get_ic_version(pcr);
262*4882a593Smuzhiyun 	pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
263*4882a593Smuzhiyun 	pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
264*4882a593Smuzhiyun 	pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
265*4882a593Smuzhiyun 	pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;
266*4882a593Smuzhiyun }
267