1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8994-regmap.c -- Register map data for WM8994 series devices
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2011 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/mfd/wm8994/core.h>
11*4882a593Smuzhiyun #include <linux/mfd/wm8994/registers.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "wm8994.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static const struct reg_default wm1811_defaults[] = {
18*4882a593Smuzhiyun { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19*4882a593Smuzhiyun { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20*4882a593Smuzhiyun { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21*4882a593Smuzhiyun { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22*4882a593Smuzhiyun { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23*4882a593Smuzhiyun { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24*4882a593Smuzhiyun { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25*4882a593Smuzhiyun { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26*4882a593Smuzhiyun { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27*4882a593Smuzhiyun { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
28*4882a593Smuzhiyun { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
29*4882a593Smuzhiyun { 0x001C, 0x006D }, /* R28 - Left Output Volume */
30*4882a593Smuzhiyun { 0x001D, 0x006D }, /* R29 - Right Output Volume */
31*4882a593Smuzhiyun { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
32*4882a593Smuzhiyun { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
33*4882a593Smuzhiyun { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
34*4882a593Smuzhiyun { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
35*4882a593Smuzhiyun { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
36*4882a593Smuzhiyun { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
37*4882a593Smuzhiyun { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
38*4882a593Smuzhiyun { 0x0025, 0x0140 }, /* R37 - ClassD */
39*4882a593Smuzhiyun { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
40*4882a593Smuzhiyun { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
41*4882a593Smuzhiyun { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
42*4882a593Smuzhiyun { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
43*4882a593Smuzhiyun { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
44*4882a593Smuzhiyun { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
45*4882a593Smuzhiyun { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
46*4882a593Smuzhiyun { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
47*4882a593Smuzhiyun { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
48*4882a593Smuzhiyun { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
49*4882a593Smuzhiyun { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
50*4882a593Smuzhiyun { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
51*4882a593Smuzhiyun { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
52*4882a593Smuzhiyun { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
53*4882a593Smuzhiyun { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
54*4882a593Smuzhiyun { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
55*4882a593Smuzhiyun { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
56*4882a593Smuzhiyun { 0x0037, 0x0000 }, /* R55 - Additional Control */
57*4882a593Smuzhiyun { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
58*4882a593Smuzhiyun { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */
59*4882a593Smuzhiyun { 0x003B, 0x000D }, /* R59 - LDO 1 */
60*4882a593Smuzhiyun { 0x003C, 0x0003 }, /* R60 - LDO 2 */
61*4882a593Smuzhiyun { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */
62*4882a593Smuzhiyun { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */
63*4882a593Smuzhiyun { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
64*4882a593Smuzhiyun { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */
65*4882a593Smuzhiyun { 0x0051, 0x0004 }, /* R81 - Class W (1) */
66*4882a593Smuzhiyun { 0x0055, 0x054A }, /* R85 - DC Servo (2) */
67*4882a593Smuzhiyun { 0x0059, 0x0000 }, /* R89 - DC Servo (4) */
68*4882a593Smuzhiyun { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
69*4882a593Smuzhiyun { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */
70*4882a593Smuzhiyun { 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */
71*4882a593Smuzhiyun { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */
72*4882a593Smuzhiyun { 0x0101, 0x8004 }, /* R257 - Control Interface */
73*4882a593Smuzhiyun { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
74*4882a593Smuzhiyun { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
75*4882a593Smuzhiyun { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
76*4882a593Smuzhiyun { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
77*4882a593Smuzhiyun { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
78*4882a593Smuzhiyun { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
79*4882a593Smuzhiyun { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
80*4882a593Smuzhiyun { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
81*4882a593Smuzhiyun { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
82*4882a593Smuzhiyun { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
83*4882a593Smuzhiyun { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
84*4882a593Smuzhiyun { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
85*4882a593Smuzhiyun { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
86*4882a593Smuzhiyun { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */
87*4882a593Smuzhiyun { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */
88*4882a593Smuzhiyun { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */
89*4882a593Smuzhiyun { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */
90*4882a593Smuzhiyun { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */
91*4882a593Smuzhiyun { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
92*4882a593Smuzhiyun { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */
93*4882a593Smuzhiyun { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */
94*4882a593Smuzhiyun { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */
95*4882a593Smuzhiyun { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
96*4882a593Smuzhiyun { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
97*4882a593Smuzhiyun { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
98*4882a593Smuzhiyun { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
99*4882a593Smuzhiyun { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
100*4882a593Smuzhiyun { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
101*4882a593Smuzhiyun { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
102*4882a593Smuzhiyun { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
103*4882a593Smuzhiyun { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */
104*4882a593Smuzhiyun { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
105*4882a593Smuzhiyun { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
106*4882a593Smuzhiyun { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
107*4882a593Smuzhiyun { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
108*4882a593Smuzhiyun { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
109*4882a593Smuzhiyun { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
110*4882a593Smuzhiyun { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
111*4882a593Smuzhiyun { 0x0318, 0x0003 }, /* R792 - AIF2TX Control */
112*4882a593Smuzhiyun { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */
113*4882a593Smuzhiyun { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */
114*4882a593Smuzhiyun { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */
115*4882a593Smuzhiyun { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */
116*4882a593Smuzhiyun { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
117*4882a593Smuzhiyun { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
118*4882a593Smuzhiyun { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
119*4882a593Smuzhiyun { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
120*4882a593Smuzhiyun { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
121*4882a593Smuzhiyun { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
122*4882a593Smuzhiyun { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
123*4882a593Smuzhiyun { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
124*4882a593Smuzhiyun { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
125*4882a593Smuzhiyun { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
126*4882a593Smuzhiyun { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */
127*4882a593Smuzhiyun { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */
128*4882a593Smuzhiyun { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
129*4882a593Smuzhiyun { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
130*4882a593Smuzhiyun { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
131*4882a593Smuzhiyun { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
132*4882a593Smuzhiyun { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
133*4882a593Smuzhiyun { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
134*4882a593Smuzhiyun { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
135*4882a593Smuzhiyun { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
136*4882a593Smuzhiyun { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
137*4882a593Smuzhiyun { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
138*4882a593Smuzhiyun { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
139*4882a593Smuzhiyun { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
140*4882a593Smuzhiyun { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
141*4882a593Smuzhiyun { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
142*4882a593Smuzhiyun { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
143*4882a593Smuzhiyun { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
144*4882a593Smuzhiyun { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
145*4882a593Smuzhiyun { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
146*4882a593Smuzhiyun { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
147*4882a593Smuzhiyun { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
148*4882a593Smuzhiyun { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
149*4882a593Smuzhiyun { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
150*4882a593Smuzhiyun { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
151*4882a593Smuzhiyun { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
152*4882a593Smuzhiyun { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
153*4882a593Smuzhiyun { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
154*4882a593Smuzhiyun { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
155*4882a593Smuzhiyun { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
156*4882a593Smuzhiyun { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
157*4882a593Smuzhiyun { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
158*4882a593Smuzhiyun { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */
159*4882a593Smuzhiyun { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
160*4882a593Smuzhiyun { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
161*4882a593Smuzhiyun { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
162*4882a593Smuzhiyun { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
163*4882a593Smuzhiyun { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
164*4882a593Smuzhiyun { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
165*4882a593Smuzhiyun { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
166*4882a593Smuzhiyun { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
167*4882a593Smuzhiyun { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
168*4882a593Smuzhiyun { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
169*4882a593Smuzhiyun { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
170*4882a593Smuzhiyun { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
171*4882a593Smuzhiyun { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
172*4882a593Smuzhiyun { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
173*4882a593Smuzhiyun { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
174*4882a593Smuzhiyun { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
175*4882a593Smuzhiyun { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
176*4882a593Smuzhiyun { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
177*4882a593Smuzhiyun { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
178*4882a593Smuzhiyun { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
179*4882a593Smuzhiyun { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2 EQ Band 1 C */
180*4882a593Smuzhiyun { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
181*4882a593Smuzhiyun { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
182*4882a593Smuzhiyun { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
183*4882a593Smuzhiyun { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
184*4882a593Smuzhiyun { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
185*4882a593Smuzhiyun { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
186*4882a593Smuzhiyun { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
187*4882a593Smuzhiyun { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */
188*4882a593Smuzhiyun { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
189*4882a593Smuzhiyun { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
190*4882a593Smuzhiyun { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
191*4882a593Smuzhiyun { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
192*4882a593Smuzhiyun { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
193*4882a593Smuzhiyun { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
194*4882a593Smuzhiyun { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
195*4882a593Smuzhiyun { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
196*4882a593Smuzhiyun { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
197*4882a593Smuzhiyun { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
198*4882a593Smuzhiyun { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
199*4882a593Smuzhiyun { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
200*4882a593Smuzhiyun { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
201*4882a593Smuzhiyun { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
202*4882a593Smuzhiyun { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
203*4882a593Smuzhiyun { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
204*4882a593Smuzhiyun { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
205*4882a593Smuzhiyun { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
206*4882a593Smuzhiyun { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
207*4882a593Smuzhiyun { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
208*4882a593Smuzhiyun { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
209*4882a593Smuzhiyun { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
210*4882a593Smuzhiyun { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
211*4882a593Smuzhiyun { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
212*4882a593Smuzhiyun { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
213*4882a593Smuzhiyun { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */
214*4882a593Smuzhiyun { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
215*4882a593Smuzhiyun { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
216*4882a593Smuzhiyun { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
217*4882a593Smuzhiyun { 0x0603, 0x0000 }, /* R1539 - AIF2ADC Mixer Volumes */
218*4882a593Smuzhiyun { 0x0604, 0x0000 }, /* R1540 - AIF2ADC Left Mixer Routing */
219*4882a593Smuzhiyun { 0x0605, 0x0000 }, /* R1541 - AIF2ADC Right Mixer Routing */
220*4882a593Smuzhiyun { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
221*4882a593Smuzhiyun { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
222*4882a593Smuzhiyun { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
223*4882a593Smuzhiyun { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right Mixer Routing */
224*4882a593Smuzhiyun { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
225*4882a593Smuzhiyun { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
226*4882a593Smuzhiyun { 0x0612, 0x02C0 }, /* R1554 - AIF2TX Left Volume */
227*4882a593Smuzhiyun { 0x0613, 0x02C0 }, /* R1555 - AIF2TX Right Volume */
228*4882a593Smuzhiyun { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
229*4882a593Smuzhiyun { 0x0620, 0x0002 }, /* R1568 - Oversampling */
230*4882a593Smuzhiyun { 0x0621, 0x0000 }, /* R1569 - Sidetone */
231*4882a593Smuzhiyun { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
232*4882a593Smuzhiyun { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */
233*4882a593Smuzhiyun { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */
234*4882a593Smuzhiyun { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */
235*4882a593Smuzhiyun { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */
236*4882a593Smuzhiyun { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
237*4882a593Smuzhiyun { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
238*4882a593Smuzhiyun { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
239*4882a593Smuzhiyun { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
240*4882a593Smuzhiyun { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
241*4882a593Smuzhiyun { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
242*4882a593Smuzhiyun { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */
243*4882a593Smuzhiyun { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
244*4882a593Smuzhiyun { 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */
245*4882a593Smuzhiyun { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
246*4882a593Smuzhiyun { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun static const struct reg_default wm8994_defaults[] = {
250*4882a593Smuzhiyun { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
251*4882a593Smuzhiyun { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
252*4882a593Smuzhiyun { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
253*4882a593Smuzhiyun { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
254*4882a593Smuzhiyun { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
255*4882a593Smuzhiyun { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
256*4882a593Smuzhiyun { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
257*4882a593Smuzhiyun { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
258*4882a593Smuzhiyun { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
259*4882a593Smuzhiyun { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
260*4882a593Smuzhiyun { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
261*4882a593Smuzhiyun { 0x001C, 0x006D }, /* R28 - Left Output Volume */
262*4882a593Smuzhiyun { 0x001D, 0x006D }, /* R29 - Right Output Volume */
263*4882a593Smuzhiyun { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
264*4882a593Smuzhiyun { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
265*4882a593Smuzhiyun { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
266*4882a593Smuzhiyun { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
267*4882a593Smuzhiyun { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
268*4882a593Smuzhiyun { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
269*4882a593Smuzhiyun { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
270*4882a593Smuzhiyun { 0x0025, 0x0140 }, /* R37 - ClassD */
271*4882a593Smuzhiyun { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
272*4882a593Smuzhiyun { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
273*4882a593Smuzhiyun { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
274*4882a593Smuzhiyun { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
275*4882a593Smuzhiyun { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
276*4882a593Smuzhiyun { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
277*4882a593Smuzhiyun { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
278*4882a593Smuzhiyun { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
279*4882a593Smuzhiyun { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
280*4882a593Smuzhiyun { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
281*4882a593Smuzhiyun { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
282*4882a593Smuzhiyun { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
283*4882a593Smuzhiyun { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
284*4882a593Smuzhiyun { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
285*4882a593Smuzhiyun { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
286*4882a593Smuzhiyun { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
287*4882a593Smuzhiyun { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
288*4882a593Smuzhiyun { 0x0037, 0x0000 }, /* R55 - Additional Control */
289*4882a593Smuzhiyun { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
290*4882a593Smuzhiyun { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */
291*4882a593Smuzhiyun { 0x003A, 0x0000 }, /* R58 - MICBIAS */
292*4882a593Smuzhiyun { 0x003B, 0x000D }, /* R59 - LDO 1 */
293*4882a593Smuzhiyun { 0x003C, 0x0003 }, /* R60 - LDO 2 */
294*4882a593Smuzhiyun { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
295*4882a593Smuzhiyun { 0x0051, 0x0004 }, /* R81 - Class W (1) */
296*4882a593Smuzhiyun { 0x0055, 0x054A }, /* R85 - DC Servo (2) */
297*4882a593Smuzhiyun { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */
298*4882a593Smuzhiyun { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
299*4882a593Smuzhiyun { 0x0101, 0x8004 }, /* R257 - Control Interface */
300*4882a593Smuzhiyun { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
301*4882a593Smuzhiyun { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
302*4882a593Smuzhiyun { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
303*4882a593Smuzhiyun { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
304*4882a593Smuzhiyun { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
305*4882a593Smuzhiyun { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
306*4882a593Smuzhiyun { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
307*4882a593Smuzhiyun { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
308*4882a593Smuzhiyun { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
309*4882a593Smuzhiyun { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
310*4882a593Smuzhiyun { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
311*4882a593Smuzhiyun { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
312*4882a593Smuzhiyun { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
313*4882a593Smuzhiyun { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
314*4882a593Smuzhiyun { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
315*4882a593Smuzhiyun { 0x0240, 0x0000 }, /* R576 - FLL2 Control (1) */
316*4882a593Smuzhiyun { 0x0241, 0x0000 }, /* R577 - FLL2 Control (2) */
317*4882a593Smuzhiyun { 0x0242, 0x0000 }, /* R578 - FLL2 Control (3) */
318*4882a593Smuzhiyun { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
319*4882a593Smuzhiyun { 0x0244, 0x0C80 }, /* R580 - FLL2 Control (5) */
320*4882a593Smuzhiyun { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
321*4882a593Smuzhiyun { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
322*4882a593Smuzhiyun { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
323*4882a593Smuzhiyun { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
324*4882a593Smuzhiyun { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
325*4882a593Smuzhiyun { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
326*4882a593Smuzhiyun { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
327*4882a593Smuzhiyun { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
328*4882a593Smuzhiyun { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */
329*4882a593Smuzhiyun { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
330*4882a593Smuzhiyun { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
331*4882a593Smuzhiyun { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
332*4882a593Smuzhiyun { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
333*4882a593Smuzhiyun { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
334*4882a593Smuzhiyun { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
335*4882a593Smuzhiyun { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
336*4882a593Smuzhiyun { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
337*4882a593Smuzhiyun { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
338*4882a593Smuzhiyun { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
339*4882a593Smuzhiyun { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
340*4882a593Smuzhiyun { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */
341*4882a593Smuzhiyun { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */
342*4882a593Smuzhiyun { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */
343*4882a593Smuzhiyun { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */
344*4882a593Smuzhiyun { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
345*4882a593Smuzhiyun { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
346*4882a593Smuzhiyun { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
347*4882a593Smuzhiyun { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
348*4882a593Smuzhiyun { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
349*4882a593Smuzhiyun { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
350*4882a593Smuzhiyun { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
351*4882a593Smuzhiyun { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
352*4882a593Smuzhiyun { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
353*4882a593Smuzhiyun { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
354*4882a593Smuzhiyun { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
355*4882a593Smuzhiyun { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
356*4882a593Smuzhiyun { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
357*4882a593Smuzhiyun { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
358*4882a593Smuzhiyun { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
359*4882a593Smuzhiyun { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
360*4882a593Smuzhiyun { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
361*4882a593Smuzhiyun { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
362*4882a593Smuzhiyun { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
363*4882a593Smuzhiyun { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
364*4882a593Smuzhiyun { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
365*4882a593Smuzhiyun { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
366*4882a593Smuzhiyun { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
367*4882a593Smuzhiyun { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
368*4882a593Smuzhiyun { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
369*4882a593Smuzhiyun { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
370*4882a593Smuzhiyun { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
371*4882a593Smuzhiyun { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
372*4882a593Smuzhiyun { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
373*4882a593Smuzhiyun { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
374*4882a593Smuzhiyun { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
375*4882a593Smuzhiyun { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
376*4882a593Smuzhiyun { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
377*4882a593Smuzhiyun { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
378*4882a593Smuzhiyun { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
379*4882a593Smuzhiyun { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
380*4882a593Smuzhiyun { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
381*4882a593Smuzhiyun { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
382*4882a593Smuzhiyun { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
383*4882a593Smuzhiyun { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
384*4882a593Smuzhiyun { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
385*4882a593Smuzhiyun { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
386*4882a593Smuzhiyun { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
387*4882a593Smuzhiyun { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
388*4882a593Smuzhiyun { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
389*4882a593Smuzhiyun { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
390*4882a593Smuzhiyun { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
391*4882a593Smuzhiyun { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
392*4882a593Smuzhiyun { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
393*4882a593Smuzhiyun { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
394*4882a593Smuzhiyun { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
395*4882a593Smuzhiyun { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
396*4882a593Smuzhiyun { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
397*4882a593Smuzhiyun { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
398*4882a593Smuzhiyun { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
399*4882a593Smuzhiyun { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
400*4882a593Smuzhiyun { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
401*4882a593Smuzhiyun { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
402*4882a593Smuzhiyun { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
403*4882a593Smuzhiyun { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
404*4882a593Smuzhiyun { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
405*4882a593Smuzhiyun { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
406*4882a593Smuzhiyun { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
407*4882a593Smuzhiyun { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
408*4882a593Smuzhiyun { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
409*4882a593Smuzhiyun { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
410*4882a593Smuzhiyun { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
411*4882a593Smuzhiyun { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
412*4882a593Smuzhiyun { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
413*4882a593Smuzhiyun { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
414*4882a593Smuzhiyun { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
415*4882a593Smuzhiyun { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
416*4882a593Smuzhiyun { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
417*4882a593Smuzhiyun { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
418*4882a593Smuzhiyun { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
419*4882a593Smuzhiyun { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
420*4882a593Smuzhiyun { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
421*4882a593Smuzhiyun { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
422*4882a593Smuzhiyun { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
423*4882a593Smuzhiyun { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
424*4882a593Smuzhiyun { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
425*4882a593Smuzhiyun { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
426*4882a593Smuzhiyun { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
427*4882a593Smuzhiyun { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
428*4882a593Smuzhiyun { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
429*4882a593Smuzhiyun { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
430*4882a593Smuzhiyun { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
431*4882a593Smuzhiyun { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
432*4882a593Smuzhiyun { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
433*4882a593Smuzhiyun { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
434*4882a593Smuzhiyun { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
435*4882a593Smuzhiyun { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
436*4882a593Smuzhiyun { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
437*4882a593Smuzhiyun { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
438*4882a593Smuzhiyun { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
439*4882a593Smuzhiyun { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
440*4882a593Smuzhiyun { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
441*4882a593Smuzhiyun { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
442*4882a593Smuzhiyun { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
443*4882a593Smuzhiyun { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
444*4882a593Smuzhiyun { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */
445*4882a593Smuzhiyun { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */
446*4882a593Smuzhiyun { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
447*4882a593Smuzhiyun { 0x0620, 0x0002 }, /* R1568 - Oversampling */
448*4882a593Smuzhiyun { 0x0621, 0x0000 }, /* R1569 - Sidetone */
449*4882a593Smuzhiyun { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
450*4882a593Smuzhiyun { 0x0701, 0xA101 }, /* R1793 - GPIO 2 */
451*4882a593Smuzhiyun { 0x0702, 0xA101 }, /* R1794 - GPIO 3 */
452*4882a593Smuzhiyun { 0x0703, 0xA101 }, /* R1795 - GPIO 4 */
453*4882a593Smuzhiyun { 0x0704, 0xA101 }, /* R1796 - GPIO 5 */
454*4882a593Smuzhiyun { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */
455*4882a593Smuzhiyun { 0x0706, 0xA101 }, /* R1798 - GPIO 7 */
456*4882a593Smuzhiyun { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
457*4882a593Smuzhiyun { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
458*4882a593Smuzhiyun { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
459*4882a593Smuzhiyun { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
460*4882a593Smuzhiyun { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
461*4882a593Smuzhiyun { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
462*4882a593Smuzhiyun { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
463*4882a593Smuzhiyun { 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */
464*4882a593Smuzhiyun { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
465*4882a593Smuzhiyun { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
466*4882a593Smuzhiyun };
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun static const struct reg_default wm8958_defaults[] = {
469*4882a593Smuzhiyun { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
470*4882a593Smuzhiyun { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
471*4882a593Smuzhiyun { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
472*4882a593Smuzhiyun { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
473*4882a593Smuzhiyun { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
474*4882a593Smuzhiyun { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
475*4882a593Smuzhiyun { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
476*4882a593Smuzhiyun { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
477*4882a593Smuzhiyun { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
478*4882a593Smuzhiyun { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
479*4882a593Smuzhiyun { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
480*4882a593Smuzhiyun { 0x001C, 0x006D }, /* R28 - Left Output Volume */
481*4882a593Smuzhiyun { 0x001D, 0x006D }, /* R29 - Right Output Volume */
482*4882a593Smuzhiyun { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
483*4882a593Smuzhiyun { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
484*4882a593Smuzhiyun { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
485*4882a593Smuzhiyun { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
486*4882a593Smuzhiyun { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
487*4882a593Smuzhiyun { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
488*4882a593Smuzhiyun { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
489*4882a593Smuzhiyun { 0x0025, 0x0140 }, /* R37 - ClassD */
490*4882a593Smuzhiyun { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
491*4882a593Smuzhiyun { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
492*4882a593Smuzhiyun { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
493*4882a593Smuzhiyun { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
494*4882a593Smuzhiyun { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
495*4882a593Smuzhiyun { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
496*4882a593Smuzhiyun { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
497*4882a593Smuzhiyun { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
498*4882a593Smuzhiyun { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
499*4882a593Smuzhiyun { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
500*4882a593Smuzhiyun { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
501*4882a593Smuzhiyun { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
502*4882a593Smuzhiyun { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
503*4882a593Smuzhiyun { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
504*4882a593Smuzhiyun { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
505*4882a593Smuzhiyun { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
506*4882a593Smuzhiyun { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
507*4882a593Smuzhiyun { 0x0037, 0x0000 }, /* R55 - Additional Control */
508*4882a593Smuzhiyun { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
509*4882a593Smuzhiyun { 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */
510*4882a593Smuzhiyun { 0x003B, 0x000D }, /* R59 - LDO 1 */
511*4882a593Smuzhiyun { 0x003C, 0x0005 }, /* R60 - LDO 2 */
512*4882a593Smuzhiyun { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */
513*4882a593Smuzhiyun { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */
514*4882a593Smuzhiyun { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
515*4882a593Smuzhiyun { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */
516*4882a593Smuzhiyun { 0x0051, 0x0004 }, /* R81 - Class W (1) */
517*4882a593Smuzhiyun { 0x0055, 0x054A }, /* R85 - DC Servo (2) */
518*4882a593Smuzhiyun { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */
519*4882a593Smuzhiyun { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
520*4882a593Smuzhiyun { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */
521*4882a593Smuzhiyun { 0x00D0, 0x5600 }, /* R208 - Mic Detect 1 */
522*4882a593Smuzhiyun { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */
523*4882a593Smuzhiyun { 0x0101, 0x8004 }, /* R257 - Control Interface */
524*4882a593Smuzhiyun { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
525*4882a593Smuzhiyun { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
526*4882a593Smuzhiyun { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
527*4882a593Smuzhiyun { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
528*4882a593Smuzhiyun { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
529*4882a593Smuzhiyun { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
530*4882a593Smuzhiyun { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
531*4882a593Smuzhiyun { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
532*4882a593Smuzhiyun { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
533*4882a593Smuzhiyun { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
534*4882a593Smuzhiyun { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
535*4882a593Smuzhiyun { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
536*4882a593Smuzhiyun { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
537*4882a593Smuzhiyun { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
538*4882a593Smuzhiyun { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
539*4882a593Smuzhiyun { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */
540*4882a593Smuzhiyun { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */
541*4882a593Smuzhiyun { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */
542*4882a593Smuzhiyun { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */
543*4882a593Smuzhiyun { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */
544*4882a593Smuzhiyun { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
545*4882a593Smuzhiyun { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */
546*4882a593Smuzhiyun { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */
547*4882a593Smuzhiyun { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */
548*4882a593Smuzhiyun { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
549*4882a593Smuzhiyun { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
550*4882a593Smuzhiyun { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
551*4882a593Smuzhiyun { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
552*4882a593Smuzhiyun { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
553*4882a593Smuzhiyun { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
554*4882a593Smuzhiyun { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
555*4882a593Smuzhiyun { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
556*4882a593Smuzhiyun { 0x0310, 0x4053 }, /* R784 - AIF2 Control (1) */
557*4882a593Smuzhiyun { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
558*4882a593Smuzhiyun { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
559*4882a593Smuzhiyun { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
560*4882a593Smuzhiyun { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
561*4882a593Smuzhiyun { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
562*4882a593Smuzhiyun { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
563*4882a593Smuzhiyun { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
564*4882a593Smuzhiyun { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */
565*4882a593Smuzhiyun { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */
566*4882a593Smuzhiyun { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */
567*4882a593Smuzhiyun { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */
568*4882a593Smuzhiyun { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
569*4882a593Smuzhiyun { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
570*4882a593Smuzhiyun { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
571*4882a593Smuzhiyun { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
572*4882a593Smuzhiyun { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */
573*4882a593Smuzhiyun { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */
574*4882a593Smuzhiyun { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */
575*4882a593Smuzhiyun { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */
576*4882a593Smuzhiyun { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
577*4882a593Smuzhiyun { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
578*4882a593Smuzhiyun { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
579*4882a593Smuzhiyun { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
580*4882a593Smuzhiyun { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
581*4882a593Smuzhiyun { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
582*4882a593Smuzhiyun { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */
583*4882a593Smuzhiyun { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */
584*4882a593Smuzhiyun { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
585*4882a593Smuzhiyun { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
586*4882a593Smuzhiyun { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
587*4882a593Smuzhiyun { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
588*4882a593Smuzhiyun { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
589*4882a593Smuzhiyun { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
590*4882a593Smuzhiyun { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
591*4882a593Smuzhiyun { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
592*4882a593Smuzhiyun { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
593*4882a593Smuzhiyun { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
594*4882a593Smuzhiyun { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
595*4882a593Smuzhiyun { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
596*4882a593Smuzhiyun { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
597*4882a593Smuzhiyun { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
598*4882a593Smuzhiyun { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
599*4882a593Smuzhiyun { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
600*4882a593Smuzhiyun { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
601*4882a593Smuzhiyun { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
602*4882a593Smuzhiyun { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
603*4882a593Smuzhiyun { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
604*4882a593Smuzhiyun { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
605*4882a593Smuzhiyun { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
606*4882a593Smuzhiyun { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
607*4882a593Smuzhiyun { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
608*4882a593Smuzhiyun { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
609*4882a593Smuzhiyun { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
610*4882a593Smuzhiyun { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
611*4882a593Smuzhiyun { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
612*4882a593Smuzhiyun { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
613*4882a593Smuzhiyun { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
614*4882a593Smuzhiyun { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */
615*4882a593Smuzhiyun { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
616*4882a593Smuzhiyun { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
617*4882a593Smuzhiyun { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
618*4882a593Smuzhiyun { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
619*4882a593Smuzhiyun { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
620*4882a593Smuzhiyun { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
621*4882a593Smuzhiyun { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
622*4882a593Smuzhiyun { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
623*4882a593Smuzhiyun { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
624*4882a593Smuzhiyun { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
625*4882a593Smuzhiyun { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
626*4882a593Smuzhiyun { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
627*4882a593Smuzhiyun { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
628*4882a593Smuzhiyun { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
629*4882a593Smuzhiyun { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
630*4882a593Smuzhiyun { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
631*4882a593Smuzhiyun { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
632*4882a593Smuzhiyun { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
633*4882a593Smuzhiyun { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
634*4882a593Smuzhiyun { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
635*4882a593Smuzhiyun { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2EQ Band 1 C */
636*4882a593Smuzhiyun { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
637*4882a593Smuzhiyun { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
638*4882a593Smuzhiyun { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
639*4882a593Smuzhiyun { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
640*4882a593Smuzhiyun { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
641*4882a593Smuzhiyun { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
642*4882a593Smuzhiyun { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
643*4882a593Smuzhiyun { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */
644*4882a593Smuzhiyun { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
645*4882a593Smuzhiyun { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
646*4882a593Smuzhiyun { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
647*4882a593Smuzhiyun { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
648*4882a593Smuzhiyun { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
649*4882a593Smuzhiyun { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
650*4882a593Smuzhiyun { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
651*4882a593Smuzhiyun { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
652*4882a593Smuzhiyun { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
653*4882a593Smuzhiyun { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
654*4882a593Smuzhiyun { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
655*4882a593Smuzhiyun { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
656*4882a593Smuzhiyun { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
657*4882a593Smuzhiyun { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
658*4882a593Smuzhiyun { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
659*4882a593Smuzhiyun { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
660*4882a593Smuzhiyun { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
661*4882a593Smuzhiyun { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
662*4882a593Smuzhiyun { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
663*4882a593Smuzhiyun { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
664*4882a593Smuzhiyun { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
665*4882a593Smuzhiyun { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
666*4882a593Smuzhiyun { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
667*4882a593Smuzhiyun { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
668*4882a593Smuzhiyun { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
669*4882a593Smuzhiyun { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */
670*4882a593Smuzhiyun { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
671*4882a593Smuzhiyun { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
672*4882a593Smuzhiyun { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
673*4882a593Smuzhiyun { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
674*4882a593Smuzhiyun { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
675*4882a593Smuzhiyun { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
676*4882a593Smuzhiyun { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
677*4882a593Smuzhiyun { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
678*4882a593Smuzhiyun { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
679*4882a593Smuzhiyun { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
680*4882a593Smuzhiyun { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
681*4882a593Smuzhiyun { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
682*4882a593Smuzhiyun { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */
683*4882a593Smuzhiyun { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */
684*4882a593Smuzhiyun { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
685*4882a593Smuzhiyun { 0x0620, 0x0002 }, /* R1568 - Oversampling */
686*4882a593Smuzhiyun { 0x0621, 0x0000 }, /* R1569 - Sidetone */
687*4882a593Smuzhiyun { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
688*4882a593Smuzhiyun { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */
689*4882a593Smuzhiyun { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */
690*4882a593Smuzhiyun { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */
691*4882a593Smuzhiyun { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */
692*4882a593Smuzhiyun { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */
693*4882a593Smuzhiyun { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
694*4882a593Smuzhiyun { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
695*4882a593Smuzhiyun { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
696*4882a593Smuzhiyun { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
697*4882a593Smuzhiyun { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
698*4882a593Smuzhiyun { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
699*4882a593Smuzhiyun { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
700*4882a593Smuzhiyun { 0x0739, 0xFFEF }, /* R1849 - Interrupt Status 2 Mask */
701*4882a593Smuzhiyun { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
702*4882a593Smuzhiyun { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
703*4882a593Smuzhiyun { 0x0900, 0x1C00 }, /* R2304 - DSP2_Program */
704*4882a593Smuzhiyun { 0x0901, 0x0000 }, /* R2305 - DSP2_Config */
705*4882a593Smuzhiyun { 0x0A0D, 0x0000 }, /* R2573 - DSP2_ExecControl */
706*4882a593Smuzhiyun { 0x2400, 0x003F }, /* R9216 - MBC Band 1 K (1) */
707*4882a593Smuzhiyun { 0x2401, 0x8BD8 }, /* R9217 - MBC Band 1 K (2) */
708*4882a593Smuzhiyun { 0x2402, 0x0032 }, /* R9218 - MBC Band 1 N1 (1) */
709*4882a593Smuzhiyun { 0x2403, 0xF52D }, /* R9219 - MBC Band 1 N1 (2) */
710*4882a593Smuzhiyun { 0x2404, 0x0065 }, /* R9220 - MBC Band 1 N2 (1) */
711*4882a593Smuzhiyun { 0x2405, 0xAC8C }, /* R9221 - MBC Band 1 N2 (2) */
712*4882a593Smuzhiyun { 0x2406, 0x006B }, /* R9222 - MBC Band 1 N3 (1) */
713*4882a593Smuzhiyun { 0x2407, 0xE087 }, /* R9223 - MBC Band 1 N3 (2) */
714*4882a593Smuzhiyun { 0x2408, 0x0072 }, /* R9224 - MBC Band 1 N4 (1) */
715*4882a593Smuzhiyun { 0x2409, 0x1483 }, /* R9225 - MBC Band 1 N4 (2) */
716*4882a593Smuzhiyun { 0x240A, 0x0072 }, /* R9226 - MBC Band 1 N5 (1) */
717*4882a593Smuzhiyun { 0x240B, 0x1483 }, /* R9227 - MBC Band 1 N5 (2) */
718*4882a593Smuzhiyun { 0x240C, 0x0043 }, /* R9228 - MBC Band 1 X1 (1) */
719*4882a593Smuzhiyun { 0x240D, 0x3525 }, /* R9229 - MBC Band 1 X1 (2) */
720*4882a593Smuzhiyun { 0x240E, 0x0006 }, /* R9230 - MBC Band 1 X2 (1) */
721*4882a593Smuzhiyun { 0x240F, 0x6A4A }, /* R9231 - MBC Band 1 X2 (2) */
722*4882a593Smuzhiyun { 0x2410, 0x0043 }, /* R9232 - MBC Band 1 X3 (1) */
723*4882a593Smuzhiyun { 0x2411, 0x6079 }, /* R9233 - MBC Band 1 X3 (2) */
724*4882a593Smuzhiyun { 0x2412, 0x000C }, /* R9234 - MBC Band 1 Attack (1) */
725*4882a593Smuzhiyun { 0x2413, 0xCCCD }, /* R9235 - MBC Band 1 Attack (2) */
726*4882a593Smuzhiyun { 0x2414, 0x0000 }, /* R9236 - MBC Band 1 Decay (1) */
727*4882a593Smuzhiyun { 0x2415, 0x0800 }, /* R9237 - MBC Band 1 Decay (2) */
728*4882a593Smuzhiyun { 0x2416, 0x003F }, /* R9238 - MBC Band 2 K (1) */
729*4882a593Smuzhiyun { 0x2417, 0x8BD8 }, /* R9239 - MBC Band 2 K (2) */
730*4882a593Smuzhiyun { 0x2418, 0x0032 }, /* R9240 - MBC Band 2 N1 (1) */
731*4882a593Smuzhiyun { 0x2419, 0xF52D }, /* R9241 - MBC Band 2 N1 (2) */
732*4882a593Smuzhiyun { 0x241A, 0x0065 }, /* R9242 - MBC Band 2 N2 (1) */
733*4882a593Smuzhiyun { 0x241B, 0xAC8C }, /* R9243 - MBC Band 2 N2 (2) */
734*4882a593Smuzhiyun { 0x241C, 0x006B }, /* R9244 - MBC Band 2 N3 (1) */
735*4882a593Smuzhiyun { 0x241D, 0xE087 }, /* R9245 - MBC Band 2 N3 (2) */
736*4882a593Smuzhiyun { 0x241E, 0x0072 }, /* R9246 - MBC Band 2 N4 (1) */
737*4882a593Smuzhiyun { 0x241F, 0x1483 }, /* R9247 - MBC Band 2 N4 (2) */
738*4882a593Smuzhiyun { 0x2420, 0x0072 }, /* R9248 - MBC Band 2 N5 (1) */
739*4882a593Smuzhiyun { 0x2421, 0x1483 }, /* R9249 - MBC Band 2 N5 (2) */
740*4882a593Smuzhiyun { 0x2422, 0x0043 }, /* R9250 - MBC Band 2 X1 (1) */
741*4882a593Smuzhiyun { 0x2423, 0x3525 }, /* R9251 - MBC Band 2 X1 (2) */
742*4882a593Smuzhiyun { 0x2424, 0x0006 }, /* R9252 - MBC Band 2 X2 (1) */
743*4882a593Smuzhiyun { 0x2425, 0x6A4A }, /* R9253 - MBC Band 2 X2 (2) */
744*4882a593Smuzhiyun { 0x2426, 0x0043 }, /* R9254 - MBC Band 2 X3 (1) */
745*4882a593Smuzhiyun { 0x2427, 0x6079 }, /* R9255 - MBC Band 2 X3 (2) */
746*4882a593Smuzhiyun { 0x2428, 0x000C }, /* R9256 - MBC Band 2 Attack (1) */
747*4882a593Smuzhiyun { 0x2429, 0xCCCD }, /* R9257 - MBC Band 2 Attack (2) */
748*4882a593Smuzhiyun { 0x242A, 0x0000 }, /* R9258 - MBC Band 2 Decay (1) */
749*4882a593Smuzhiyun { 0x242B, 0x0800 }, /* R9259 - MBC Band 2 Decay (2) */
750*4882a593Smuzhiyun { 0x242C, 0x005A }, /* R9260 - MBC_B2_PG2 (1) */
751*4882a593Smuzhiyun { 0x242D, 0x7EFA }, /* R9261 - MBC_B2_PG2 (2) */
752*4882a593Smuzhiyun { 0x242E, 0x005A }, /* R9262 - MBC_B1_PG2 (1) */
753*4882a593Smuzhiyun { 0x242F, 0x7EFA }, /* R9263 - MBC_B1_PG2 (2) */
754*4882a593Smuzhiyun { 0x2600, 0x00A7 }, /* R9728 - MBC Crossover (1) */
755*4882a593Smuzhiyun { 0x2601, 0x0D1C }, /* R9729 - MBC Crossover (2) */
756*4882a593Smuzhiyun { 0x2602, 0x0083 }, /* R9730 - MBC HPF (1) */
757*4882a593Smuzhiyun { 0x2603, 0x98AD }, /* R9731 - MBC HPF (2) */
758*4882a593Smuzhiyun { 0x2606, 0x0008 }, /* R9734 - MBC LPF (1) */
759*4882a593Smuzhiyun { 0x2607, 0xE7A2 }, /* R9735 - MBC LPF (2) */
760*4882a593Smuzhiyun { 0x260A, 0x0055 }, /* R9738 - MBC RMS Limit (1) */
761*4882a593Smuzhiyun { 0x260B, 0x8C4B }, /* R9739 - MBC RMS Limit (2) */
762*4882a593Smuzhiyun };
763*4882a593Smuzhiyun
wm1811_readable_register(struct device * dev,unsigned int reg)764*4882a593Smuzhiyun static bool wm1811_readable_register(struct device *dev, unsigned int reg)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun switch (reg) {
767*4882a593Smuzhiyun case WM8994_SOFTWARE_RESET:
768*4882a593Smuzhiyun case WM8994_POWER_MANAGEMENT_1:
769*4882a593Smuzhiyun case WM8994_POWER_MANAGEMENT_2:
770*4882a593Smuzhiyun case WM8994_POWER_MANAGEMENT_3:
771*4882a593Smuzhiyun case WM8994_POWER_MANAGEMENT_4:
772*4882a593Smuzhiyun case WM8994_POWER_MANAGEMENT_5:
773*4882a593Smuzhiyun case WM8994_POWER_MANAGEMENT_6:
774*4882a593Smuzhiyun case WM8994_INPUT_MIXER_1:
775*4882a593Smuzhiyun case WM8994_LEFT_LINE_INPUT_1_2_VOLUME:
776*4882a593Smuzhiyun case WM8994_LEFT_LINE_INPUT_3_4_VOLUME:
777*4882a593Smuzhiyun case WM8994_RIGHT_LINE_INPUT_1_2_VOLUME:
778*4882a593Smuzhiyun case WM8994_RIGHT_LINE_INPUT_3_4_VOLUME:
779*4882a593Smuzhiyun case WM8994_LEFT_OUTPUT_VOLUME:
780*4882a593Smuzhiyun case WM8994_RIGHT_OUTPUT_VOLUME:
781*4882a593Smuzhiyun case WM8994_LINE_OUTPUTS_VOLUME:
782*4882a593Smuzhiyun case WM8994_HPOUT2_VOLUME:
783*4882a593Smuzhiyun case WM8994_LEFT_OPGA_VOLUME:
784*4882a593Smuzhiyun case WM8994_RIGHT_OPGA_VOLUME:
785*4882a593Smuzhiyun case WM8994_SPKMIXL_ATTENUATION:
786*4882a593Smuzhiyun case WM8994_SPKMIXR_ATTENUATION:
787*4882a593Smuzhiyun case WM8994_SPKOUT_MIXERS:
788*4882a593Smuzhiyun case WM8994_CLASSD:
789*4882a593Smuzhiyun case WM8994_SPEAKER_VOLUME_LEFT:
790*4882a593Smuzhiyun case WM8994_SPEAKER_VOLUME_RIGHT:
791*4882a593Smuzhiyun case WM8994_INPUT_MIXER_2:
792*4882a593Smuzhiyun case WM8994_INPUT_MIXER_3:
793*4882a593Smuzhiyun case WM8994_INPUT_MIXER_4:
794*4882a593Smuzhiyun case WM8994_INPUT_MIXER_5:
795*4882a593Smuzhiyun case WM8994_INPUT_MIXER_6:
796*4882a593Smuzhiyun case WM8994_OUTPUT_MIXER_1:
797*4882a593Smuzhiyun case WM8994_OUTPUT_MIXER_2:
798*4882a593Smuzhiyun case WM8994_OUTPUT_MIXER_3:
799*4882a593Smuzhiyun case WM8994_OUTPUT_MIXER_4:
800*4882a593Smuzhiyun case WM8994_OUTPUT_MIXER_5:
801*4882a593Smuzhiyun case WM8994_OUTPUT_MIXER_6:
802*4882a593Smuzhiyun case WM8994_HPOUT2_MIXER:
803*4882a593Smuzhiyun case WM8994_LINE_MIXER_1:
804*4882a593Smuzhiyun case WM8994_LINE_MIXER_2:
805*4882a593Smuzhiyun case WM8994_SPEAKER_MIXER:
806*4882a593Smuzhiyun case WM8994_ADDITIONAL_CONTROL:
807*4882a593Smuzhiyun case WM8994_ANTIPOP_1:
808*4882a593Smuzhiyun case WM8994_ANTIPOP_2:
809*4882a593Smuzhiyun case WM8994_LDO_1:
810*4882a593Smuzhiyun case WM8994_LDO_2:
811*4882a593Smuzhiyun case WM8958_MICBIAS1:
812*4882a593Smuzhiyun case WM8958_MICBIAS2:
813*4882a593Smuzhiyun case WM8994_CHARGE_PUMP_1:
814*4882a593Smuzhiyun case WM8958_CHARGE_PUMP_2:
815*4882a593Smuzhiyun case WM8994_CLASS_W_1:
816*4882a593Smuzhiyun case WM8994_DC_SERVO_1:
817*4882a593Smuzhiyun case WM8994_DC_SERVO_2:
818*4882a593Smuzhiyun case WM8994_DC_SERVO_READBACK:
819*4882a593Smuzhiyun case WM8994_DC_SERVO_4:
820*4882a593Smuzhiyun case WM8994_DC_SERVO_4E:
821*4882a593Smuzhiyun case WM8994_ANALOGUE_HP_1:
822*4882a593Smuzhiyun case WM8958_MIC_DETECT_1:
823*4882a593Smuzhiyun case WM8958_MIC_DETECT_2:
824*4882a593Smuzhiyun case WM8958_MIC_DETECT_3:
825*4882a593Smuzhiyun case WM8994_CHIP_REVISION:
826*4882a593Smuzhiyun case WM8994_CONTROL_INTERFACE:
827*4882a593Smuzhiyun case WM8994_AIF1_CLOCKING_1:
828*4882a593Smuzhiyun case WM8994_AIF1_CLOCKING_2:
829*4882a593Smuzhiyun case WM8994_AIF2_CLOCKING_1:
830*4882a593Smuzhiyun case WM8994_AIF2_CLOCKING_2:
831*4882a593Smuzhiyun case WM8994_CLOCKING_1:
832*4882a593Smuzhiyun case WM8994_CLOCKING_2:
833*4882a593Smuzhiyun case WM8994_AIF1_RATE:
834*4882a593Smuzhiyun case WM8994_AIF2_RATE:
835*4882a593Smuzhiyun case WM8994_RATE_STATUS:
836*4882a593Smuzhiyun case WM8994_FLL1_CONTROL_1:
837*4882a593Smuzhiyun case WM8994_FLL1_CONTROL_2:
838*4882a593Smuzhiyun case WM8994_FLL1_CONTROL_3:
839*4882a593Smuzhiyun case WM8994_FLL1_CONTROL_4:
840*4882a593Smuzhiyun case WM8994_FLL1_CONTROL_5:
841*4882a593Smuzhiyun case WM8958_FLL1_EFS_1:
842*4882a593Smuzhiyun case WM8958_FLL1_EFS_2:
843*4882a593Smuzhiyun case WM8994_FLL2_CONTROL_1:
844*4882a593Smuzhiyun case WM8994_FLL2_CONTROL_2:
845*4882a593Smuzhiyun case WM8994_FLL2_CONTROL_3:
846*4882a593Smuzhiyun case WM8994_FLL2_CONTROL_4:
847*4882a593Smuzhiyun case WM8994_FLL2_CONTROL_5:
848*4882a593Smuzhiyun case WM8958_FLL2_EFS_1:
849*4882a593Smuzhiyun case WM8958_FLL2_EFS_2:
850*4882a593Smuzhiyun case WM8994_AIF1_CONTROL_1:
851*4882a593Smuzhiyun case WM8994_AIF1_CONTROL_2:
852*4882a593Smuzhiyun case WM8994_AIF1_MASTER_SLAVE:
853*4882a593Smuzhiyun case WM8994_AIF1_BCLK:
854*4882a593Smuzhiyun case WM8994_AIF1ADC_LRCLK:
855*4882a593Smuzhiyun case WM8994_AIF1DAC_LRCLK:
856*4882a593Smuzhiyun case WM8994_AIF1DAC_DATA:
857*4882a593Smuzhiyun case WM8994_AIF1ADC_DATA:
858*4882a593Smuzhiyun case WM8994_AIF2_CONTROL_1:
859*4882a593Smuzhiyun case WM8994_AIF2_CONTROL_2:
860*4882a593Smuzhiyun case WM8994_AIF2_MASTER_SLAVE:
861*4882a593Smuzhiyun case WM8994_AIF2_BCLK:
862*4882a593Smuzhiyun case WM8994_AIF2ADC_LRCLK:
863*4882a593Smuzhiyun case WM8994_AIF2DAC_LRCLK:
864*4882a593Smuzhiyun case WM8994_AIF2DAC_DATA:
865*4882a593Smuzhiyun case WM8994_AIF2ADC_DATA:
866*4882a593Smuzhiyun case WM1811_AIF2TX_CONTROL:
867*4882a593Smuzhiyun case WM8958_AIF3_CONTROL_1:
868*4882a593Smuzhiyun case WM8958_AIF3_CONTROL_2:
869*4882a593Smuzhiyun case WM8958_AIF3DAC_DATA:
870*4882a593Smuzhiyun case WM8958_AIF3ADC_DATA:
871*4882a593Smuzhiyun case WM8994_AIF1_ADC1_LEFT_VOLUME:
872*4882a593Smuzhiyun case WM8994_AIF1_ADC1_RIGHT_VOLUME:
873*4882a593Smuzhiyun case WM8994_AIF1_DAC1_LEFT_VOLUME:
874*4882a593Smuzhiyun case WM8994_AIF1_DAC1_RIGHT_VOLUME:
875*4882a593Smuzhiyun case WM8994_AIF1_ADC1_FILTERS:
876*4882a593Smuzhiyun case WM8994_AIF1_ADC2_FILTERS:
877*4882a593Smuzhiyun case WM8994_AIF1_DAC1_FILTERS_1:
878*4882a593Smuzhiyun case WM8994_AIF1_DAC1_FILTERS_2:
879*4882a593Smuzhiyun case WM8994_AIF1_DAC2_FILTERS_1:
880*4882a593Smuzhiyun case WM8994_AIF1_DAC2_FILTERS_2:
881*4882a593Smuzhiyun case WM8958_AIF1_DAC1_NOISE_GATE:
882*4882a593Smuzhiyun case WM8958_AIF1_DAC2_NOISE_GATE:
883*4882a593Smuzhiyun case WM8994_AIF1_DRC1_1:
884*4882a593Smuzhiyun case WM8994_AIF1_DRC1_2:
885*4882a593Smuzhiyun case WM8994_AIF1_DRC1_3:
886*4882a593Smuzhiyun case WM8994_AIF1_DRC1_4:
887*4882a593Smuzhiyun case WM8994_AIF1_DRC1_5:
888*4882a593Smuzhiyun case WM8994_AIF1_DRC2_1:
889*4882a593Smuzhiyun case WM8994_AIF1_DRC2_2:
890*4882a593Smuzhiyun case WM8994_AIF1_DRC2_3:
891*4882a593Smuzhiyun case WM8994_AIF1_DRC2_4:
892*4882a593Smuzhiyun case WM8994_AIF1_DRC2_5:
893*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_GAINS_1:
894*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_GAINS_2:
895*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_1_A:
896*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_1_B:
897*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_1_PG:
898*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_2_A:
899*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_2_B:
900*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_2_C:
901*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_2_PG:
902*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_3_A:
903*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_3_B:
904*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_3_C:
905*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_3_PG:
906*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_4_A:
907*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_4_B:
908*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_4_C:
909*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_4_PG:
910*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_5_A:
911*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_5_B:
912*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_5_PG:
913*4882a593Smuzhiyun case WM8994_AIF1_DAC1_EQ_BAND_1_C:
914*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_GAINS_1:
915*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_GAINS_2:
916*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_A:
917*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_B:
918*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
919*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_A:
920*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_B:
921*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_C:
922*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
923*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_A:
924*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_B:
925*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_C:
926*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
927*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_A:
928*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_B:
929*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_C:
930*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
931*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_5_A:
932*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_5_B:
933*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
934*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_C:
935*4882a593Smuzhiyun case WM8994_AIF2_ADC_LEFT_VOLUME:
936*4882a593Smuzhiyun case WM8994_AIF2_ADC_RIGHT_VOLUME:
937*4882a593Smuzhiyun case WM8994_AIF2_DAC_LEFT_VOLUME:
938*4882a593Smuzhiyun case WM8994_AIF2_DAC_RIGHT_VOLUME:
939*4882a593Smuzhiyun case WM8994_AIF2_ADC_FILTERS:
940*4882a593Smuzhiyun case WM8994_AIF2_DAC_FILTERS_1:
941*4882a593Smuzhiyun case WM8994_AIF2_DAC_FILTERS_2:
942*4882a593Smuzhiyun case WM8958_AIF2_DAC_NOISE_GATE:
943*4882a593Smuzhiyun case WM8994_AIF2_DRC_1:
944*4882a593Smuzhiyun case WM8994_AIF2_DRC_2:
945*4882a593Smuzhiyun case WM8994_AIF2_DRC_3:
946*4882a593Smuzhiyun case WM8994_AIF2_DRC_4:
947*4882a593Smuzhiyun case WM8994_AIF2_DRC_5:
948*4882a593Smuzhiyun case WM8994_AIF2_EQ_GAINS_1:
949*4882a593Smuzhiyun case WM8994_AIF2_EQ_GAINS_2:
950*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_1_A:
951*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_1_B:
952*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_1_PG:
953*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_2_A:
954*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_2_B:
955*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_2_C:
956*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_2_PG:
957*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_3_A:
958*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_3_B:
959*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_3_C:
960*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_3_PG:
961*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_4_A:
962*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_4_B:
963*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_4_C:
964*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_4_PG:
965*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_5_A:
966*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_5_B:
967*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_5_PG:
968*4882a593Smuzhiyun case WM8994_AIF2_EQ_BAND_1_C:
969*4882a593Smuzhiyun case WM8994_DAC1_MIXER_VOLUMES:
970*4882a593Smuzhiyun case WM8994_DAC1_LEFT_MIXER_ROUTING:
971*4882a593Smuzhiyun case WM8994_DAC1_RIGHT_MIXER_ROUTING:
972*4882a593Smuzhiyun case WM8994_DAC2_MIXER_VOLUMES:
973*4882a593Smuzhiyun case WM8994_DAC2_LEFT_MIXER_ROUTING:
974*4882a593Smuzhiyun case WM8994_DAC2_RIGHT_MIXER_ROUTING:
975*4882a593Smuzhiyun case WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING:
976*4882a593Smuzhiyun case WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING:
977*4882a593Smuzhiyun case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
978*4882a593Smuzhiyun case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
979*4882a593Smuzhiyun case WM8994_DAC1_LEFT_VOLUME:
980*4882a593Smuzhiyun case WM8994_DAC1_RIGHT_VOLUME:
981*4882a593Smuzhiyun case WM8994_DAC2_LEFT_VOLUME:
982*4882a593Smuzhiyun case WM8994_DAC2_RIGHT_VOLUME:
983*4882a593Smuzhiyun case WM8994_DAC_SOFTMUTE:
984*4882a593Smuzhiyun case WM8994_OVERSAMPLING:
985*4882a593Smuzhiyun case WM8994_SIDETONE:
986*4882a593Smuzhiyun case WM8994_GPIO_1:
987*4882a593Smuzhiyun case WM8994_GPIO_2:
988*4882a593Smuzhiyun case WM8994_GPIO_3:
989*4882a593Smuzhiyun case WM8994_GPIO_4:
990*4882a593Smuzhiyun case WM8994_GPIO_5:
991*4882a593Smuzhiyun case WM8994_GPIO_6:
992*4882a593Smuzhiyun case WM8994_GPIO_8:
993*4882a593Smuzhiyun case WM8994_GPIO_9:
994*4882a593Smuzhiyun case WM8994_GPIO_10:
995*4882a593Smuzhiyun case WM8994_GPIO_11:
996*4882a593Smuzhiyun case WM8994_PULL_CONTROL_1:
997*4882a593Smuzhiyun case WM8994_PULL_CONTROL_2:
998*4882a593Smuzhiyun case WM8994_INTERRUPT_STATUS_1:
999*4882a593Smuzhiyun case WM8994_INTERRUPT_STATUS_2:
1000*4882a593Smuzhiyun case WM8994_INTERRUPT_RAW_STATUS_2:
1001*4882a593Smuzhiyun case WM8994_INTERRUPT_STATUS_1_MASK:
1002*4882a593Smuzhiyun case WM8994_INTERRUPT_STATUS_2_MASK:
1003*4882a593Smuzhiyun case WM8994_INTERRUPT_CONTROL:
1004*4882a593Smuzhiyun case WM8994_IRQ_DEBOUNCE:
1005*4882a593Smuzhiyun return true;
1006*4882a593Smuzhiyun default:
1007*4882a593Smuzhiyun return false;
1008*4882a593Smuzhiyun }
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
wm8994_readable_register(struct device * dev,unsigned int reg)1011*4882a593Smuzhiyun static bool wm8994_readable_register(struct device *dev, unsigned int reg)
1012*4882a593Smuzhiyun {
1013*4882a593Smuzhiyun switch (reg) {
1014*4882a593Smuzhiyun case WM8994_DC_SERVO_READBACK:
1015*4882a593Smuzhiyun case WM8994_MICBIAS:
1016*4882a593Smuzhiyun case WM8994_WRITE_SEQUENCER_CTRL_1:
1017*4882a593Smuzhiyun case WM8994_WRITE_SEQUENCER_CTRL_2:
1018*4882a593Smuzhiyun case WM8994_AIF1_ADC2_LEFT_VOLUME:
1019*4882a593Smuzhiyun case WM8994_AIF1_ADC2_RIGHT_VOLUME:
1020*4882a593Smuzhiyun case WM8994_AIF1_DAC2_LEFT_VOLUME:
1021*4882a593Smuzhiyun case WM8994_AIF1_DAC2_RIGHT_VOLUME:
1022*4882a593Smuzhiyun case WM8994_AIF1_ADC2_FILTERS:
1023*4882a593Smuzhiyun case WM8994_AIF1_DAC2_FILTERS_1:
1024*4882a593Smuzhiyun case WM8994_AIF1_DAC2_FILTERS_2:
1025*4882a593Smuzhiyun case WM8958_AIF1_DAC2_NOISE_GATE:
1026*4882a593Smuzhiyun case WM8994_AIF1_DRC2_1:
1027*4882a593Smuzhiyun case WM8994_AIF1_DRC2_2:
1028*4882a593Smuzhiyun case WM8994_AIF1_DRC2_3:
1029*4882a593Smuzhiyun case WM8994_AIF1_DRC2_4:
1030*4882a593Smuzhiyun case WM8994_AIF1_DRC2_5:
1031*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_GAINS_1:
1032*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_GAINS_2:
1033*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_A:
1034*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_B:
1035*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
1036*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_A:
1037*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_B:
1038*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_C:
1039*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
1040*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_A:
1041*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_B:
1042*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_C:
1043*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
1044*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_A:
1045*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_B:
1046*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_C:
1047*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
1048*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_5_A:
1049*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_5_B:
1050*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
1051*4882a593Smuzhiyun case WM8994_AIF1_DAC2_EQ_BAND_1_C:
1052*4882a593Smuzhiyun case WM8994_DAC2_MIXER_VOLUMES:
1053*4882a593Smuzhiyun case WM8994_DAC2_LEFT_MIXER_ROUTING:
1054*4882a593Smuzhiyun case WM8994_DAC2_RIGHT_MIXER_ROUTING:
1055*4882a593Smuzhiyun case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
1056*4882a593Smuzhiyun case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
1057*4882a593Smuzhiyun case WM8994_DAC2_LEFT_VOLUME:
1058*4882a593Smuzhiyun case WM8994_DAC2_RIGHT_VOLUME:
1059*4882a593Smuzhiyun return true;
1060*4882a593Smuzhiyun default:
1061*4882a593Smuzhiyun return wm1811_readable_register(dev, reg);
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
wm8958_readable_register(struct device * dev,unsigned int reg)1065*4882a593Smuzhiyun static bool wm8958_readable_register(struct device *dev, unsigned int reg)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun switch (reg) {
1068*4882a593Smuzhiyun case WM8958_DSP2_PROGRAM:
1069*4882a593Smuzhiyun case WM8958_DSP2_CONFIG:
1070*4882a593Smuzhiyun case WM8958_DSP2_MAGICNUM:
1071*4882a593Smuzhiyun case WM8958_DSP2_RELEASEYEAR:
1072*4882a593Smuzhiyun case WM8958_DSP2_RELEASEMONTHDAY:
1073*4882a593Smuzhiyun case WM8958_DSP2_RELEASETIME:
1074*4882a593Smuzhiyun case WM8958_DSP2_VERMAJMIN:
1075*4882a593Smuzhiyun case WM8958_DSP2_VERBUILD:
1076*4882a593Smuzhiyun case WM8958_DSP2_TESTREG:
1077*4882a593Smuzhiyun case WM8958_DSP2_XORREG:
1078*4882a593Smuzhiyun case WM8958_DSP2_SHIFTMAXX:
1079*4882a593Smuzhiyun case WM8958_DSP2_SHIFTMAXY:
1080*4882a593Smuzhiyun case WM8958_DSP2_SHIFTMAXZ:
1081*4882a593Smuzhiyun case WM8958_DSP2_SHIFTMAXEXTLO:
1082*4882a593Smuzhiyun case WM8958_DSP2_AESSELECT:
1083*4882a593Smuzhiyun case WM8958_DSP2_EXECCONTROL:
1084*4882a593Smuzhiyun case WM8958_DSP2_SAMPLEBREAK:
1085*4882a593Smuzhiyun case WM8958_DSP2_COUNTBREAK:
1086*4882a593Smuzhiyun case WM8958_DSP2_INTSTATUS:
1087*4882a593Smuzhiyun case WM8958_DSP2_EVENTSTATUS:
1088*4882a593Smuzhiyun case WM8958_DSP2_INTMASK:
1089*4882a593Smuzhiyun case WM8958_DSP2_CONFIGDWIDTH:
1090*4882a593Smuzhiyun case WM8958_DSP2_CONFIGINSTR:
1091*4882a593Smuzhiyun case WM8958_DSP2_CONFIGDMEM:
1092*4882a593Smuzhiyun case WM8958_DSP2_CONFIGDELAYS:
1093*4882a593Smuzhiyun case WM8958_DSP2_CONFIGNUMIO:
1094*4882a593Smuzhiyun case WM8958_DSP2_CONFIGEXTDEPTH:
1095*4882a593Smuzhiyun case WM8958_DSP2_CONFIGMULTIPLIER:
1096*4882a593Smuzhiyun case WM8958_DSP2_CONFIGCTRLDWIDTH:
1097*4882a593Smuzhiyun case WM8958_DSP2_CONFIGPIPELINE:
1098*4882a593Smuzhiyun case WM8958_DSP2_SHIFTMAXEXTHI:
1099*4882a593Smuzhiyun case WM8958_DSP2_SWVERSIONREG:
1100*4882a593Smuzhiyun case WM8958_DSP2_CONFIGXMEM:
1101*4882a593Smuzhiyun case WM8958_DSP2_CONFIGYMEM:
1102*4882a593Smuzhiyun case WM8958_DSP2_CONFIGZMEM:
1103*4882a593Smuzhiyun case WM8958_FW_BUILD_1:
1104*4882a593Smuzhiyun case WM8958_FW_BUILD_0:
1105*4882a593Smuzhiyun case WM8958_FW_ID_1:
1106*4882a593Smuzhiyun case WM8958_FW_ID_0:
1107*4882a593Smuzhiyun case WM8958_FW_MAJOR_1:
1108*4882a593Smuzhiyun case WM8958_FW_MAJOR_0:
1109*4882a593Smuzhiyun case WM8958_FW_MINOR_1:
1110*4882a593Smuzhiyun case WM8958_FW_MINOR_0:
1111*4882a593Smuzhiyun case WM8958_FW_PATCH_1:
1112*4882a593Smuzhiyun case WM8958_FW_PATCH_0:
1113*4882a593Smuzhiyun case WM8958_MBC_BAND_1_K_1:
1114*4882a593Smuzhiyun case WM8958_MBC_BAND_1_K_2:
1115*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N1_1:
1116*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N1_2:
1117*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N2_1:
1118*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N2_2:
1119*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N3_1:
1120*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N3_2:
1121*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N4_1:
1122*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N4_2:
1123*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N5_1:
1124*4882a593Smuzhiyun case WM8958_MBC_BAND_1_N5_2:
1125*4882a593Smuzhiyun case WM8958_MBC_BAND_1_X1_1:
1126*4882a593Smuzhiyun case WM8958_MBC_BAND_1_X1_2:
1127*4882a593Smuzhiyun case WM8958_MBC_BAND_1_X2_1:
1128*4882a593Smuzhiyun case WM8958_MBC_BAND_1_X2_2:
1129*4882a593Smuzhiyun case WM8958_MBC_BAND_1_X3_1:
1130*4882a593Smuzhiyun case WM8958_MBC_BAND_1_X3_2:
1131*4882a593Smuzhiyun case WM8958_MBC_BAND_1_ATTACK_1:
1132*4882a593Smuzhiyun case WM8958_MBC_BAND_1_ATTACK_2:
1133*4882a593Smuzhiyun case WM8958_MBC_BAND_1_DECAY_1:
1134*4882a593Smuzhiyun case WM8958_MBC_BAND_1_DECAY_2:
1135*4882a593Smuzhiyun case WM8958_MBC_BAND_2_K_1:
1136*4882a593Smuzhiyun case WM8958_MBC_BAND_2_K_2:
1137*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N1_1:
1138*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N1_2:
1139*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N2_1:
1140*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N2_2:
1141*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N3_1:
1142*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N3_2:
1143*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N4_1:
1144*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N4_2:
1145*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N5_1:
1146*4882a593Smuzhiyun case WM8958_MBC_BAND_2_N5_2:
1147*4882a593Smuzhiyun case WM8958_MBC_BAND_2_X1_1:
1148*4882a593Smuzhiyun case WM8958_MBC_BAND_2_X1_2:
1149*4882a593Smuzhiyun case WM8958_MBC_BAND_2_X2_1:
1150*4882a593Smuzhiyun case WM8958_MBC_BAND_2_X2_2:
1151*4882a593Smuzhiyun case WM8958_MBC_BAND_2_X3_1:
1152*4882a593Smuzhiyun case WM8958_MBC_BAND_2_X3_2:
1153*4882a593Smuzhiyun case WM8958_MBC_BAND_2_ATTACK_1:
1154*4882a593Smuzhiyun case WM8958_MBC_BAND_2_ATTACK_2:
1155*4882a593Smuzhiyun case WM8958_MBC_BAND_2_DECAY_1:
1156*4882a593Smuzhiyun case WM8958_MBC_BAND_2_DECAY_2:
1157*4882a593Smuzhiyun case WM8958_MBC_B2_PG2_1:
1158*4882a593Smuzhiyun case WM8958_MBC_B2_PG2_2:
1159*4882a593Smuzhiyun case WM8958_MBC_B1_PG2_1:
1160*4882a593Smuzhiyun case WM8958_MBC_B1_PG2_2:
1161*4882a593Smuzhiyun case WM8958_MBC_CROSSOVER_1:
1162*4882a593Smuzhiyun case WM8958_MBC_CROSSOVER_2:
1163*4882a593Smuzhiyun case WM8958_MBC_HPF_1:
1164*4882a593Smuzhiyun case WM8958_MBC_HPF_2:
1165*4882a593Smuzhiyun case WM8958_MBC_LPF_1:
1166*4882a593Smuzhiyun case WM8958_MBC_LPF_2:
1167*4882a593Smuzhiyun case WM8958_MBC_RMS_LIMIT_1:
1168*4882a593Smuzhiyun case WM8958_MBC_RMS_LIMIT_2:
1169*4882a593Smuzhiyun return true;
1170*4882a593Smuzhiyun default:
1171*4882a593Smuzhiyun return wm8994_readable_register(dev, reg);
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun
wm8994_volatile_register(struct device * dev,unsigned int reg)1175*4882a593Smuzhiyun static bool wm8994_volatile_register(struct device *dev, unsigned int reg)
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun switch (reg) {
1178*4882a593Smuzhiyun case WM8994_SOFTWARE_RESET:
1179*4882a593Smuzhiyun case WM8994_DC_SERVO_1:
1180*4882a593Smuzhiyun case WM8994_DC_SERVO_READBACK:
1181*4882a593Smuzhiyun case WM8994_RATE_STATUS:
1182*4882a593Smuzhiyun case WM8958_MIC_DETECT_3:
1183*4882a593Smuzhiyun case WM8994_DC_SERVO_4E:
1184*4882a593Smuzhiyun case WM8994_INTERRUPT_STATUS_1:
1185*4882a593Smuzhiyun case WM8994_INTERRUPT_STATUS_2:
1186*4882a593Smuzhiyun return true;
1187*4882a593Smuzhiyun default:
1188*4882a593Smuzhiyun return false;
1189*4882a593Smuzhiyun }
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun
wm1811_volatile_register(struct device * dev,unsigned int reg)1192*4882a593Smuzhiyun static bool wm1811_volatile_register(struct device *dev, unsigned int reg)
1193*4882a593Smuzhiyun {
1194*4882a593Smuzhiyun struct wm8994 *wm8994 = dev_get_drvdata(dev);
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun switch (reg) {
1197*4882a593Smuzhiyun case WM8994_GPIO_6:
1198*4882a593Smuzhiyun if (wm8994->cust_id > 1 || wm8994->revision > 1)
1199*4882a593Smuzhiyun return true;
1200*4882a593Smuzhiyun else
1201*4882a593Smuzhiyun return false;
1202*4882a593Smuzhiyun default:
1203*4882a593Smuzhiyun return wm8994_volatile_register(dev, reg);
1204*4882a593Smuzhiyun }
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun
wm8958_volatile_register(struct device * dev,unsigned int reg)1207*4882a593Smuzhiyun static bool wm8958_volatile_register(struct device *dev, unsigned int reg)
1208*4882a593Smuzhiyun {
1209*4882a593Smuzhiyun switch (reg) {
1210*4882a593Smuzhiyun case WM8958_DSP2_MAGICNUM:
1211*4882a593Smuzhiyun case WM8958_DSP2_RELEASEYEAR:
1212*4882a593Smuzhiyun case WM8958_DSP2_RELEASEMONTHDAY:
1213*4882a593Smuzhiyun case WM8958_DSP2_RELEASETIME:
1214*4882a593Smuzhiyun case WM8958_DSP2_VERMAJMIN:
1215*4882a593Smuzhiyun case WM8958_DSP2_VERBUILD:
1216*4882a593Smuzhiyun case WM8958_DSP2_EXECCONTROL:
1217*4882a593Smuzhiyun case WM8958_DSP2_SWVERSIONREG:
1218*4882a593Smuzhiyun case WM8958_DSP2_CONFIGXMEM:
1219*4882a593Smuzhiyun case WM8958_DSP2_CONFIGYMEM:
1220*4882a593Smuzhiyun case WM8958_DSP2_CONFIGZMEM:
1221*4882a593Smuzhiyun case WM8958_FW_BUILD_1:
1222*4882a593Smuzhiyun case WM8958_FW_BUILD_0:
1223*4882a593Smuzhiyun case WM8958_FW_ID_1:
1224*4882a593Smuzhiyun case WM8958_FW_ID_0:
1225*4882a593Smuzhiyun case WM8958_FW_MAJOR_1:
1226*4882a593Smuzhiyun case WM8958_FW_MAJOR_0:
1227*4882a593Smuzhiyun case WM8958_FW_MINOR_1:
1228*4882a593Smuzhiyun case WM8958_FW_MINOR_0:
1229*4882a593Smuzhiyun case WM8958_FW_PATCH_1:
1230*4882a593Smuzhiyun case WM8958_FW_PATCH_0:
1231*4882a593Smuzhiyun return true;
1232*4882a593Smuzhiyun default:
1233*4882a593Smuzhiyun return wm8994_volatile_register(dev, reg);
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun struct regmap_config wm1811_regmap_config = {
1238*4882a593Smuzhiyun .reg_bits = 16,
1239*4882a593Smuzhiyun .val_bits = 16,
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun .reg_defaults = wm1811_defaults,
1244*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm1811_defaults),
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun .max_register = WM8994_MAX_REGISTER,
1247*4882a593Smuzhiyun .volatile_reg = wm1811_volatile_register,
1248*4882a593Smuzhiyun .readable_reg = wm1811_readable_register,
1249*4882a593Smuzhiyun };
1250*4882a593Smuzhiyun EXPORT_SYMBOL(wm1811_regmap_config);
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun struct regmap_config wm8994_regmap_config = {
1253*4882a593Smuzhiyun .reg_bits = 16,
1254*4882a593Smuzhiyun .val_bits = 16,
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun .reg_defaults = wm8994_defaults,
1259*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm8994_defaults),
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun .max_register = WM8994_MAX_REGISTER,
1262*4882a593Smuzhiyun .volatile_reg = wm8994_volatile_register,
1263*4882a593Smuzhiyun .readable_reg = wm8994_readable_register,
1264*4882a593Smuzhiyun };
1265*4882a593Smuzhiyun EXPORT_SYMBOL(wm8994_regmap_config);
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun struct regmap_config wm8958_regmap_config = {
1268*4882a593Smuzhiyun .reg_bits = 16,
1269*4882a593Smuzhiyun .val_bits = 16,
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun .reg_defaults = wm8958_defaults,
1274*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm8958_defaults),
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun .max_register = WM8994_MAX_REGISTER,
1277*4882a593Smuzhiyun .volatile_reg = wm8958_volatile_register,
1278*4882a593Smuzhiyun .readable_reg = wm8958_readable_register,
1279*4882a593Smuzhiyun };
1280*4882a593Smuzhiyun EXPORT_SYMBOL(wm8958_regmap_config);
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun struct regmap_config wm8994_base_regmap_config = {
1283*4882a593Smuzhiyun .reg_bits = 16,
1284*4882a593Smuzhiyun .val_bits = 16,
1285*4882a593Smuzhiyun };
1286*4882a593Smuzhiyun EXPORT_SYMBOL(wm8994_base_regmap_config);
1287