1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2010 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/gpio.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/mfd/core.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/irqdomain.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/mfd/wm8994/core.h>
21*4882a593Smuzhiyun #include <linux/mfd/wm8994/pdata.h>
22*4882a593Smuzhiyun #include <linux/mfd/wm8994/registers.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <linux/delay.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static const struct regmap_irq wm8994_irqs[] = {
27*4882a593Smuzhiyun [WM8994_IRQ_TEMP_SHUT] = {
28*4882a593Smuzhiyun .reg_offset = 1,
29*4882a593Smuzhiyun .mask = WM8994_TEMP_SHUT_EINT,
30*4882a593Smuzhiyun },
31*4882a593Smuzhiyun [WM8994_IRQ_MIC1_DET] = {
32*4882a593Smuzhiyun .reg_offset = 1,
33*4882a593Smuzhiyun .mask = WM8994_MIC1_DET_EINT,
34*4882a593Smuzhiyun },
35*4882a593Smuzhiyun [WM8994_IRQ_MIC1_SHRT] = {
36*4882a593Smuzhiyun .reg_offset = 1,
37*4882a593Smuzhiyun .mask = WM8994_MIC1_SHRT_EINT,
38*4882a593Smuzhiyun },
39*4882a593Smuzhiyun [WM8994_IRQ_MIC2_DET] = {
40*4882a593Smuzhiyun .reg_offset = 1,
41*4882a593Smuzhiyun .mask = WM8994_MIC2_DET_EINT,
42*4882a593Smuzhiyun },
43*4882a593Smuzhiyun [WM8994_IRQ_MIC2_SHRT] = {
44*4882a593Smuzhiyun .reg_offset = 1,
45*4882a593Smuzhiyun .mask = WM8994_MIC2_SHRT_EINT,
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun [WM8994_IRQ_FLL1_LOCK] = {
48*4882a593Smuzhiyun .reg_offset = 1,
49*4882a593Smuzhiyun .mask = WM8994_FLL1_LOCK_EINT,
50*4882a593Smuzhiyun },
51*4882a593Smuzhiyun [WM8994_IRQ_FLL2_LOCK] = {
52*4882a593Smuzhiyun .reg_offset = 1,
53*4882a593Smuzhiyun .mask = WM8994_FLL2_LOCK_EINT,
54*4882a593Smuzhiyun },
55*4882a593Smuzhiyun [WM8994_IRQ_SRC1_LOCK] = {
56*4882a593Smuzhiyun .reg_offset = 1,
57*4882a593Smuzhiyun .mask = WM8994_SRC1_LOCK_EINT,
58*4882a593Smuzhiyun },
59*4882a593Smuzhiyun [WM8994_IRQ_SRC2_LOCK] = {
60*4882a593Smuzhiyun .reg_offset = 1,
61*4882a593Smuzhiyun .mask = WM8994_SRC2_LOCK_EINT,
62*4882a593Smuzhiyun },
63*4882a593Smuzhiyun [WM8994_IRQ_AIF1DRC1_SIG_DET] = {
64*4882a593Smuzhiyun .reg_offset = 1,
65*4882a593Smuzhiyun .mask = WM8994_AIF1DRC1_SIG_DET,
66*4882a593Smuzhiyun },
67*4882a593Smuzhiyun [WM8994_IRQ_AIF1DRC2_SIG_DET] = {
68*4882a593Smuzhiyun .reg_offset = 1,
69*4882a593Smuzhiyun .mask = WM8994_AIF1DRC2_SIG_DET_EINT,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun [WM8994_IRQ_AIF2DRC_SIG_DET] = {
72*4882a593Smuzhiyun .reg_offset = 1,
73*4882a593Smuzhiyun .mask = WM8994_AIF2DRC_SIG_DET_EINT,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun [WM8994_IRQ_FIFOS_ERR] = {
76*4882a593Smuzhiyun .reg_offset = 1,
77*4882a593Smuzhiyun .mask = WM8994_FIFOS_ERR_EINT,
78*4882a593Smuzhiyun },
79*4882a593Smuzhiyun [WM8994_IRQ_WSEQ_DONE] = {
80*4882a593Smuzhiyun .reg_offset = 1,
81*4882a593Smuzhiyun .mask = WM8994_WSEQ_DONE_EINT,
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun [WM8994_IRQ_DCS_DONE] = {
84*4882a593Smuzhiyun .reg_offset = 1,
85*4882a593Smuzhiyun .mask = WM8994_DCS_DONE_EINT,
86*4882a593Smuzhiyun },
87*4882a593Smuzhiyun [WM8994_IRQ_TEMP_WARN] = {
88*4882a593Smuzhiyun .reg_offset = 1,
89*4882a593Smuzhiyun .mask = WM8994_TEMP_WARN_EINT,
90*4882a593Smuzhiyun },
91*4882a593Smuzhiyun [WM8994_IRQ_GPIO(1)] = {
92*4882a593Smuzhiyun .mask = WM8994_GP1_EINT,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun [WM8994_IRQ_GPIO(2)] = {
95*4882a593Smuzhiyun .mask = WM8994_GP2_EINT,
96*4882a593Smuzhiyun },
97*4882a593Smuzhiyun [WM8994_IRQ_GPIO(3)] = {
98*4882a593Smuzhiyun .mask = WM8994_GP3_EINT,
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun [WM8994_IRQ_GPIO(4)] = {
101*4882a593Smuzhiyun .mask = WM8994_GP4_EINT,
102*4882a593Smuzhiyun },
103*4882a593Smuzhiyun [WM8994_IRQ_GPIO(5)] = {
104*4882a593Smuzhiyun .mask = WM8994_GP5_EINT,
105*4882a593Smuzhiyun },
106*4882a593Smuzhiyun [WM8994_IRQ_GPIO(6)] = {
107*4882a593Smuzhiyun .mask = WM8994_GP6_EINT,
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun [WM8994_IRQ_GPIO(7)] = {
110*4882a593Smuzhiyun .mask = WM8994_GP7_EINT,
111*4882a593Smuzhiyun },
112*4882a593Smuzhiyun [WM8994_IRQ_GPIO(8)] = {
113*4882a593Smuzhiyun .mask = WM8994_GP8_EINT,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun [WM8994_IRQ_GPIO(9)] = {
116*4882a593Smuzhiyun .mask = WM8994_GP8_EINT,
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun [WM8994_IRQ_GPIO(10)] = {
119*4882a593Smuzhiyun .mask = WM8994_GP10_EINT,
120*4882a593Smuzhiyun },
121*4882a593Smuzhiyun [WM8994_IRQ_GPIO(11)] = {
122*4882a593Smuzhiyun .mask = WM8994_GP11_EINT,
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static const struct regmap_irq_chip wm8994_irq_chip = {
127*4882a593Smuzhiyun .name = "wm8994",
128*4882a593Smuzhiyun .irqs = wm8994_irqs,
129*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(wm8994_irqs),
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun .num_regs = 2,
132*4882a593Smuzhiyun .status_base = WM8994_INTERRUPT_STATUS_1,
133*4882a593Smuzhiyun .mask_base = WM8994_INTERRUPT_STATUS_1_MASK,
134*4882a593Smuzhiyun .ack_base = WM8994_INTERRUPT_STATUS_1,
135*4882a593Smuzhiyun .runtime_pm = true,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
wm8994_edge_irq_enable(struct irq_data * data)138*4882a593Smuzhiyun static void wm8994_edge_irq_enable(struct irq_data *data)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
wm8994_edge_irq_disable(struct irq_data * data)142*4882a593Smuzhiyun static void wm8994_edge_irq_disable(struct irq_data *data)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static struct irq_chip wm8994_edge_irq_chip = {
147*4882a593Smuzhiyun .name = "wm8994_edge",
148*4882a593Smuzhiyun .irq_disable = wm8994_edge_irq_disable,
149*4882a593Smuzhiyun .irq_enable = wm8994_edge_irq_enable,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
wm8994_edge_irq(int irq,void * data)152*4882a593Smuzhiyun static irqreturn_t wm8994_edge_irq(int irq, void *data)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct wm8994 *wm8994 = data;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio))
157*4882a593Smuzhiyun handle_nested_irq(irq_find_mapping(wm8994->edge_irq, 0));
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return IRQ_HANDLED;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
wm8994_edge_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)162*4882a593Smuzhiyun static int wm8994_edge_irq_map(struct irq_domain *h, unsigned int virq,
163*4882a593Smuzhiyun irq_hw_number_t hw)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct wm8994 *wm8994 = h->host_data;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun irq_set_chip_data(virq, wm8994);
168*4882a593Smuzhiyun irq_set_chip_and_handler(virq, &wm8994_edge_irq_chip, handle_edge_irq);
169*4882a593Smuzhiyun irq_set_nested_thread(virq, 1);
170*4882a593Smuzhiyun irq_set_noprobe(virq);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static const struct irq_domain_ops wm8994_edge_irq_ops = {
176*4882a593Smuzhiyun .map = wm8994_edge_irq_map,
177*4882a593Smuzhiyun .xlate = irq_domain_xlate_twocell,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
wm8994_irq_init(struct wm8994 * wm8994)180*4882a593Smuzhiyun int wm8994_irq_init(struct wm8994 *wm8994)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun int ret;
183*4882a593Smuzhiyun unsigned long irqflags;
184*4882a593Smuzhiyun struct wm8994_pdata *pdata = &wm8994->pdata;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun if (!wm8994->irq) {
187*4882a593Smuzhiyun dev_warn(wm8994->dev,
188*4882a593Smuzhiyun "No interrupt specified, no interrupts\n");
189*4882a593Smuzhiyun wm8994->irq_base = 0;
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* select user or default irq flags */
194*4882a593Smuzhiyun irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
195*4882a593Smuzhiyun if (pdata->irq_flags)
196*4882a593Smuzhiyun irqflags = pdata->irq_flags;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* use a GPIO for edge triggered controllers */
199*4882a593Smuzhiyun if (irqflags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
200*4882a593Smuzhiyun if (gpio_to_irq(pdata->irq_gpio) != wm8994->irq) {
201*4882a593Smuzhiyun dev_warn(wm8994->dev, "IRQ %d is not GPIO %d (%d)\n",
202*4882a593Smuzhiyun wm8994->irq, pdata->irq_gpio,
203*4882a593Smuzhiyun gpio_to_irq(pdata->irq_gpio));
204*4882a593Smuzhiyun wm8994->irq = gpio_to_irq(pdata->irq_gpio);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun ret = devm_gpio_request_one(wm8994->dev, pdata->irq_gpio,
208*4882a593Smuzhiyun GPIOF_IN, "WM8994 IRQ");
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun if (ret != 0) {
211*4882a593Smuzhiyun dev_err(wm8994->dev, "Failed to get IRQ GPIO: %d\n",
212*4882a593Smuzhiyun ret);
213*4882a593Smuzhiyun return ret;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun wm8994->edge_irq = irq_domain_add_linear(NULL, 1,
217*4882a593Smuzhiyun &wm8994_edge_irq_ops,
218*4882a593Smuzhiyun wm8994);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ret = regmap_add_irq_chip(wm8994->regmap,
221*4882a593Smuzhiyun irq_create_mapping(wm8994->edge_irq,
222*4882a593Smuzhiyun 0),
223*4882a593Smuzhiyun IRQF_ONESHOT,
224*4882a593Smuzhiyun wm8994->irq_base, &wm8994_irq_chip,
225*4882a593Smuzhiyun &wm8994->irq_data);
226*4882a593Smuzhiyun if (ret != 0) {
227*4882a593Smuzhiyun dev_err(wm8994->dev, "Failed to get IRQ: %d\n",
228*4882a593Smuzhiyun ret);
229*4882a593Smuzhiyun return ret;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun ret = request_threaded_irq(wm8994->irq,
233*4882a593Smuzhiyun NULL, wm8994_edge_irq,
234*4882a593Smuzhiyun irqflags,
235*4882a593Smuzhiyun "WM8994 edge", wm8994);
236*4882a593Smuzhiyun } else {
237*4882a593Smuzhiyun ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
238*4882a593Smuzhiyun irqflags,
239*4882a593Smuzhiyun wm8994->irq_base, &wm8994_irq_chip,
240*4882a593Smuzhiyun &wm8994->irq_data);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun if (ret != 0) {
244*4882a593Smuzhiyun dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret);
245*4882a593Smuzhiyun return ret;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Enable top level interrupt if it was masked */
249*4882a593Smuzhiyun wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun EXPORT_SYMBOL(wm8994_irq_init);
254*4882a593Smuzhiyun
wm8994_irq_exit(struct wm8994 * wm8994)255*4882a593Smuzhiyun void wm8994_irq_exit(struct wm8994 *wm8994)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun regmap_del_irq_chip(wm8994->irq, wm8994->irq_data);
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun EXPORT_SYMBOL(wm8994_irq_exit);
260