1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8350-core.c -- Device access for Wolfson WM8350
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Liam Girdwood, Mark Brown
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/export.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/bug.h>
15*4882a593Smuzhiyun #include <linux/device.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun #include <linux/workqueue.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/mfd/wm8350/core.h>
22*4882a593Smuzhiyun #include <linux/mfd/wm8350/audio.h>
23*4882a593Smuzhiyun #include <linux/mfd/wm8350/comparator.h>
24*4882a593Smuzhiyun #include <linux/mfd/wm8350/gpio.h>
25*4882a593Smuzhiyun #include <linux/mfd/wm8350/pmic.h>
26*4882a593Smuzhiyun #include <linux/mfd/wm8350/rtc.h>
27*4882a593Smuzhiyun #include <linux/mfd/wm8350/supply.h>
28*4882a593Smuzhiyun #include <linux/mfd/wm8350/wdt.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define WM8350_CLOCK_CONTROL_1 0x28
31*4882a593Smuzhiyun #define WM8350_AIF_TEST 0x74
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* debug */
34*4882a593Smuzhiyun #define WM8350_BUS_DEBUG 0
35*4882a593Smuzhiyun #if WM8350_BUS_DEBUG
36*4882a593Smuzhiyun #define dump(regs, src) do { \
37*4882a593Smuzhiyun int i_; \
38*4882a593Smuzhiyun u16 *src_ = src; \
39*4882a593Smuzhiyun printk(KERN_DEBUG); \
40*4882a593Smuzhiyun for (i_ = 0; i_ < regs; i_++) \
41*4882a593Smuzhiyun printk(" 0x%4.4x", *src_++); \
42*4882a593Smuzhiyun printk("\n"); \
43*4882a593Smuzhiyun } while (0);
44*4882a593Smuzhiyun #else
45*4882a593Smuzhiyun #define dump(bytes, src)
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define WM8350_LOCK_DEBUG 0
49*4882a593Smuzhiyun #if WM8350_LOCK_DEBUG
50*4882a593Smuzhiyun #define ldbg(format, arg...) printk(format, ## arg)
51*4882a593Smuzhiyun #else
52*4882a593Smuzhiyun #define ldbg(format, arg...)
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * WM8350 Device IO
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun static DEFINE_MUTEX(reg_lock_mutex);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * Safe read, modify, write methods
62*4882a593Smuzhiyun */
wm8350_clear_bits(struct wm8350 * wm8350,u16 reg,u16 mask)63*4882a593Smuzhiyun int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun return regmap_update_bits(wm8350->regmap, reg, mask, 0);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_clear_bits);
68*4882a593Smuzhiyun
wm8350_set_bits(struct wm8350 * wm8350,u16 reg,u16 mask)69*4882a593Smuzhiyun int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun return regmap_update_bits(wm8350->regmap, reg, mask, mask);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_set_bits);
74*4882a593Smuzhiyun
wm8350_reg_read(struct wm8350 * wm8350,int reg)75*4882a593Smuzhiyun u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun unsigned int data;
78*4882a593Smuzhiyun int err;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun err = regmap_read(wm8350->regmap, reg, &data);
81*4882a593Smuzhiyun if (err)
82*4882a593Smuzhiyun dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return data;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_reg_read);
87*4882a593Smuzhiyun
wm8350_reg_write(struct wm8350 * wm8350,int reg,u16 val)88*4882a593Smuzhiyun int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ret = regmap_write(wm8350->regmap, reg, val);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (ret)
95*4882a593Smuzhiyun dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
96*4882a593Smuzhiyun return ret;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_reg_write);
99*4882a593Smuzhiyun
wm8350_block_read(struct wm8350 * wm8350,int start_reg,int regs,u16 * dest)100*4882a593Smuzhiyun int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
101*4882a593Smuzhiyun u16 *dest)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun int err = 0;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun err = regmap_bulk_read(wm8350->regmap, start_reg, dest, regs);
106*4882a593Smuzhiyun if (err)
107*4882a593Smuzhiyun dev_err(wm8350->dev, "block read starting from R%d failed\n",
108*4882a593Smuzhiyun start_reg);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return err;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_block_read);
113*4882a593Smuzhiyun
wm8350_block_write(struct wm8350 * wm8350,int start_reg,int regs,u16 * src)114*4882a593Smuzhiyun int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
115*4882a593Smuzhiyun u16 *src)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun int ret = 0;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ret = regmap_bulk_write(wm8350->regmap, start_reg, src, regs);
120*4882a593Smuzhiyun if (ret)
121*4882a593Smuzhiyun dev_err(wm8350->dev, "block write starting at R%d failed\n",
122*4882a593Smuzhiyun start_reg);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_block_write);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /**
129*4882a593Smuzhiyun * wm8350_reg_lock()
130*4882a593Smuzhiyun *
131*4882a593Smuzhiyun * The WM8350 has a hardware lock which can be used to prevent writes to
132*4882a593Smuzhiyun * some registers (generally those which can cause particularly serious
133*4882a593Smuzhiyun * problems if misused). This function enables that lock.
134*4882a593Smuzhiyun *
135*4882a593Smuzhiyun * @wm8350: pointer to local driver data structure
136*4882a593Smuzhiyun */
wm8350_reg_lock(struct wm8350 * wm8350)137*4882a593Smuzhiyun int wm8350_reg_lock(struct wm8350 *wm8350)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun int ret;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun mutex_lock(®_lock_mutex);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun ldbg(__func__);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_LOCK_KEY);
146*4882a593Smuzhiyun if (ret)
147*4882a593Smuzhiyun dev_err(wm8350->dev, "lock failed\n");
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun wm8350->unlocked = false;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun mutex_unlock(®_lock_mutex);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_reg_lock);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /**
158*4882a593Smuzhiyun * wm8350_reg_unlock()
159*4882a593Smuzhiyun *
160*4882a593Smuzhiyun * The WM8350 has a hardware lock which can be used to prevent writes to
161*4882a593Smuzhiyun * some registers (generally those which can cause particularly serious
162*4882a593Smuzhiyun * problems if misused). This function disables that lock so updates
163*4882a593Smuzhiyun * can be performed. For maximum safety this should be done only when
164*4882a593Smuzhiyun * required.
165*4882a593Smuzhiyun *
166*4882a593Smuzhiyun * @wm8350: pointer to local driver data structure
167*4882a593Smuzhiyun */
wm8350_reg_unlock(struct wm8350 * wm8350)168*4882a593Smuzhiyun int wm8350_reg_unlock(struct wm8350 *wm8350)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun int ret;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun mutex_lock(®_lock_mutex);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ldbg(__func__);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_UNLOCK_KEY);
177*4882a593Smuzhiyun if (ret)
178*4882a593Smuzhiyun dev_err(wm8350->dev, "unlock failed\n");
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun wm8350->unlocked = true;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun mutex_unlock(®_lock_mutex);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return ret;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
187*4882a593Smuzhiyun
wm8350_read_auxadc(struct wm8350 * wm8350,int channel,int scale,int vref)188*4882a593Smuzhiyun int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun u16 reg, result = 0;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
193*4882a593Smuzhiyun return -EINVAL;
194*4882a593Smuzhiyun if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
195*4882a593Smuzhiyun && (scale != 0 || vref != 0))
196*4882a593Smuzhiyun return -EINVAL;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun mutex_lock(&wm8350->auxadc_mutex);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /* Turn on the ADC */
201*4882a593Smuzhiyun reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
202*4882a593Smuzhiyun wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (scale || vref) {
205*4882a593Smuzhiyun reg = scale << 13;
206*4882a593Smuzhiyun reg |= vref << 12;
207*4882a593Smuzhiyun wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
211*4882a593Smuzhiyun reg |= 1 << channel | WM8350_AUXADC_POLL;
212*4882a593Smuzhiyun wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* If a late IRQ left the completion signalled then consume
215*4882a593Smuzhiyun * the completion. */
216*4882a593Smuzhiyun try_wait_for_completion(&wm8350->auxadc_done);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* We ignore the result of the completion and just check for a
219*4882a593Smuzhiyun * conversion result, allowing us to soldier on if the IRQ
220*4882a593Smuzhiyun * infrastructure is not set up for the chip. */
221*4882a593Smuzhiyun wait_for_completion_timeout(&wm8350->auxadc_done, msecs_to_jiffies(5));
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
224*4882a593Smuzhiyun if (reg & WM8350_AUXADC_POLL)
225*4882a593Smuzhiyun dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
226*4882a593Smuzhiyun else
227*4882a593Smuzhiyun result = wm8350_reg_read(wm8350,
228*4882a593Smuzhiyun WM8350_AUX1_READBACK + channel);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /* Turn off the ADC */
231*4882a593Smuzhiyun reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
232*4882a593Smuzhiyun wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
233*4882a593Smuzhiyun reg & ~WM8350_AUXADC_ENA);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun mutex_unlock(&wm8350->auxadc_mutex);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun return result & WM8350_AUXADC_DATA1_MASK;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
240*4882a593Smuzhiyun
wm8350_auxadc_irq(int irq,void * irq_data)241*4882a593Smuzhiyun static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun struct wm8350 *wm8350 = irq_data;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun complete(&wm8350->auxadc_done);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun return IRQ_HANDLED;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /*
251*4882a593Smuzhiyun * Register a client device. This is non-fatal since there is no need to
252*4882a593Smuzhiyun * fail the entire device init due to a single platform device failing.
253*4882a593Smuzhiyun */
wm8350_client_dev_register(struct wm8350 * wm8350,const char * name,struct platform_device ** pdev)254*4882a593Smuzhiyun static void wm8350_client_dev_register(struct wm8350 *wm8350,
255*4882a593Smuzhiyun const char *name,
256*4882a593Smuzhiyun struct platform_device **pdev)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun int ret;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun *pdev = platform_device_alloc(name, -1);
261*4882a593Smuzhiyun if (*pdev == NULL) {
262*4882a593Smuzhiyun dev_err(wm8350->dev, "Failed to allocate %s\n", name);
263*4882a593Smuzhiyun return;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun (*pdev)->dev.parent = wm8350->dev;
267*4882a593Smuzhiyun platform_set_drvdata(*pdev, wm8350);
268*4882a593Smuzhiyun ret = platform_device_add(*pdev);
269*4882a593Smuzhiyun if (ret != 0) {
270*4882a593Smuzhiyun dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
271*4882a593Smuzhiyun platform_device_put(*pdev);
272*4882a593Smuzhiyun *pdev = NULL;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
wm8350_device_init(struct wm8350 * wm8350,int irq,struct wm8350_platform_data * pdata)276*4882a593Smuzhiyun int wm8350_device_init(struct wm8350 *wm8350, int irq,
277*4882a593Smuzhiyun struct wm8350_platform_data *pdata)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun int ret;
280*4882a593Smuzhiyun unsigned int id1, id2, mask_rev;
281*4882a593Smuzhiyun unsigned int cust_id, mode, chip_rev;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun dev_set_drvdata(wm8350->dev, wm8350);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /* get WM8350 revision and config mode */
286*4882a593Smuzhiyun ret = regmap_read(wm8350->regmap, WM8350_RESET_ID, &id1);
287*4882a593Smuzhiyun if (ret != 0) {
288*4882a593Smuzhiyun dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
289*4882a593Smuzhiyun goto err;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun ret = regmap_read(wm8350->regmap, WM8350_ID, &id2);
293*4882a593Smuzhiyun if (ret != 0) {
294*4882a593Smuzhiyun dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
295*4882a593Smuzhiyun goto err;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun ret = regmap_read(wm8350->regmap, WM8350_REVISION, &mask_rev);
299*4882a593Smuzhiyun if (ret != 0) {
300*4882a593Smuzhiyun dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
301*4882a593Smuzhiyun goto err;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (id1 != 0x6143) {
305*4882a593Smuzhiyun dev_err(wm8350->dev,
306*4882a593Smuzhiyun "Device with ID %x is not a WM8350\n", id1);
307*4882a593Smuzhiyun ret = -ENODEV;
308*4882a593Smuzhiyun goto err;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun mode = (id2 & WM8350_CONF_STS_MASK) >> 10;
312*4882a593Smuzhiyun cust_id = id2 & WM8350_CUST_ID_MASK;
313*4882a593Smuzhiyun chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
314*4882a593Smuzhiyun dev_info(wm8350->dev,
315*4882a593Smuzhiyun "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
316*4882a593Smuzhiyun mode, cust_id, mask_rev, chip_rev);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun if (cust_id != 0) {
319*4882a593Smuzhiyun dev_err(wm8350->dev, "Unsupported CUST_ID\n");
320*4882a593Smuzhiyun ret = -ENODEV;
321*4882a593Smuzhiyun goto err;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun switch (mask_rev) {
325*4882a593Smuzhiyun case 0:
326*4882a593Smuzhiyun wm8350->pmic.max_dcdc = WM8350_DCDC_6;
327*4882a593Smuzhiyun wm8350->pmic.max_isink = WM8350_ISINK_B;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun switch (chip_rev) {
330*4882a593Smuzhiyun case WM8350_REV_E:
331*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8350 Rev E\n");
332*4882a593Smuzhiyun break;
333*4882a593Smuzhiyun case WM8350_REV_F:
334*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8350 Rev F\n");
335*4882a593Smuzhiyun break;
336*4882a593Smuzhiyun case WM8350_REV_G:
337*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8350 Rev G\n");
338*4882a593Smuzhiyun wm8350->power.rev_g_coeff = 1;
339*4882a593Smuzhiyun break;
340*4882a593Smuzhiyun case WM8350_REV_H:
341*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8350 Rev H\n");
342*4882a593Smuzhiyun wm8350->power.rev_g_coeff = 1;
343*4882a593Smuzhiyun break;
344*4882a593Smuzhiyun default:
345*4882a593Smuzhiyun /* For safety we refuse to run on unknown hardware */
346*4882a593Smuzhiyun dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
347*4882a593Smuzhiyun ret = -ENODEV;
348*4882a593Smuzhiyun goto err;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun break;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun case 1:
353*4882a593Smuzhiyun wm8350->pmic.max_dcdc = WM8350_DCDC_4;
354*4882a593Smuzhiyun wm8350->pmic.max_isink = WM8350_ISINK_A;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun switch (chip_rev) {
357*4882a593Smuzhiyun case 0:
358*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8351 Rev A\n");
359*4882a593Smuzhiyun wm8350->power.rev_g_coeff = 1;
360*4882a593Smuzhiyun break;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun case 1:
363*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8351 Rev B\n");
364*4882a593Smuzhiyun wm8350->power.rev_g_coeff = 1;
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun default:
368*4882a593Smuzhiyun dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
369*4882a593Smuzhiyun ret = -ENODEV;
370*4882a593Smuzhiyun goto err;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun break;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun case 2:
375*4882a593Smuzhiyun wm8350->pmic.max_dcdc = WM8350_DCDC_6;
376*4882a593Smuzhiyun wm8350->pmic.max_isink = WM8350_ISINK_B;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun switch (chip_rev) {
379*4882a593Smuzhiyun case 0:
380*4882a593Smuzhiyun dev_info(wm8350->dev, "WM8352 Rev A\n");
381*4882a593Smuzhiyun wm8350->power.rev_g_coeff = 1;
382*4882a593Smuzhiyun break;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun default:
385*4882a593Smuzhiyun dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
386*4882a593Smuzhiyun ret = -ENODEV;
387*4882a593Smuzhiyun goto err;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun break;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun default:
392*4882a593Smuzhiyun dev_err(wm8350->dev, "Unknown MASK_REV\n");
393*4882a593Smuzhiyun ret = -ENODEV;
394*4882a593Smuzhiyun goto err;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun mutex_init(&wm8350->auxadc_mutex);
398*4882a593Smuzhiyun init_completion(&wm8350->auxadc_done);
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun ret = wm8350_irq_init(wm8350, irq, pdata);
401*4882a593Smuzhiyun if (ret < 0)
402*4882a593Smuzhiyun goto err;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun if (wm8350->irq_base) {
405*4882a593Smuzhiyun ret = request_threaded_irq(wm8350->irq_base +
406*4882a593Smuzhiyun WM8350_IRQ_AUXADC_DATARDY,
407*4882a593Smuzhiyun NULL, wm8350_auxadc_irq,
408*4882a593Smuzhiyun IRQF_ONESHOT,
409*4882a593Smuzhiyun "auxadc", wm8350);
410*4882a593Smuzhiyun if (ret < 0)
411*4882a593Smuzhiyun dev_warn(wm8350->dev,
412*4882a593Smuzhiyun "Failed to request AUXADC IRQ: %d\n", ret);
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun if (pdata && pdata->init) {
416*4882a593Smuzhiyun ret = pdata->init(wm8350);
417*4882a593Smuzhiyun if (ret != 0) {
418*4882a593Smuzhiyun dev_err(wm8350->dev, "Platform init() failed: %d\n",
419*4882a593Smuzhiyun ret);
420*4882a593Smuzhiyun goto err_irq;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun wm8350_client_dev_register(wm8350, "wm8350-codec",
427*4882a593Smuzhiyun &(wm8350->codec.pdev));
428*4882a593Smuzhiyun wm8350_client_dev_register(wm8350, "wm8350-gpio",
429*4882a593Smuzhiyun &(wm8350->gpio.pdev));
430*4882a593Smuzhiyun wm8350_client_dev_register(wm8350, "wm8350-hwmon",
431*4882a593Smuzhiyun &(wm8350->hwmon.pdev));
432*4882a593Smuzhiyun wm8350_client_dev_register(wm8350, "wm8350-power",
433*4882a593Smuzhiyun &(wm8350->power.pdev));
434*4882a593Smuzhiyun wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
435*4882a593Smuzhiyun wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun return 0;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun err_irq:
440*4882a593Smuzhiyun wm8350_irq_exit(wm8350);
441*4882a593Smuzhiyun err:
442*4882a593Smuzhiyun return ret;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm8350_device_init);
445