xref: /OK3568_Linux_fs/kernel/drivers/mfd/wm831x-auxadc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * wm831x-auxadc.c  --  AUXADC for Wolfson WM831x PMICs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2009-2011 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/mfd/core.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/list.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/mfd/wm831x/core.h>
18*4882a593Smuzhiyun #include <linux/mfd/wm831x/pdata.h>
19*4882a593Smuzhiyun #include <linux/mfd/wm831x/irq.h>
20*4882a593Smuzhiyun #include <linux/mfd/wm831x/auxadc.h>
21*4882a593Smuzhiyun #include <linux/mfd/wm831x/otp.h>
22*4882a593Smuzhiyun #include <linux/mfd/wm831x/regulator.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun struct wm831x_auxadc_req {
25*4882a593Smuzhiyun 	struct list_head list;
26*4882a593Smuzhiyun 	enum wm831x_auxadc input;
27*4882a593Smuzhiyun 	int val;
28*4882a593Smuzhiyun 	struct completion done;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
wm831x_auxadc_read_irq(struct wm831x * wm831x,enum wm831x_auxadc input)31*4882a593Smuzhiyun static int wm831x_auxadc_read_irq(struct wm831x *wm831x,
32*4882a593Smuzhiyun 				  enum wm831x_auxadc input)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	struct wm831x_auxadc_req *req;
35*4882a593Smuzhiyun 	int ret;
36*4882a593Smuzhiyun 	bool ena = false;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	req = kzalloc(sizeof(*req), GFP_KERNEL);
39*4882a593Smuzhiyun 	if (!req)
40*4882a593Smuzhiyun 		return -ENOMEM;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	init_completion(&req->done);
43*4882a593Smuzhiyun 	req->input = input;
44*4882a593Smuzhiyun 	req->val = -ETIMEDOUT;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	mutex_lock(&wm831x->auxadc_lock);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	/* Enqueue the request */
49*4882a593Smuzhiyun 	list_add(&req->list, &wm831x->auxadc_pending);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	ena = !wm831x->auxadc_active;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	if (ena) {
54*4882a593Smuzhiyun 		ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
55*4882a593Smuzhiyun 				      WM831X_AUX_ENA, WM831X_AUX_ENA);
56*4882a593Smuzhiyun 		if (ret != 0) {
57*4882a593Smuzhiyun 			dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n",
58*4882a593Smuzhiyun 				ret);
59*4882a593Smuzhiyun 			goto out;
60*4882a593Smuzhiyun 		}
61*4882a593Smuzhiyun 	}
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	/* Enable the conversion if not already running */
64*4882a593Smuzhiyun 	if (!(wm831x->auxadc_active & (1 << input))) {
65*4882a593Smuzhiyun 		ret = wm831x_set_bits(wm831x, WM831X_AUXADC_SOURCE,
66*4882a593Smuzhiyun 				      1 << input, 1 << input);
67*4882a593Smuzhiyun 		if (ret != 0) {
68*4882a593Smuzhiyun 			dev_err(wm831x->dev,
69*4882a593Smuzhiyun 				"Failed to set AUXADC source: %d\n", ret);
70*4882a593Smuzhiyun 			goto out;
71*4882a593Smuzhiyun 		}
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 		wm831x->auxadc_active |= 1 << input;
74*4882a593Smuzhiyun 	}
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	/* We convert at the fastest rate possible */
77*4882a593Smuzhiyun 	if (ena) {
78*4882a593Smuzhiyun 		ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
79*4882a593Smuzhiyun 				      WM831X_AUX_CVT_ENA |
80*4882a593Smuzhiyun 				      WM831X_AUX_RATE_MASK,
81*4882a593Smuzhiyun 				      WM831X_AUX_CVT_ENA |
82*4882a593Smuzhiyun 				      WM831X_AUX_RATE_MASK);
83*4882a593Smuzhiyun 		if (ret != 0) {
84*4882a593Smuzhiyun 			dev_err(wm831x->dev, "Failed to start AUXADC: %d\n",
85*4882a593Smuzhiyun 				ret);
86*4882a593Smuzhiyun 			goto out;
87*4882a593Smuzhiyun 		}
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	mutex_unlock(&wm831x->auxadc_lock);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	/* Wait for an interrupt */
93*4882a593Smuzhiyun 	wait_for_completion_timeout(&req->done, msecs_to_jiffies(500));
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	mutex_lock(&wm831x->auxadc_lock);
96*4882a593Smuzhiyun 	ret = req->val;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun out:
99*4882a593Smuzhiyun 	list_del(&req->list);
100*4882a593Smuzhiyun 	mutex_unlock(&wm831x->auxadc_lock);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	kfree(req);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	return ret;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
wm831x_auxadc_irq(int irq,void * irq_data)107*4882a593Smuzhiyun static irqreturn_t wm831x_auxadc_irq(int irq, void *irq_data)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	struct wm831x *wm831x = irq_data;
110*4882a593Smuzhiyun 	struct wm831x_auxadc_req *req;
111*4882a593Smuzhiyun 	int ret, input, val;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
114*4882a593Smuzhiyun 	if (ret < 0) {
115*4882a593Smuzhiyun 		dev_err(wm831x->dev,
116*4882a593Smuzhiyun 			"Failed to read AUXADC data: %d\n", ret);
117*4882a593Smuzhiyun 		return IRQ_NONE;
118*4882a593Smuzhiyun 	}
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	input = ((ret & WM831X_AUX_DATA_SRC_MASK)
121*4882a593Smuzhiyun 		 >> WM831X_AUX_DATA_SRC_SHIFT) - 1;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (input == 14)
124*4882a593Smuzhiyun 		input = WM831X_AUX_CAL;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	val = ret & WM831X_AUX_DATA_MASK;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	mutex_lock(&wm831x->auxadc_lock);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/* Disable this conversion, we're about to complete all users */
131*4882a593Smuzhiyun 	wm831x_set_bits(wm831x, WM831X_AUXADC_SOURCE,
132*4882a593Smuzhiyun 			1 << input, 0);
133*4882a593Smuzhiyun 	wm831x->auxadc_active &= ~(1 << input);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* Turn off the entire convertor if idle */
136*4882a593Smuzhiyun 	if (!wm831x->auxadc_active)
137*4882a593Smuzhiyun 		wm831x_reg_write(wm831x, WM831X_AUXADC_CONTROL, 0);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	/* Wake up any threads waiting for this request */
140*4882a593Smuzhiyun 	list_for_each_entry(req, &wm831x->auxadc_pending, list) {
141*4882a593Smuzhiyun 		if (req->input == input) {
142*4882a593Smuzhiyun 			req->val = val;
143*4882a593Smuzhiyun 			complete(&req->done);
144*4882a593Smuzhiyun 		}
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	mutex_unlock(&wm831x->auxadc_lock);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	return IRQ_HANDLED;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
wm831x_auxadc_read_polled(struct wm831x * wm831x,enum wm831x_auxadc input)152*4882a593Smuzhiyun static int wm831x_auxadc_read_polled(struct wm831x *wm831x,
153*4882a593Smuzhiyun 				     enum wm831x_auxadc input)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	int ret, src, timeout;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	mutex_lock(&wm831x->auxadc_lock);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
160*4882a593Smuzhiyun 			      WM831X_AUX_ENA, WM831X_AUX_ENA);
161*4882a593Smuzhiyun 	if (ret < 0) {
162*4882a593Smuzhiyun 		dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n", ret);
163*4882a593Smuzhiyun 		goto out;
164*4882a593Smuzhiyun 	}
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	/* We force a single source at present */
167*4882a593Smuzhiyun 	src = input;
168*4882a593Smuzhiyun 	ret = wm831x_reg_write(wm831x, WM831X_AUXADC_SOURCE,
169*4882a593Smuzhiyun 			       1 << src);
170*4882a593Smuzhiyun 	if (ret < 0) {
171*4882a593Smuzhiyun 		dev_err(wm831x->dev, "Failed to set AUXADC source: %d\n", ret);
172*4882a593Smuzhiyun 		goto out;
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
176*4882a593Smuzhiyun 			      WM831X_AUX_CVT_ENA, WM831X_AUX_CVT_ENA);
177*4882a593Smuzhiyun 	if (ret < 0) {
178*4882a593Smuzhiyun 		dev_err(wm831x->dev, "Failed to start AUXADC: %d\n", ret);
179*4882a593Smuzhiyun 		goto disable;
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	/* If we're not using interrupts then poll the
183*4882a593Smuzhiyun 	 * interrupt status register */
184*4882a593Smuzhiyun 	timeout = 5;
185*4882a593Smuzhiyun 	while (timeout) {
186*4882a593Smuzhiyun 		msleep(1);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 		ret = wm831x_reg_read(wm831x,
189*4882a593Smuzhiyun 				      WM831X_INTERRUPT_STATUS_1);
190*4882a593Smuzhiyun 		if (ret < 0) {
191*4882a593Smuzhiyun 			dev_err(wm831x->dev,
192*4882a593Smuzhiyun 				"ISR 1 read failed: %d\n", ret);
193*4882a593Smuzhiyun 			goto disable;
194*4882a593Smuzhiyun 		}
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 		/* Did it complete? */
197*4882a593Smuzhiyun 		if (ret & WM831X_AUXADC_DATA_EINT) {
198*4882a593Smuzhiyun 			wm831x_reg_write(wm831x,
199*4882a593Smuzhiyun 					 WM831X_INTERRUPT_STATUS_1,
200*4882a593Smuzhiyun 					 WM831X_AUXADC_DATA_EINT);
201*4882a593Smuzhiyun 			break;
202*4882a593Smuzhiyun 		} else {
203*4882a593Smuzhiyun 			dev_err(wm831x->dev,
204*4882a593Smuzhiyun 				"AUXADC conversion timeout\n");
205*4882a593Smuzhiyun 			ret = -EBUSY;
206*4882a593Smuzhiyun 			goto disable;
207*4882a593Smuzhiyun 		}
208*4882a593Smuzhiyun 	}
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
211*4882a593Smuzhiyun 	if (ret < 0) {
212*4882a593Smuzhiyun 		dev_err(wm831x->dev,
213*4882a593Smuzhiyun 			"Failed to read AUXADC data: %d\n", ret);
214*4882a593Smuzhiyun 		goto disable;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	src = ((ret & WM831X_AUX_DATA_SRC_MASK)
218*4882a593Smuzhiyun 	       >> WM831X_AUX_DATA_SRC_SHIFT) - 1;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	if (src == 14)
221*4882a593Smuzhiyun 		src = WM831X_AUX_CAL;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	if (src != input) {
224*4882a593Smuzhiyun 		dev_err(wm831x->dev, "Data from source %d not %d\n",
225*4882a593Smuzhiyun 			src, input);
226*4882a593Smuzhiyun 		ret = -EINVAL;
227*4882a593Smuzhiyun 	} else {
228*4882a593Smuzhiyun 		ret &= WM831X_AUX_DATA_MASK;
229*4882a593Smuzhiyun 	}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun disable:
232*4882a593Smuzhiyun 	wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL, WM831X_AUX_ENA, 0);
233*4882a593Smuzhiyun out:
234*4882a593Smuzhiyun 	mutex_unlock(&wm831x->auxadc_lock);
235*4882a593Smuzhiyun 	return ret;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /**
239*4882a593Smuzhiyun  * wm831x_auxadc_read: Read a value from the WM831x AUXADC
240*4882a593Smuzhiyun  *
241*4882a593Smuzhiyun  * @wm831x: Device to read from.
242*4882a593Smuzhiyun  * @input: AUXADC input to read.
243*4882a593Smuzhiyun  */
wm831x_auxadc_read(struct wm831x * wm831x,enum wm831x_auxadc input)244*4882a593Smuzhiyun int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	return wm831x->auxadc_read(wm831x, input);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm831x_auxadc_read);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /**
251*4882a593Smuzhiyun  * wm831x_auxadc_read_uv: Read a voltage from the WM831x AUXADC
252*4882a593Smuzhiyun  *
253*4882a593Smuzhiyun  * @wm831x: Device to read from.
254*4882a593Smuzhiyun  * @input: AUXADC input to read.
255*4882a593Smuzhiyun  */
wm831x_auxadc_read_uv(struct wm831x * wm831x,enum wm831x_auxadc input)256*4882a593Smuzhiyun int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun 	int ret;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	ret = wm831x_auxadc_read(wm831x, input);
261*4882a593Smuzhiyun 	if (ret < 0)
262*4882a593Smuzhiyun 		return ret;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	ret *= 1465;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	return ret;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm831x_auxadc_read_uv);
269*4882a593Smuzhiyun 
wm831x_auxadc_init(struct wm831x * wm831x)270*4882a593Smuzhiyun void wm831x_auxadc_init(struct wm831x *wm831x)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun 	int ret;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	mutex_init(&wm831x->auxadc_lock);
275*4882a593Smuzhiyun 	INIT_LIST_HEAD(&wm831x->auxadc_pending);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (wm831x->irq) {
278*4882a593Smuzhiyun 		wm831x->auxadc_read = wm831x_auxadc_read_irq;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 		ret = request_threaded_irq(wm831x_irq(wm831x,
281*4882a593Smuzhiyun 						      WM831X_IRQ_AUXADC_DATA),
282*4882a593Smuzhiyun 					   NULL, wm831x_auxadc_irq,
283*4882a593Smuzhiyun 					   IRQF_ONESHOT,
284*4882a593Smuzhiyun 					   "auxadc", wm831x);
285*4882a593Smuzhiyun 		if (ret < 0) {
286*4882a593Smuzhiyun 			dev_err(wm831x->dev, "AUXADC IRQ request failed: %d\n",
287*4882a593Smuzhiyun 				ret);
288*4882a593Smuzhiyun 			wm831x->auxadc_read = NULL;
289*4882a593Smuzhiyun 		}
290*4882a593Smuzhiyun 	}
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	if (!wm831x->auxadc_read)
293*4882a593Smuzhiyun 		wm831x->auxadc_read = wm831x_auxadc_read_polled;
294*4882a593Smuzhiyun }
295