1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2019, Linaro Limited
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/clk.h>
5*4882a593Smuzhiyun #include <linux/gpio.h>
6*4882a593Smuzhiyun #include <linux/interrupt.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/mfd/core.h>
9*4882a593Smuzhiyun #include <linux/mfd/wcd934x/registers.h>
10*4882a593Smuzhiyun #include <linux/mfd/wcd934x/wcd934x.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_gpio.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_irq.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun #include <linux/slimbus.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static const struct mfd_cell wcd934x_devices[] = {
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun .name = "wcd934x-codec",
23*4882a593Smuzhiyun }, {
24*4882a593Smuzhiyun .name = "wcd934x-gpio",
25*4882a593Smuzhiyun .of_compatible = "qcom,wcd9340-gpio",
26*4882a593Smuzhiyun }, {
27*4882a593Smuzhiyun .name = "wcd934x-soundwire",
28*4882a593Smuzhiyun .of_compatible = "qcom,soundwire-v1.3.0",
29*4882a593Smuzhiyun },
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct regmap_irq wcd934x_irqs[] = {
33*4882a593Smuzhiyun [WCD934X_IRQ_SLIMBUS] = {
34*4882a593Smuzhiyun .reg_offset = 0,
35*4882a593Smuzhiyun .mask = BIT(0),
36*4882a593Smuzhiyun .type = {
37*4882a593Smuzhiyun .type_reg_offset = 0,
38*4882a593Smuzhiyun .types_supported = IRQ_TYPE_EDGE_BOTH,
39*4882a593Smuzhiyun .type_reg_mask = BIT(0),
40*4882a593Smuzhiyun .type_level_low_val = BIT(0),
41*4882a593Smuzhiyun .type_level_high_val = BIT(0),
42*4882a593Smuzhiyun .type_falling_val = 0,
43*4882a593Smuzhiyun .type_rising_val = 0,
44*4882a593Smuzhiyun },
45*4882a593Smuzhiyun },
46*4882a593Smuzhiyun [WCD934X_IRQ_SOUNDWIRE] = {
47*4882a593Smuzhiyun .reg_offset = 2,
48*4882a593Smuzhiyun .mask = BIT(4),
49*4882a593Smuzhiyun .type = {
50*4882a593Smuzhiyun .type_reg_offset = 2,
51*4882a593Smuzhiyun .types_supported = IRQ_TYPE_EDGE_BOTH,
52*4882a593Smuzhiyun .type_reg_mask = BIT(4),
53*4882a593Smuzhiyun .type_level_low_val = BIT(4),
54*4882a593Smuzhiyun .type_level_high_val = BIT(4),
55*4882a593Smuzhiyun .type_falling_val = 0,
56*4882a593Smuzhiyun .type_rising_val = 0,
57*4882a593Smuzhiyun },
58*4882a593Smuzhiyun },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct regmap_irq_chip wcd934x_regmap_irq_chip = {
62*4882a593Smuzhiyun .name = "wcd934x_irq",
63*4882a593Smuzhiyun .status_base = WCD934X_INTR_PIN1_STATUS0,
64*4882a593Smuzhiyun .mask_base = WCD934X_INTR_PIN1_MASK0,
65*4882a593Smuzhiyun .ack_base = WCD934X_INTR_PIN1_CLEAR0,
66*4882a593Smuzhiyun .type_base = WCD934X_INTR_LEVEL0,
67*4882a593Smuzhiyun .num_type_reg = 4,
68*4882a593Smuzhiyun .type_in_mask = false,
69*4882a593Smuzhiyun .num_regs = 4,
70*4882a593Smuzhiyun .irqs = wcd934x_irqs,
71*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(wcd934x_irqs),
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
wcd934x_is_volatile_register(struct device * dev,unsigned int reg)74*4882a593Smuzhiyun static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun switch (reg) {
77*4882a593Smuzhiyun case WCD934X_INTR_PIN1_STATUS0...WCD934X_INTR_PIN2_CLEAR3:
78*4882a593Smuzhiyun case WCD934X_SWR_AHB_BRIDGE_RD_DATA_0:
79*4882a593Smuzhiyun case WCD934X_SWR_AHB_BRIDGE_RD_DATA_1:
80*4882a593Smuzhiyun case WCD934X_SWR_AHB_BRIDGE_RD_DATA_2:
81*4882a593Smuzhiyun case WCD934X_SWR_AHB_BRIDGE_RD_DATA_3:
82*4882a593Smuzhiyun case WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS:
83*4882a593Smuzhiyun case WCD934X_ANA_MBHC_RESULT_3:
84*4882a593Smuzhiyun case WCD934X_ANA_MBHC_RESULT_2:
85*4882a593Smuzhiyun case WCD934X_ANA_MBHC_RESULT_1:
86*4882a593Smuzhiyun case WCD934X_ANA_MBHC_MECH:
87*4882a593Smuzhiyun case WCD934X_ANA_MBHC_ELECT:
88*4882a593Smuzhiyun case WCD934X_ANA_MBHC_ZDET:
89*4882a593Smuzhiyun case WCD934X_ANA_MICB2:
90*4882a593Smuzhiyun case WCD934X_ANA_RCO:
91*4882a593Smuzhiyun case WCD934X_ANA_BIAS:
92*4882a593Smuzhiyun return true;
93*4882a593Smuzhiyun default:
94*4882a593Smuzhiyun return false;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const struct regmap_range_cfg wcd934x_ranges[] = {
99*4882a593Smuzhiyun { .name = "WCD934X",
100*4882a593Smuzhiyun .range_min = 0x0,
101*4882a593Smuzhiyun .range_max = WCD934X_MAX_REGISTER,
102*4882a593Smuzhiyun .selector_reg = WCD934X_SEL_REGISTER,
103*4882a593Smuzhiyun .selector_mask = WCD934X_SEL_MASK,
104*4882a593Smuzhiyun .selector_shift = WCD934X_SEL_SHIFT,
105*4882a593Smuzhiyun .window_start = WCD934X_WINDOW_START,
106*4882a593Smuzhiyun .window_len = WCD934X_WINDOW_LENGTH,
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct regmap_config wcd934x_regmap_config = {
111*4882a593Smuzhiyun .reg_bits = 16,
112*4882a593Smuzhiyun .val_bits = 8,
113*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
114*4882a593Smuzhiyun .max_register = 0xffff,
115*4882a593Smuzhiyun .can_multi_write = true,
116*4882a593Smuzhiyun .ranges = wcd934x_ranges,
117*4882a593Smuzhiyun .num_ranges = ARRAY_SIZE(wcd934x_ranges),
118*4882a593Smuzhiyun .volatile_reg = wcd934x_is_volatile_register,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
wcd934x_bring_up(struct wcd934x_ddata * ddata)121*4882a593Smuzhiyun static int wcd934x_bring_up(struct wcd934x_ddata *ddata)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct regmap *regmap = ddata->regmap;
124*4882a593Smuzhiyun u16 id_minor, id_major;
125*4882a593Smuzhiyun int ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
128*4882a593Smuzhiyun (u8 *)&id_minor, sizeof(u16));
129*4882a593Smuzhiyun if (ret)
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2,
133*4882a593Smuzhiyun (u8 *)&id_major, sizeof(u16));
134*4882a593Smuzhiyun if (ret)
135*4882a593Smuzhiyun return ret;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun dev_info(ddata->dev, "WCD934x chip id major 0x%x, minor 0x%x\n",
138*4882a593Smuzhiyun id_major, id_minor);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun regmap_write(regmap, WCD934X_CODEC_RPM_RST_CTL, 0x01);
141*4882a593Smuzhiyun regmap_write(regmap, WCD934X_SIDO_NEW_VOUT_A_STARTUP, 0x19);
142*4882a593Smuzhiyun regmap_write(regmap, WCD934X_SIDO_NEW_VOUT_D_STARTUP, 0x15);
143*4882a593Smuzhiyun /* Add 1msec delay for VOUT to settle */
144*4882a593Smuzhiyun usleep_range(1000, 1100);
145*4882a593Smuzhiyun regmap_write(regmap, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
146*4882a593Smuzhiyun regmap_write(regmap, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
147*4882a593Smuzhiyun regmap_write(regmap, WCD934X_CODEC_RPM_RST_CTL, 0x3);
148*4882a593Smuzhiyun regmap_write(regmap, WCD934X_CODEC_RPM_RST_CTL, 0x7);
149*4882a593Smuzhiyun regmap_write(regmap, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun return 0;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
wcd934x_slim_status_up(struct slim_device * sdev)154*4882a593Smuzhiyun static int wcd934x_slim_status_up(struct slim_device *sdev)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun struct device *dev = &sdev->dev;
157*4882a593Smuzhiyun struct wcd934x_ddata *ddata;
158*4882a593Smuzhiyun int ret;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun ddata = dev_get_drvdata(dev);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ddata->regmap = regmap_init_slimbus(sdev, &wcd934x_regmap_config);
163*4882a593Smuzhiyun if (IS_ERR(ddata->regmap)) {
164*4882a593Smuzhiyun dev_err(dev, "Error allocating slim regmap\n");
165*4882a593Smuzhiyun return PTR_ERR(ddata->regmap);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun ret = wcd934x_bring_up(ddata);
169*4882a593Smuzhiyun if (ret) {
170*4882a593Smuzhiyun dev_err(dev, "Failed to bring up WCD934X: err = %d\n", ret);
171*4882a593Smuzhiyun return ret;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
175*4882a593Smuzhiyun IRQF_TRIGGER_HIGH, 0,
176*4882a593Smuzhiyun &wcd934x_regmap_irq_chip,
177*4882a593Smuzhiyun &ddata->irq_data);
178*4882a593Smuzhiyun if (ret) {
179*4882a593Smuzhiyun dev_err(dev, "Failed to add IRQ chip: err = %d\n", ret);
180*4882a593Smuzhiyun return ret;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, wcd934x_devices,
184*4882a593Smuzhiyun ARRAY_SIZE(wcd934x_devices), NULL, 0, NULL);
185*4882a593Smuzhiyun if (ret) {
186*4882a593Smuzhiyun dev_err(dev, "Failed to add child devices: err = %d\n",
187*4882a593Smuzhiyun ret);
188*4882a593Smuzhiyun return ret;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun return ret;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
wcd934x_slim_status(struct slim_device * sdev,enum slim_device_status status)194*4882a593Smuzhiyun static int wcd934x_slim_status(struct slim_device *sdev,
195*4882a593Smuzhiyun enum slim_device_status status)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun switch (status) {
198*4882a593Smuzhiyun case SLIM_DEVICE_STATUS_UP:
199*4882a593Smuzhiyun return wcd934x_slim_status_up(sdev);
200*4882a593Smuzhiyun case SLIM_DEVICE_STATUS_DOWN:
201*4882a593Smuzhiyun mfd_remove_devices(&sdev->dev);
202*4882a593Smuzhiyun break;
203*4882a593Smuzhiyun default:
204*4882a593Smuzhiyun return -EINVAL;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun return 0;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
wcd934x_slim_probe(struct slim_device * sdev)210*4882a593Smuzhiyun static int wcd934x_slim_probe(struct slim_device *sdev)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun struct device *dev = &sdev->dev;
213*4882a593Smuzhiyun struct device_node *np = dev->of_node;
214*4882a593Smuzhiyun struct wcd934x_ddata *ddata;
215*4882a593Smuzhiyun int reset_gpio, ret;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
218*4882a593Smuzhiyun if (!ddata)
219*4882a593Smuzhiyun return -ENOMEM;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun ddata->irq = of_irq_get(np, 0);
222*4882a593Smuzhiyun if (ddata->irq < 0)
223*4882a593Smuzhiyun return dev_err_probe(ddata->dev, ddata->irq,
224*4882a593Smuzhiyun "Failed to get IRQ\n");
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
227*4882a593Smuzhiyun if (reset_gpio < 0) {
228*4882a593Smuzhiyun dev_err(dev, "Failed to get reset gpio: err = %d\n",
229*4882a593Smuzhiyun reset_gpio);
230*4882a593Smuzhiyun return reset_gpio;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ddata->extclk = devm_clk_get(dev, "extclk");
234*4882a593Smuzhiyun if (IS_ERR(ddata->extclk)) {
235*4882a593Smuzhiyun dev_err(dev, "Failed to get extclk");
236*4882a593Smuzhiyun return PTR_ERR(ddata->extclk);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun ddata->supplies[0].supply = "vdd-buck";
240*4882a593Smuzhiyun ddata->supplies[1].supply = "vdd-buck-sido";
241*4882a593Smuzhiyun ddata->supplies[2].supply = "vdd-tx";
242*4882a593Smuzhiyun ddata->supplies[3].supply = "vdd-rx";
243*4882a593Smuzhiyun ddata->supplies[4].supply = "vdd-io";
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun ret = regulator_bulk_get(dev, WCD934X_MAX_SUPPLY, ddata->supplies);
246*4882a593Smuzhiyun if (ret) {
247*4882a593Smuzhiyun dev_err(dev, "Failed to get supplies: err = %d\n", ret);
248*4882a593Smuzhiyun return ret;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun ret = regulator_bulk_enable(WCD934X_MAX_SUPPLY, ddata->supplies);
252*4882a593Smuzhiyun if (ret) {
253*4882a593Smuzhiyun dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /*
258*4882a593Smuzhiyun * For WCD934X, it takes about 600us for the Vout_A and
259*4882a593Smuzhiyun * Vout_D to be ready after BUCK_SIDO is powered up.
260*4882a593Smuzhiyun * SYS_RST_N shouldn't be pulled high during this time
261*4882a593Smuzhiyun */
262*4882a593Smuzhiyun usleep_range(600, 650);
263*4882a593Smuzhiyun gpio_direction_output(reset_gpio, 0);
264*4882a593Smuzhiyun msleep(20);
265*4882a593Smuzhiyun gpio_set_value(reset_gpio, 1);
266*4882a593Smuzhiyun msleep(20);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun ddata->dev = dev;
269*4882a593Smuzhiyun dev_set_drvdata(dev, ddata);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return 0;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
wcd934x_slim_remove(struct slim_device * sdev)274*4882a593Smuzhiyun static void wcd934x_slim_remove(struct slim_device *sdev)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun struct wcd934x_ddata *ddata = dev_get_drvdata(&sdev->dev);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun regulator_bulk_disable(WCD934X_MAX_SUPPLY, ddata->supplies);
279*4882a593Smuzhiyun mfd_remove_devices(&sdev->dev);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun static const struct slim_device_id wcd934x_slim_id[] = {
283*4882a593Smuzhiyun { SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9340,
284*4882a593Smuzhiyun SLIM_DEV_IDX_WCD9340, SLIM_DEV_INSTANCE_ID_WCD9340 },
285*4882a593Smuzhiyun {}
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun static struct slim_driver wcd934x_slim_driver = {
289*4882a593Smuzhiyun .driver = {
290*4882a593Smuzhiyun .name = "wcd934x-slim",
291*4882a593Smuzhiyun },
292*4882a593Smuzhiyun .probe = wcd934x_slim_probe,
293*4882a593Smuzhiyun .remove = wcd934x_slim_remove,
294*4882a593Smuzhiyun .device_status = wcd934x_slim_status,
295*4882a593Smuzhiyun .id_table = wcd934x_slim_id,
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun module_slim_driver(wcd934x_slim_driver);
299*4882a593Smuzhiyun MODULE_DESCRIPTION("WCD934X slim driver");
300*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
301*4882a593Smuzhiyun MODULE_ALIAS("slim:217:250:*");
302*4882a593Smuzhiyun MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
303