xref: /OK3568_Linux_fs/kernel/drivers/mfd/twl6040.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * MFD driver for TWL6040 audio device
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Authors:	Misael Lopez Cruz <misael.lopez@ti.com>
6*4882a593Smuzhiyun  *		Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
7*4882a593Smuzhiyun  *		Peter Ujfalusi <peter.ujfalusi@ti.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright:	(C) 2011 Texas Instruments, Inc.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/types.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/of.h>
19*4882a593Smuzhiyun #include <linux/of_irq.h>
20*4882a593Smuzhiyun #include <linux/of_gpio.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun #include <linux/gpio.h>
23*4882a593Smuzhiyun #include <linux/delay.h>
24*4882a593Smuzhiyun #include <linux/i2c.h>
25*4882a593Smuzhiyun #include <linux/regmap.h>
26*4882a593Smuzhiyun #include <linux/mfd/core.h>
27*4882a593Smuzhiyun #include <linux/mfd/twl6040.h>
28*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
31*4882a593Smuzhiyun #define TWL6040_NUM_SUPPLIES	(2)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun static const struct reg_default twl6040_defaults[] = {
34*4882a593Smuzhiyun 	{ 0x01, 0x4B }, /* REG_ASICID	(ro) */
35*4882a593Smuzhiyun 	{ 0x02, 0x00 }, /* REG_ASICREV	(ro) */
36*4882a593Smuzhiyun 	{ 0x03, 0x00 }, /* REG_INTID	*/
37*4882a593Smuzhiyun 	{ 0x04, 0x00 }, /* REG_INTMR	*/
38*4882a593Smuzhiyun 	{ 0x05, 0x00 }, /* REG_NCPCTRL	*/
39*4882a593Smuzhiyun 	{ 0x06, 0x00 }, /* REG_LDOCTL	*/
40*4882a593Smuzhiyun 	{ 0x07, 0x60 }, /* REG_HPPLLCTL	*/
41*4882a593Smuzhiyun 	{ 0x08, 0x00 }, /* REG_LPPLLCTL	*/
42*4882a593Smuzhiyun 	{ 0x09, 0x4A }, /* REG_LPPLLDIV	*/
43*4882a593Smuzhiyun 	{ 0x0A, 0x00 }, /* REG_AMICBCTL	*/
44*4882a593Smuzhiyun 	{ 0x0B, 0x00 }, /* REG_DMICBCTL	*/
45*4882a593Smuzhiyun 	{ 0x0C, 0x00 }, /* REG_MICLCTL	*/
46*4882a593Smuzhiyun 	{ 0x0D, 0x00 }, /* REG_MICRCTL	*/
47*4882a593Smuzhiyun 	{ 0x0E, 0x00 }, /* REG_MICGAIN	*/
48*4882a593Smuzhiyun 	{ 0x0F, 0x1B }, /* REG_LINEGAIN	*/
49*4882a593Smuzhiyun 	{ 0x10, 0x00 }, /* REG_HSLCTL	*/
50*4882a593Smuzhiyun 	{ 0x11, 0x00 }, /* REG_HSRCTL	*/
51*4882a593Smuzhiyun 	{ 0x12, 0x00 }, /* REG_HSGAIN	*/
52*4882a593Smuzhiyun 	{ 0x13, 0x00 }, /* REG_EARCTL	*/
53*4882a593Smuzhiyun 	{ 0x14, 0x00 }, /* REG_HFLCTL	*/
54*4882a593Smuzhiyun 	{ 0x15, 0x00 }, /* REG_HFLGAIN	*/
55*4882a593Smuzhiyun 	{ 0x16, 0x00 }, /* REG_HFRCTL	*/
56*4882a593Smuzhiyun 	{ 0x17, 0x00 }, /* REG_HFRGAIN	*/
57*4882a593Smuzhiyun 	{ 0x18, 0x00 }, /* REG_VIBCTLL	*/
58*4882a593Smuzhiyun 	{ 0x19, 0x00 }, /* REG_VIBDATL	*/
59*4882a593Smuzhiyun 	{ 0x1A, 0x00 }, /* REG_VIBCTLR	*/
60*4882a593Smuzhiyun 	{ 0x1B, 0x00 }, /* REG_VIBDATR	*/
61*4882a593Smuzhiyun 	{ 0x1C, 0x00 }, /* REG_HKCTL1	*/
62*4882a593Smuzhiyun 	{ 0x1D, 0x00 }, /* REG_HKCTL2	*/
63*4882a593Smuzhiyun 	{ 0x1E, 0x00 }, /* REG_GPOCTL	*/
64*4882a593Smuzhiyun 	{ 0x1F, 0x00 }, /* REG_ALB	*/
65*4882a593Smuzhiyun 	{ 0x20, 0x00 }, /* REG_DLB	*/
66*4882a593Smuzhiyun 	/* 0x28, REG_TRIM1 */
67*4882a593Smuzhiyun 	/* 0x29, REG_TRIM2 */
68*4882a593Smuzhiyun 	/* 0x2A, REG_TRIM3 */
69*4882a593Smuzhiyun 	/* 0x2B, REG_HSOTRIM */
70*4882a593Smuzhiyun 	/* 0x2C, REG_HFOTRIM */
71*4882a593Smuzhiyun 	{ 0x2D, 0x08 }, /* REG_ACCCTL	*/
72*4882a593Smuzhiyun 	{ 0x2E, 0x00 }, /* REG_STATUS	(ro) */
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun static struct reg_sequence twl6040_patch[] = {
76*4882a593Smuzhiyun 	/*
77*4882a593Smuzhiyun 	 * Select I2C bus access to dual access registers
78*4882a593Smuzhiyun 	 * Interrupt register is cleared on read
79*4882a593Smuzhiyun 	 * Select fast mode for i2c (400KHz)
80*4882a593Smuzhiyun 	 */
81*4882a593Smuzhiyun 	{ TWL6040_REG_ACCCTL,
82*4882a593Smuzhiyun 		TWL6040_I2CSEL | TWL6040_INTCLRMODE | TWL6040_I2CMODE(1) },
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 
twl6040_has_vibra(struct device_node * parent)86*4882a593Smuzhiyun static bool twl6040_has_vibra(struct device_node *parent)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	struct device_node *node;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	node = of_get_child_by_name(parent, "vibra");
91*4882a593Smuzhiyun 	if (node) {
92*4882a593Smuzhiyun 		of_node_put(node);
93*4882a593Smuzhiyun 		return true;
94*4882a593Smuzhiyun 	}
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return false;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
twl6040_reg_read(struct twl6040 * twl6040,unsigned int reg)99*4882a593Smuzhiyun int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	int ret;
102*4882a593Smuzhiyun 	unsigned int val;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = regmap_read(twl6040->regmap, reg, &val);
105*4882a593Smuzhiyun 	if (ret < 0)
106*4882a593Smuzhiyun 		return ret;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	return val;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_reg_read);
111*4882a593Smuzhiyun 
twl6040_reg_write(struct twl6040 * twl6040,unsigned int reg,u8 val)112*4882a593Smuzhiyun int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	int ret;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	ret = regmap_write(twl6040->regmap, reg, val);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_reg_write);
121*4882a593Smuzhiyun 
twl6040_set_bits(struct twl6040 * twl6040,unsigned int reg,u8 mask)122*4882a593Smuzhiyun int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	return regmap_update_bits(twl6040->regmap, reg, mask, mask);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_set_bits);
127*4882a593Smuzhiyun 
twl6040_clear_bits(struct twl6040 * twl6040,unsigned int reg,u8 mask)128*4882a593Smuzhiyun int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	return regmap_update_bits(twl6040->regmap, reg, mask, 0);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_clear_bits);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /* twl6040 codec manual power-up sequence */
twl6040_power_up_manual(struct twl6040 * twl6040)135*4882a593Smuzhiyun static int twl6040_power_up_manual(struct twl6040 *twl6040)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	u8 ldoctl, ncpctl, lppllctl;
138*4882a593Smuzhiyun 	int ret;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	/* enable high-side LDO, reference system and internal oscillator */
141*4882a593Smuzhiyun 	ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
142*4882a593Smuzhiyun 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
143*4882a593Smuzhiyun 	if (ret)
144*4882a593Smuzhiyun 		return ret;
145*4882a593Smuzhiyun 	usleep_range(10000, 10500);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/* enable negative charge pump */
148*4882a593Smuzhiyun 	ncpctl = TWL6040_NCPENA;
149*4882a593Smuzhiyun 	ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
150*4882a593Smuzhiyun 	if (ret)
151*4882a593Smuzhiyun 		goto ncp_err;
152*4882a593Smuzhiyun 	usleep_range(1000, 1500);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* enable low-side LDO */
155*4882a593Smuzhiyun 	ldoctl |= TWL6040_LSLDOENA;
156*4882a593Smuzhiyun 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
157*4882a593Smuzhiyun 	if (ret)
158*4882a593Smuzhiyun 		goto lsldo_err;
159*4882a593Smuzhiyun 	usleep_range(1000, 1500);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* enable low-power PLL */
162*4882a593Smuzhiyun 	lppllctl = TWL6040_LPLLENA;
163*4882a593Smuzhiyun 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
164*4882a593Smuzhiyun 	if (ret)
165*4882a593Smuzhiyun 		goto lppll_err;
166*4882a593Smuzhiyun 	usleep_range(5000, 5500);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/* disable internal oscillator */
169*4882a593Smuzhiyun 	ldoctl &= ~TWL6040_OSCENA;
170*4882a593Smuzhiyun 	ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
171*4882a593Smuzhiyun 	if (ret)
172*4882a593Smuzhiyun 		goto osc_err;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	return 0;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun osc_err:
177*4882a593Smuzhiyun 	lppllctl &= ~TWL6040_LPLLENA;
178*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
179*4882a593Smuzhiyun lppll_err:
180*4882a593Smuzhiyun 	ldoctl &= ~TWL6040_LSLDOENA;
181*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
182*4882a593Smuzhiyun lsldo_err:
183*4882a593Smuzhiyun 	ncpctl &= ~TWL6040_NCPENA;
184*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
185*4882a593Smuzhiyun ncp_err:
186*4882a593Smuzhiyun 	ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
187*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	dev_err(twl6040->dev, "manual power-up failed\n");
190*4882a593Smuzhiyun 	return ret;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun /* twl6040 manual power-down sequence */
twl6040_power_down_manual(struct twl6040 * twl6040)194*4882a593Smuzhiyun static void twl6040_power_down_manual(struct twl6040 *twl6040)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	u8 ncpctl, ldoctl, lppllctl;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
199*4882a593Smuzhiyun 	ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
200*4882a593Smuzhiyun 	lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	/* enable internal oscillator */
203*4882a593Smuzhiyun 	ldoctl |= TWL6040_OSCENA;
204*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
205*4882a593Smuzhiyun 	usleep_range(1000, 1500);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* disable low-power PLL */
208*4882a593Smuzhiyun 	lppllctl &= ~TWL6040_LPLLENA;
209*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	/* disable low-side LDO */
212*4882a593Smuzhiyun 	ldoctl &= ~TWL6040_LSLDOENA;
213*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	/* disable negative charge pump */
216*4882a593Smuzhiyun 	ncpctl &= ~TWL6040_NCPENA;
217*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	/* disable high-side LDO, reference system and internal oscillator */
220*4882a593Smuzhiyun 	ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
221*4882a593Smuzhiyun 	twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
twl6040_readyint_handler(int irq,void * data)224*4882a593Smuzhiyun static irqreturn_t twl6040_readyint_handler(int irq, void *data)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun 	struct twl6040 *twl6040 = data;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	complete(&twl6040->ready);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	return IRQ_HANDLED;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
twl6040_thint_handler(int irq,void * data)233*4882a593Smuzhiyun static irqreturn_t twl6040_thint_handler(int irq, void *data)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	struct twl6040 *twl6040 = data;
236*4882a593Smuzhiyun 	u8 status;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
239*4882a593Smuzhiyun 	if (status & TWL6040_TSHUTDET) {
240*4882a593Smuzhiyun 		dev_warn(twl6040->dev, "Thermal shutdown, powering-off");
241*4882a593Smuzhiyun 		twl6040_power(twl6040, 0);
242*4882a593Smuzhiyun 	} else {
243*4882a593Smuzhiyun 		dev_warn(twl6040->dev, "Leaving thermal shutdown, powering-on");
244*4882a593Smuzhiyun 		twl6040_power(twl6040, 1);
245*4882a593Smuzhiyun 	}
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return IRQ_HANDLED;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
twl6040_power_up_automatic(struct twl6040 * twl6040)250*4882a593Smuzhiyun static int twl6040_power_up_automatic(struct twl6040 *twl6040)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	int time_left;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	gpio_set_value(twl6040->audpwron, 1);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	time_left = wait_for_completion_timeout(&twl6040->ready,
257*4882a593Smuzhiyun 						msecs_to_jiffies(144));
258*4882a593Smuzhiyun 	if (!time_left) {
259*4882a593Smuzhiyun 		u8 intid;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 		dev_warn(twl6040->dev, "timeout waiting for READYINT\n");
262*4882a593Smuzhiyun 		intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
263*4882a593Smuzhiyun 		if (!(intid & TWL6040_READYINT)) {
264*4882a593Smuzhiyun 			dev_err(twl6040->dev, "automatic power-up failed\n");
265*4882a593Smuzhiyun 			gpio_set_value(twl6040->audpwron, 0);
266*4882a593Smuzhiyun 			return -ETIMEDOUT;
267*4882a593Smuzhiyun 		}
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	return 0;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun 
twl6040_power(struct twl6040 * twl6040,int on)273*4882a593Smuzhiyun int twl6040_power(struct twl6040 *twl6040, int on)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	int ret = 0;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	mutex_lock(&twl6040->mutex);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	if (on) {
280*4882a593Smuzhiyun 		/* already powered-up */
281*4882a593Smuzhiyun 		if (twl6040->power_count++)
282*4882a593Smuzhiyun 			goto out;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 		ret = clk_prepare_enable(twl6040->clk32k);
285*4882a593Smuzhiyun 		if (ret) {
286*4882a593Smuzhiyun 			twl6040->power_count = 0;
287*4882a593Smuzhiyun 			goto out;
288*4882a593Smuzhiyun 		}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 		/* Allow writes to the chip */
291*4882a593Smuzhiyun 		regcache_cache_only(twl6040->regmap, false);
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 		if (gpio_is_valid(twl6040->audpwron)) {
294*4882a593Smuzhiyun 			/* use automatic power-up sequence */
295*4882a593Smuzhiyun 			ret = twl6040_power_up_automatic(twl6040);
296*4882a593Smuzhiyun 			if (ret) {
297*4882a593Smuzhiyun 				clk_disable_unprepare(twl6040->clk32k);
298*4882a593Smuzhiyun 				twl6040->power_count = 0;
299*4882a593Smuzhiyun 				goto out;
300*4882a593Smuzhiyun 			}
301*4882a593Smuzhiyun 		} else {
302*4882a593Smuzhiyun 			/* use manual power-up sequence */
303*4882a593Smuzhiyun 			ret = twl6040_power_up_manual(twl6040);
304*4882a593Smuzhiyun 			if (ret) {
305*4882a593Smuzhiyun 				clk_disable_unprepare(twl6040->clk32k);
306*4882a593Smuzhiyun 				twl6040->power_count = 0;
307*4882a593Smuzhiyun 				goto out;
308*4882a593Smuzhiyun 			}
309*4882a593Smuzhiyun 		}
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 		/*
312*4882a593Smuzhiyun 		 * Register access can produce errors after power-up unless we
313*4882a593Smuzhiyun 		 * wait at least 8ms based on measurements on duovero.
314*4882a593Smuzhiyun 		 */
315*4882a593Smuzhiyun 		usleep_range(10000, 12000);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 		/* Sync with the HW */
318*4882a593Smuzhiyun 		ret = regcache_sync(twl6040->regmap);
319*4882a593Smuzhiyun 		if (ret) {
320*4882a593Smuzhiyun 			dev_err(twl6040->dev, "Failed to sync with the HW: %i\n",
321*4882a593Smuzhiyun 				ret);
322*4882a593Smuzhiyun 			goto out;
323*4882a593Smuzhiyun 		}
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 		/* Default PLL configuration after power up */
326*4882a593Smuzhiyun 		twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
327*4882a593Smuzhiyun 		twl6040->sysclk_rate = 19200000;
328*4882a593Smuzhiyun 	} else {
329*4882a593Smuzhiyun 		/* already powered-down */
330*4882a593Smuzhiyun 		if (!twl6040->power_count) {
331*4882a593Smuzhiyun 			dev_err(twl6040->dev,
332*4882a593Smuzhiyun 				"device is already powered-off\n");
333*4882a593Smuzhiyun 			ret = -EPERM;
334*4882a593Smuzhiyun 			goto out;
335*4882a593Smuzhiyun 		}
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 		if (--twl6040->power_count)
338*4882a593Smuzhiyun 			goto out;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 		if (gpio_is_valid(twl6040->audpwron)) {
341*4882a593Smuzhiyun 			/* use AUDPWRON line */
342*4882a593Smuzhiyun 			gpio_set_value(twl6040->audpwron, 0);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 			/* power-down sequence latency */
345*4882a593Smuzhiyun 			usleep_range(500, 700);
346*4882a593Smuzhiyun 		} else {
347*4882a593Smuzhiyun 			/* use manual power-down sequence */
348*4882a593Smuzhiyun 			twl6040_power_down_manual(twl6040);
349*4882a593Smuzhiyun 		}
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 		/* Set regmap to cache only and mark it as dirty */
352*4882a593Smuzhiyun 		regcache_cache_only(twl6040->regmap, true);
353*4882a593Smuzhiyun 		regcache_mark_dirty(twl6040->regmap);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 		twl6040->sysclk_rate = 0;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 		if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) {
358*4882a593Smuzhiyun 			clk_disable_unprepare(twl6040->mclk);
359*4882a593Smuzhiyun 			twl6040->mclk_rate = 0;
360*4882a593Smuzhiyun 		}
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 		clk_disable_unprepare(twl6040->clk32k);
363*4882a593Smuzhiyun 	}
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun out:
366*4882a593Smuzhiyun 	mutex_unlock(&twl6040->mutex);
367*4882a593Smuzhiyun 	return ret;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_power);
370*4882a593Smuzhiyun 
twl6040_set_pll(struct twl6040 * twl6040,int pll_id,unsigned int freq_in,unsigned int freq_out)371*4882a593Smuzhiyun int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
372*4882a593Smuzhiyun 		    unsigned int freq_in, unsigned int freq_out)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun 	u8 hppllctl, lppllctl;
375*4882a593Smuzhiyun 	int ret = 0;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	mutex_lock(&twl6040->mutex);
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
380*4882a593Smuzhiyun 	lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	/* Force full reconfiguration when switching between PLL */
383*4882a593Smuzhiyun 	if (pll_id != twl6040->pll) {
384*4882a593Smuzhiyun 		twl6040->sysclk_rate = 0;
385*4882a593Smuzhiyun 		twl6040->mclk_rate = 0;
386*4882a593Smuzhiyun 	}
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	switch (pll_id) {
389*4882a593Smuzhiyun 	case TWL6040_SYSCLK_SEL_LPPLL:
390*4882a593Smuzhiyun 		/* low-power PLL divider */
391*4882a593Smuzhiyun 		/* Change the sysclk configuration only if it has been canged */
392*4882a593Smuzhiyun 		if (twl6040->sysclk_rate != freq_out) {
393*4882a593Smuzhiyun 			switch (freq_out) {
394*4882a593Smuzhiyun 			case 17640000:
395*4882a593Smuzhiyun 				lppllctl |= TWL6040_LPLLFIN;
396*4882a593Smuzhiyun 				break;
397*4882a593Smuzhiyun 			case 19200000:
398*4882a593Smuzhiyun 				lppllctl &= ~TWL6040_LPLLFIN;
399*4882a593Smuzhiyun 				break;
400*4882a593Smuzhiyun 			default:
401*4882a593Smuzhiyun 				dev_err(twl6040->dev,
402*4882a593Smuzhiyun 					"freq_out %d not supported\n",
403*4882a593Smuzhiyun 					freq_out);
404*4882a593Smuzhiyun 				ret = -EINVAL;
405*4882a593Smuzhiyun 				goto pll_out;
406*4882a593Smuzhiyun 			}
407*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
408*4882a593Smuzhiyun 					  lppllctl);
409*4882a593Smuzhiyun 		}
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 		/* The PLL in use has not been change, we can exit */
412*4882a593Smuzhiyun 		if (twl6040->pll == pll_id)
413*4882a593Smuzhiyun 			break;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 		switch (freq_in) {
416*4882a593Smuzhiyun 		case 32768:
417*4882a593Smuzhiyun 			lppllctl |= TWL6040_LPLLENA;
418*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
419*4882a593Smuzhiyun 					  lppllctl);
420*4882a593Smuzhiyun 			mdelay(5);
421*4882a593Smuzhiyun 			lppllctl &= ~TWL6040_HPLLSEL;
422*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
423*4882a593Smuzhiyun 					  lppllctl);
424*4882a593Smuzhiyun 			hppllctl &= ~TWL6040_HPLLENA;
425*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
426*4882a593Smuzhiyun 					  hppllctl);
427*4882a593Smuzhiyun 			break;
428*4882a593Smuzhiyun 		default:
429*4882a593Smuzhiyun 			dev_err(twl6040->dev,
430*4882a593Smuzhiyun 				"freq_in %d not supported\n", freq_in);
431*4882a593Smuzhiyun 			ret = -EINVAL;
432*4882a593Smuzhiyun 			goto pll_out;
433*4882a593Smuzhiyun 		}
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 		clk_disable_unprepare(twl6040->mclk);
436*4882a593Smuzhiyun 		break;
437*4882a593Smuzhiyun 	case TWL6040_SYSCLK_SEL_HPPLL:
438*4882a593Smuzhiyun 		/* high-performance PLL can provide only 19.2 MHz */
439*4882a593Smuzhiyun 		if (freq_out != 19200000) {
440*4882a593Smuzhiyun 			dev_err(twl6040->dev,
441*4882a593Smuzhiyun 				"freq_out %d not supported\n", freq_out);
442*4882a593Smuzhiyun 			ret = -EINVAL;
443*4882a593Smuzhiyun 			goto pll_out;
444*4882a593Smuzhiyun 		}
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 		if (twl6040->mclk_rate != freq_in) {
447*4882a593Smuzhiyun 			hppllctl &= ~TWL6040_MCLK_MSK;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 			switch (freq_in) {
450*4882a593Smuzhiyun 			case 12000000:
451*4882a593Smuzhiyun 				/* PLL enabled, active mode */
452*4882a593Smuzhiyun 				hppllctl |= TWL6040_MCLK_12000KHZ |
453*4882a593Smuzhiyun 					    TWL6040_HPLLENA;
454*4882a593Smuzhiyun 				break;
455*4882a593Smuzhiyun 			case 19200000:
456*4882a593Smuzhiyun 				/* PLL enabled, bypass mode */
457*4882a593Smuzhiyun 				hppllctl |= TWL6040_MCLK_19200KHZ |
458*4882a593Smuzhiyun 					    TWL6040_HPLLBP | TWL6040_HPLLENA;
459*4882a593Smuzhiyun 				break;
460*4882a593Smuzhiyun 			case 26000000:
461*4882a593Smuzhiyun 				/* PLL enabled, active mode */
462*4882a593Smuzhiyun 				hppllctl |= TWL6040_MCLK_26000KHZ |
463*4882a593Smuzhiyun 					    TWL6040_HPLLENA;
464*4882a593Smuzhiyun 				break;
465*4882a593Smuzhiyun 			case 38400000:
466*4882a593Smuzhiyun 				/* PLL enabled, bypass mode */
467*4882a593Smuzhiyun 				hppllctl |= TWL6040_MCLK_38400KHZ |
468*4882a593Smuzhiyun 					    TWL6040_HPLLBP | TWL6040_HPLLENA;
469*4882a593Smuzhiyun 				break;
470*4882a593Smuzhiyun 			default:
471*4882a593Smuzhiyun 				dev_err(twl6040->dev,
472*4882a593Smuzhiyun 					"freq_in %d not supported\n", freq_in);
473*4882a593Smuzhiyun 				ret = -EINVAL;
474*4882a593Smuzhiyun 				goto pll_out;
475*4882a593Smuzhiyun 			}
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 			/* When switching to HPPLL, enable the mclk first */
478*4882a593Smuzhiyun 			if (pll_id != twl6040->pll)
479*4882a593Smuzhiyun 				clk_prepare_enable(twl6040->mclk);
480*4882a593Smuzhiyun 			/*
481*4882a593Smuzhiyun 			 * enable clock slicer to ensure input waveform is
482*4882a593Smuzhiyun 			 * square
483*4882a593Smuzhiyun 			 */
484*4882a593Smuzhiyun 			hppllctl |= TWL6040_HPLLSQRENA;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
487*4882a593Smuzhiyun 					  hppllctl);
488*4882a593Smuzhiyun 			usleep_range(500, 700);
489*4882a593Smuzhiyun 			lppllctl |= TWL6040_HPLLSEL;
490*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
491*4882a593Smuzhiyun 					  lppllctl);
492*4882a593Smuzhiyun 			lppllctl &= ~TWL6040_LPLLENA;
493*4882a593Smuzhiyun 			twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
494*4882a593Smuzhiyun 					  lppllctl);
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 			twl6040->mclk_rate = freq_in;
497*4882a593Smuzhiyun 		}
498*4882a593Smuzhiyun 		break;
499*4882a593Smuzhiyun 	default:
500*4882a593Smuzhiyun 		dev_err(twl6040->dev, "unknown pll id %d\n", pll_id);
501*4882a593Smuzhiyun 		ret = -EINVAL;
502*4882a593Smuzhiyun 		goto pll_out;
503*4882a593Smuzhiyun 	}
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	twl6040->sysclk_rate = freq_out;
506*4882a593Smuzhiyun 	twl6040->pll = pll_id;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun pll_out:
509*4882a593Smuzhiyun 	mutex_unlock(&twl6040->mutex);
510*4882a593Smuzhiyun 	return ret;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_set_pll);
513*4882a593Smuzhiyun 
twl6040_get_pll(struct twl6040 * twl6040)514*4882a593Smuzhiyun int twl6040_get_pll(struct twl6040 *twl6040)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun 	if (twl6040->power_count)
517*4882a593Smuzhiyun 		return twl6040->pll;
518*4882a593Smuzhiyun 	else
519*4882a593Smuzhiyun 		return -ENODEV;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_get_pll);
522*4882a593Smuzhiyun 
twl6040_get_sysclk(struct twl6040 * twl6040)523*4882a593Smuzhiyun unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun 	return twl6040->sysclk_rate;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_get_sysclk);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun /* Get the combined status of the vibra control register */
twl6040_get_vibralr_status(struct twl6040 * twl6040)530*4882a593Smuzhiyun int twl6040_get_vibralr_status(struct twl6040 *twl6040)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun 	unsigned int reg;
533*4882a593Smuzhiyun 	int ret;
534*4882a593Smuzhiyun 	u8 status;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLL, &reg);
537*4882a593Smuzhiyun 	if (ret != 0)
538*4882a593Smuzhiyun 		return ret;
539*4882a593Smuzhiyun 	status = reg;
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLR, &reg);
542*4882a593Smuzhiyun 	if (ret != 0)
543*4882a593Smuzhiyun 		return ret;
544*4882a593Smuzhiyun 	status |= reg;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	status &= (TWL6040_VIBENA | TWL6040_VIBSEL);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	return status;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun EXPORT_SYMBOL(twl6040_get_vibralr_status);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun static struct resource twl6040_vibra_rsrc[] = {
553*4882a593Smuzhiyun 	{
554*4882a593Smuzhiyun 		.flags = IORESOURCE_IRQ,
555*4882a593Smuzhiyun 	},
556*4882a593Smuzhiyun };
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun static struct resource twl6040_codec_rsrc[] = {
559*4882a593Smuzhiyun 	{
560*4882a593Smuzhiyun 		.flags = IORESOURCE_IRQ,
561*4882a593Smuzhiyun 	},
562*4882a593Smuzhiyun };
563*4882a593Smuzhiyun 
twl6040_readable_reg(struct device * dev,unsigned int reg)564*4882a593Smuzhiyun static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun 	/* Register 0 is not readable */
567*4882a593Smuzhiyun 	if (!reg)
568*4882a593Smuzhiyun 		return false;
569*4882a593Smuzhiyun 	return true;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun 
twl6040_volatile_reg(struct device * dev,unsigned int reg)572*4882a593Smuzhiyun static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun 	switch (reg) {
575*4882a593Smuzhiyun 	case TWL6040_REG_ASICID:
576*4882a593Smuzhiyun 	case TWL6040_REG_ASICREV:
577*4882a593Smuzhiyun 	case TWL6040_REG_INTID:
578*4882a593Smuzhiyun 	case TWL6040_REG_LPPLLCTL:
579*4882a593Smuzhiyun 	case TWL6040_REG_HPPLLCTL:
580*4882a593Smuzhiyun 	case TWL6040_REG_STATUS:
581*4882a593Smuzhiyun 		return true;
582*4882a593Smuzhiyun 	default:
583*4882a593Smuzhiyun 		return false;
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun 
twl6040_writeable_reg(struct device * dev,unsigned int reg)587*4882a593Smuzhiyun static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	switch (reg) {
590*4882a593Smuzhiyun 	case TWL6040_REG_ASICID:
591*4882a593Smuzhiyun 	case TWL6040_REG_ASICREV:
592*4882a593Smuzhiyun 	case TWL6040_REG_STATUS:
593*4882a593Smuzhiyun 		return false;
594*4882a593Smuzhiyun 	default:
595*4882a593Smuzhiyun 		return true;
596*4882a593Smuzhiyun 	}
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun static const struct regmap_config twl6040_regmap_config = {
600*4882a593Smuzhiyun 	.reg_bits = 8,
601*4882a593Smuzhiyun 	.val_bits = 8,
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	.reg_defaults = twl6040_defaults,
604*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	.max_register = TWL6040_REG_STATUS, /* 0x2e */
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	.readable_reg = twl6040_readable_reg,
609*4882a593Smuzhiyun 	.volatile_reg = twl6040_volatile_reg,
610*4882a593Smuzhiyun 	.writeable_reg = twl6040_writeable_reg,
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
613*4882a593Smuzhiyun 	.use_single_read = true,
614*4882a593Smuzhiyun 	.use_single_write = true,
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun static const struct regmap_irq twl6040_irqs[] = {
618*4882a593Smuzhiyun 	{ .reg_offset = 0, .mask = TWL6040_THINT, },
619*4882a593Smuzhiyun 	{ .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
620*4882a593Smuzhiyun 	{ .reg_offset = 0, .mask = TWL6040_HOOKINT, },
621*4882a593Smuzhiyun 	{ .reg_offset = 0, .mask = TWL6040_HFINT, },
622*4882a593Smuzhiyun 	{ .reg_offset = 0, .mask = TWL6040_VIBINT, },
623*4882a593Smuzhiyun 	{ .reg_offset = 0, .mask = TWL6040_READYINT, },
624*4882a593Smuzhiyun };
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun static struct regmap_irq_chip twl6040_irq_chip = {
627*4882a593Smuzhiyun 	.name = "twl6040",
628*4882a593Smuzhiyun 	.irqs = twl6040_irqs,
629*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(twl6040_irqs),
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	.num_regs = 1,
632*4882a593Smuzhiyun 	.status_base = TWL6040_REG_INTID,
633*4882a593Smuzhiyun 	.mask_base = TWL6040_REG_INTMR,
634*4882a593Smuzhiyun };
635*4882a593Smuzhiyun 
twl6040_probe(struct i2c_client * client,const struct i2c_device_id * id)636*4882a593Smuzhiyun static int twl6040_probe(struct i2c_client *client,
637*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun 	struct device_node *node = client->dev.of_node;
640*4882a593Smuzhiyun 	struct twl6040 *twl6040;
641*4882a593Smuzhiyun 	struct mfd_cell *cell = NULL;
642*4882a593Smuzhiyun 	int irq, ret, children = 0;
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	if (!node) {
645*4882a593Smuzhiyun 		dev_err(&client->dev, "of node is missing\n");
646*4882a593Smuzhiyun 		return -EINVAL;
647*4882a593Smuzhiyun 	}
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	/* In order to operate correctly we need valid interrupt config */
650*4882a593Smuzhiyun 	if (!client->irq) {
651*4882a593Smuzhiyun 		dev_err(&client->dev, "Invalid IRQ configuration\n");
652*4882a593Smuzhiyun 		return -EINVAL;
653*4882a593Smuzhiyun 	}
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
656*4882a593Smuzhiyun 			       GFP_KERNEL);
657*4882a593Smuzhiyun 	if (!twl6040)
658*4882a593Smuzhiyun 		return -ENOMEM;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	twl6040->regmap = devm_regmap_init_i2c(client, &twl6040_regmap_config);
661*4882a593Smuzhiyun 	if (IS_ERR(twl6040->regmap))
662*4882a593Smuzhiyun 		return PTR_ERR(twl6040->regmap);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	i2c_set_clientdata(client, twl6040);
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
667*4882a593Smuzhiyun 	if (IS_ERR(twl6040->clk32k)) {
668*4882a593Smuzhiyun 		if (PTR_ERR(twl6040->clk32k) == -EPROBE_DEFER)
669*4882a593Smuzhiyun 			return -EPROBE_DEFER;
670*4882a593Smuzhiyun 		dev_dbg(&client->dev, "clk32k is not handled\n");
671*4882a593Smuzhiyun 		twl6040->clk32k = NULL;
672*4882a593Smuzhiyun 	}
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	twl6040->mclk = devm_clk_get(&client->dev, "mclk");
675*4882a593Smuzhiyun 	if (IS_ERR(twl6040->mclk)) {
676*4882a593Smuzhiyun 		if (PTR_ERR(twl6040->mclk) == -EPROBE_DEFER)
677*4882a593Smuzhiyun 			return -EPROBE_DEFER;
678*4882a593Smuzhiyun 		dev_dbg(&client->dev, "mclk is not handled\n");
679*4882a593Smuzhiyun 		twl6040->mclk = NULL;
680*4882a593Smuzhiyun 	}
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	twl6040->supplies[0].supply = "vio";
683*4882a593Smuzhiyun 	twl6040->supplies[1].supply = "v2v1";
684*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
685*4882a593Smuzhiyun 				      twl6040->supplies);
686*4882a593Smuzhiyun 	if (ret != 0) {
687*4882a593Smuzhiyun 		dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
688*4882a593Smuzhiyun 		return ret;
689*4882a593Smuzhiyun 	}
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
692*4882a593Smuzhiyun 	if (ret != 0) {
693*4882a593Smuzhiyun 		dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
694*4882a593Smuzhiyun 		return ret;
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	twl6040->dev = &client->dev;
698*4882a593Smuzhiyun 	twl6040->irq = client->irq;
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	mutex_init(&twl6040->mutex);
701*4882a593Smuzhiyun 	init_completion(&twl6040->ready);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	regmap_register_patch(twl6040->regmap, twl6040_patch,
704*4882a593Smuzhiyun 			      ARRAY_SIZE(twl6040_patch));
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
707*4882a593Smuzhiyun 	if (twl6040->rev < 0) {
708*4882a593Smuzhiyun 		dev_err(&client->dev, "Failed to read revision register: %d\n",
709*4882a593Smuzhiyun 			twl6040->rev);
710*4882a593Smuzhiyun 		ret = twl6040->rev;
711*4882a593Smuzhiyun 		goto gpio_err;
712*4882a593Smuzhiyun 	}
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	/* ERRATA: Automatic power-up is not possible in ES1.0 */
715*4882a593Smuzhiyun 	if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0)
716*4882a593Smuzhiyun 		twl6040->audpwron = of_get_named_gpio(node,
717*4882a593Smuzhiyun 						      "ti,audpwron-gpio", 0);
718*4882a593Smuzhiyun 	else
719*4882a593Smuzhiyun 		twl6040->audpwron = -EINVAL;
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	if (gpio_is_valid(twl6040->audpwron)) {
722*4882a593Smuzhiyun 		ret = devm_gpio_request_one(&client->dev, twl6040->audpwron,
723*4882a593Smuzhiyun 					    GPIOF_OUT_INIT_LOW, "audpwron");
724*4882a593Smuzhiyun 		if (ret)
725*4882a593Smuzhiyun 			goto gpio_err;
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 		/* Clear any pending interrupt */
728*4882a593Smuzhiyun 		twl6040_reg_read(twl6040, TWL6040_REG_INTID);
729*4882a593Smuzhiyun 	}
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT,
732*4882a593Smuzhiyun 				  0, &twl6040_irq_chip, &twl6040->irq_data);
733*4882a593Smuzhiyun 	if (ret < 0)
734*4882a593Smuzhiyun 		goto gpio_err;
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	twl6040->irq_ready = regmap_irq_get_virq(twl6040->irq_data,
737*4882a593Smuzhiyun 						 TWL6040_IRQ_READY);
738*4882a593Smuzhiyun 	twl6040->irq_th = regmap_irq_get_virq(twl6040->irq_data,
739*4882a593Smuzhiyun 					      TWL6040_IRQ_TH);
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_ready, NULL,
742*4882a593Smuzhiyun 					twl6040_readyint_handler, IRQF_ONESHOT,
743*4882a593Smuzhiyun 					"twl6040_irq_ready", twl6040);
744*4882a593Smuzhiyun 	if (ret) {
745*4882a593Smuzhiyun 		dev_err(twl6040->dev, "READY IRQ request failed: %d\n", ret);
746*4882a593Smuzhiyun 		goto readyirq_err;
747*4882a593Smuzhiyun 	}
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_th, NULL,
750*4882a593Smuzhiyun 					twl6040_thint_handler, IRQF_ONESHOT,
751*4882a593Smuzhiyun 					"twl6040_irq_th", twl6040);
752*4882a593Smuzhiyun 	if (ret) {
753*4882a593Smuzhiyun 		dev_err(twl6040->dev, "Thermal IRQ request failed: %d\n", ret);
754*4882a593Smuzhiyun 		goto readyirq_err;
755*4882a593Smuzhiyun 	}
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	/*
758*4882a593Smuzhiyun 	 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
759*4882a593Smuzhiyun 	 * We can add the ASoC codec child whenever this driver has been loaded.
760*4882a593Smuzhiyun 	 */
761*4882a593Smuzhiyun 	irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_PLUG);
762*4882a593Smuzhiyun 	cell = &twl6040->cells[children];
763*4882a593Smuzhiyun 	cell->name = "twl6040-codec";
764*4882a593Smuzhiyun 	twl6040_codec_rsrc[0].start = irq;
765*4882a593Smuzhiyun 	twl6040_codec_rsrc[0].end = irq;
766*4882a593Smuzhiyun 	cell->resources = twl6040_codec_rsrc;
767*4882a593Smuzhiyun 	cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
768*4882a593Smuzhiyun 	children++;
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	/* Vibra input driver support */
771*4882a593Smuzhiyun 	if (twl6040_has_vibra(node)) {
772*4882a593Smuzhiyun 		irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_VIB);
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 		cell = &twl6040->cells[children];
775*4882a593Smuzhiyun 		cell->name = "twl6040-vibra";
776*4882a593Smuzhiyun 		twl6040_vibra_rsrc[0].start = irq;
777*4882a593Smuzhiyun 		twl6040_vibra_rsrc[0].end = irq;
778*4882a593Smuzhiyun 		cell->resources = twl6040_vibra_rsrc;
779*4882a593Smuzhiyun 		cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
780*4882a593Smuzhiyun 		children++;
781*4882a593Smuzhiyun 	}
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 	/* GPO support */
784*4882a593Smuzhiyun 	cell = &twl6040->cells[children];
785*4882a593Smuzhiyun 	cell->name = "twl6040-gpo";
786*4882a593Smuzhiyun 	children++;
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	/* PDM clock support  */
789*4882a593Smuzhiyun 	cell = &twl6040->cells[children];
790*4882a593Smuzhiyun 	cell->name = "twl6040-pdmclk";
791*4882a593Smuzhiyun 	children++;
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	/* The chip is powered down so mark regmap to cache only and dirty */
794*4882a593Smuzhiyun 	regcache_cache_only(twl6040->regmap, true);
795*4882a593Smuzhiyun 	regcache_mark_dirty(twl6040->regmap);
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 	ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
798*4882a593Smuzhiyun 			      NULL, 0, NULL);
799*4882a593Smuzhiyun 	if (ret)
800*4882a593Smuzhiyun 		goto readyirq_err;
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	return 0;
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun readyirq_err:
805*4882a593Smuzhiyun 	regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
806*4882a593Smuzhiyun gpio_err:
807*4882a593Smuzhiyun 	regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
808*4882a593Smuzhiyun 	return ret;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun 
twl6040_remove(struct i2c_client * client)811*4882a593Smuzhiyun static int twl6040_remove(struct i2c_client *client)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun 	struct twl6040 *twl6040 = i2c_get_clientdata(client);
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	if (twl6040->power_count)
816*4882a593Smuzhiyun 		twl6040_power(twl6040, 0);
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun 	regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	mfd_remove_devices(&client->dev);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun 	return 0;
825*4882a593Smuzhiyun }
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun static const struct i2c_device_id twl6040_i2c_id[] = {
828*4882a593Smuzhiyun 	{ "twl6040", 0, },
829*4882a593Smuzhiyun 	{ "twl6041", 0, },
830*4882a593Smuzhiyun 	{ },
831*4882a593Smuzhiyun };
832*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun static struct i2c_driver twl6040_driver = {
835*4882a593Smuzhiyun 	.driver = {
836*4882a593Smuzhiyun 		.name = "twl6040",
837*4882a593Smuzhiyun 	},
838*4882a593Smuzhiyun 	.probe		= twl6040_probe,
839*4882a593Smuzhiyun 	.remove		= twl6040_remove,
840*4882a593Smuzhiyun 	.id_table	= twl6040_i2c_id,
841*4882a593Smuzhiyun };
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun module_i2c_driver(twl6040_driver);
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun MODULE_DESCRIPTION("TWL6040 MFD");
846*4882a593Smuzhiyun MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
847*4882a593Smuzhiyun MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
848*4882a593Smuzhiyun MODULE_LICENSE("GPL");
849