1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * tps65910.c -- TI TPS6591x chip family multi-function driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2010 Texas Instruments Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Graeme Gregory <gg@slimlogic.co.uk>
8*4882a593Smuzhiyun * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/irqdomain.h>
18*4882a593Smuzhiyun #include <linux/mfd/core.h>
19*4882a593Smuzhiyun #include <linux/regmap.h>
20*4882a593Smuzhiyun #include <linux/mfd/tps65910.h>
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun #include <linux/of_device.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static struct resource rtc_resources[] = {
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun .start = TPS65910_IRQ_RTC_ALARM,
27*4882a593Smuzhiyun .end = TPS65910_IRQ_RTC_ALARM,
28*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct mfd_cell tps65910s[] = {
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun .name = "tps65910-gpio",
35*4882a593Smuzhiyun },
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun .name = "tps65910-pmic",
38*4882a593Smuzhiyun },
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun .name = "tps65910-rtc",
41*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rtc_resources),
42*4882a593Smuzhiyun .resources = &rtc_resources[0],
43*4882a593Smuzhiyun },
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun .name = "tps65910-power",
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct regmap_irq tps65911_irqs[] = {
51*4882a593Smuzhiyun /* INT_STS */
52*4882a593Smuzhiyun [TPS65911_IRQ_PWRHOLD_F] = {
53*4882a593Smuzhiyun .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
54*4882a593Smuzhiyun .reg_offset = 0,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun [TPS65911_IRQ_VBAT_VMHI] = {
57*4882a593Smuzhiyun .mask = INT_MSK_VMBHI_IT_MSK_MASK,
58*4882a593Smuzhiyun .reg_offset = 0,
59*4882a593Smuzhiyun },
60*4882a593Smuzhiyun [TPS65911_IRQ_PWRON] = {
61*4882a593Smuzhiyun .mask = INT_MSK_PWRON_IT_MSK_MASK,
62*4882a593Smuzhiyun .reg_offset = 0,
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun [TPS65911_IRQ_PWRON_LP] = {
65*4882a593Smuzhiyun .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
66*4882a593Smuzhiyun .reg_offset = 0,
67*4882a593Smuzhiyun },
68*4882a593Smuzhiyun [TPS65911_IRQ_PWRHOLD_R] = {
69*4882a593Smuzhiyun .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
70*4882a593Smuzhiyun .reg_offset = 0,
71*4882a593Smuzhiyun },
72*4882a593Smuzhiyun [TPS65911_IRQ_HOTDIE] = {
73*4882a593Smuzhiyun .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
74*4882a593Smuzhiyun .reg_offset = 0,
75*4882a593Smuzhiyun },
76*4882a593Smuzhiyun [TPS65911_IRQ_RTC_ALARM] = {
77*4882a593Smuzhiyun .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
78*4882a593Smuzhiyun .reg_offset = 0,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun [TPS65911_IRQ_RTC_PERIOD] = {
81*4882a593Smuzhiyun .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
82*4882a593Smuzhiyun .reg_offset = 0,
83*4882a593Smuzhiyun },
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* INT_STS2 */
86*4882a593Smuzhiyun [TPS65911_IRQ_GPIO0_R] = {
87*4882a593Smuzhiyun .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
88*4882a593Smuzhiyun .reg_offset = 1,
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun [TPS65911_IRQ_GPIO0_F] = {
91*4882a593Smuzhiyun .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
92*4882a593Smuzhiyun .reg_offset = 1,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun [TPS65911_IRQ_GPIO1_R] = {
95*4882a593Smuzhiyun .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
96*4882a593Smuzhiyun .reg_offset = 1,
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun [TPS65911_IRQ_GPIO1_F] = {
99*4882a593Smuzhiyun .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
100*4882a593Smuzhiyun .reg_offset = 1,
101*4882a593Smuzhiyun },
102*4882a593Smuzhiyun [TPS65911_IRQ_GPIO2_R] = {
103*4882a593Smuzhiyun .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
104*4882a593Smuzhiyun .reg_offset = 1,
105*4882a593Smuzhiyun },
106*4882a593Smuzhiyun [TPS65911_IRQ_GPIO2_F] = {
107*4882a593Smuzhiyun .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
108*4882a593Smuzhiyun .reg_offset = 1,
109*4882a593Smuzhiyun },
110*4882a593Smuzhiyun [TPS65911_IRQ_GPIO3_R] = {
111*4882a593Smuzhiyun .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
112*4882a593Smuzhiyun .reg_offset = 1,
113*4882a593Smuzhiyun },
114*4882a593Smuzhiyun [TPS65911_IRQ_GPIO3_F] = {
115*4882a593Smuzhiyun .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
116*4882a593Smuzhiyun .reg_offset = 1,
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* INT_STS2 */
120*4882a593Smuzhiyun [TPS65911_IRQ_GPIO4_R] = {
121*4882a593Smuzhiyun .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
122*4882a593Smuzhiyun .reg_offset = 2,
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun [TPS65911_IRQ_GPIO4_F] = {
125*4882a593Smuzhiyun .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
126*4882a593Smuzhiyun .reg_offset = 2,
127*4882a593Smuzhiyun },
128*4882a593Smuzhiyun [TPS65911_IRQ_GPIO5_R] = {
129*4882a593Smuzhiyun .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
130*4882a593Smuzhiyun .reg_offset = 2,
131*4882a593Smuzhiyun },
132*4882a593Smuzhiyun [TPS65911_IRQ_GPIO5_F] = {
133*4882a593Smuzhiyun .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
134*4882a593Smuzhiyun .reg_offset = 2,
135*4882a593Smuzhiyun },
136*4882a593Smuzhiyun [TPS65911_IRQ_WTCHDG] = {
137*4882a593Smuzhiyun .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
138*4882a593Smuzhiyun .reg_offset = 2,
139*4882a593Smuzhiyun },
140*4882a593Smuzhiyun [TPS65911_IRQ_VMBCH2_H] = {
141*4882a593Smuzhiyun .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
142*4882a593Smuzhiyun .reg_offset = 2,
143*4882a593Smuzhiyun },
144*4882a593Smuzhiyun [TPS65911_IRQ_VMBCH2_L] = {
145*4882a593Smuzhiyun .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
146*4882a593Smuzhiyun .reg_offset = 2,
147*4882a593Smuzhiyun },
148*4882a593Smuzhiyun [TPS65911_IRQ_PWRDN] = {
149*4882a593Smuzhiyun .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
150*4882a593Smuzhiyun .reg_offset = 2,
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun static const struct regmap_irq tps65910_irqs[] = {
155*4882a593Smuzhiyun /* INT_STS */
156*4882a593Smuzhiyun [TPS65910_IRQ_VBAT_VMBDCH] = {
157*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
158*4882a593Smuzhiyun .reg_offset = 0,
159*4882a593Smuzhiyun },
160*4882a593Smuzhiyun [TPS65910_IRQ_VBAT_VMHI] = {
161*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
162*4882a593Smuzhiyun .reg_offset = 0,
163*4882a593Smuzhiyun },
164*4882a593Smuzhiyun [TPS65910_IRQ_PWRON] = {
165*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
166*4882a593Smuzhiyun .reg_offset = 0,
167*4882a593Smuzhiyun },
168*4882a593Smuzhiyun [TPS65910_IRQ_PWRON_LP] = {
169*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
170*4882a593Smuzhiyun .reg_offset = 0,
171*4882a593Smuzhiyun },
172*4882a593Smuzhiyun [TPS65910_IRQ_PWRHOLD] = {
173*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
174*4882a593Smuzhiyun .reg_offset = 0,
175*4882a593Smuzhiyun },
176*4882a593Smuzhiyun [TPS65910_IRQ_HOTDIE] = {
177*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
178*4882a593Smuzhiyun .reg_offset = 0,
179*4882a593Smuzhiyun },
180*4882a593Smuzhiyun [TPS65910_IRQ_RTC_ALARM] = {
181*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
182*4882a593Smuzhiyun .reg_offset = 0,
183*4882a593Smuzhiyun },
184*4882a593Smuzhiyun [TPS65910_IRQ_RTC_PERIOD] = {
185*4882a593Smuzhiyun .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
186*4882a593Smuzhiyun .reg_offset = 0,
187*4882a593Smuzhiyun },
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* INT_STS2 */
190*4882a593Smuzhiyun [TPS65910_IRQ_GPIO_R] = {
191*4882a593Smuzhiyun .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
192*4882a593Smuzhiyun .reg_offset = 1,
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun [TPS65910_IRQ_GPIO_F] = {
195*4882a593Smuzhiyun .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
196*4882a593Smuzhiyun .reg_offset = 1,
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static struct regmap_irq_chip tps65911_irq_chip = {
201*4882a593Smuzhiyun .name = "tps65910",
202*4882a593Smuzhiyun .irqs = tps65911_irqs,
203*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(tps65911_irqs),
204*4882a593Smuzhiyun .num_regs = 3,
205*4882a593Smuzhiyun .irq_reg_stride = 2,
206*4882a593Smuzhiyun .status_base = TPS65910_INT_STS,
207*4882a593Smuzhiyun .mask_base = TPS65910_INT_MSK,
208*4882a593Smuzhiyun .ack_base = TPS65910_INT_STS,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static struct regmap_irq_chip tps65910_irq_chip = {
212*4882a593Smuzhiyun .name = "tps65910",
213*4882a593Smuzhiyun .irqs = tps65910_irqs,
214*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(tps65910_irqs),
215*4882a593Smuzhiyun .num_regs = 2,
216*4882a593Smuzhiyun .irq_reg_stride = 2,
217*4882a593Smuzhiyun .status_base = TPS65910_INT_STS,
218*4882a593Smuzhiyun .mask_base = TPS65910_INT_MSK,
219*4882a593Smuzhiyun .ack_base = TPS65910_INT_STS,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
tps65910_irq_init(struct tps65910 * tps65910,int irq,struct tps65910_platform_data * pdata)222*4882a593Smuzhiyun static int tps65910_irq_init(struct tps65910 *tps65910, int irq,
223*4882a593Smuzhiyun struct tps65910_platform_data *pdata)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun int ret;
226*4882a593Smuzhiyun static struct regmap_irq_chip *tps6591x_irqs_chip;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun if (!irq) {
229*4882a593Smuzhiyun dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
230*4882a593Smuzhiyun return -EINVAL;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (!pdata) {
234*4882a593Smuzhiyun dev_warn(tps65910->dev, "No interrupt support, no pdata\n");
235*4882a593Smuzhiyun return -EINVAL;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun switch (tps65910_chip_id(tps65910)) {
239*4882a593Smuzhiyun case TPS65910:
240*4882a593Smuzhiyun tps6591x_irqs_chip = &tps65910_irq_chip;
241*4882a593Smuzhiyun break;
242*4882a593Smuzhiyun case TPS65911:
243*4882a593Smuzhiyun tps6591x_irqs_chip = &tps65911_irq_chip;
244*4882a593Smuzhiyun break;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun tps65910->chip_irq = irq;
248*4882a593Smuzhiyun ret = devm_regmap_add_irq_chip(tps65910->dev, tps65910->regmap,
249*4882a593Smuzhiyun tps65910->chip_irq,
250*4882a593Smuzhiyun IRQF_ONESHOT, pdata->irq_base,
251*4882a593Smuzhiyun tps6591x_irqs_chip, &tps65910->irq_data);
252*4882a593Smuzhiyun if (ret < 0) {
253*4882a593Smuzhiyun dev_warn(tps65910->dev, "Failed to add irq_chip %d\n", ret);
254*4882a593Smuzhiyun tps65910->chip_irq = 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun return ret;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
is_volatile_reg(struct device * dev,unsigned int reg)259*4882a593Smuzhiyun static bool is_volatile_reg(struct device *dev, unsigned int reg)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun struct tps65910 *tps65910 = dev_get_drvdata(dev);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * Caching all regulator registers.
265*4882a593Smuzhiyun * All regualator register address range is same for
266*4882a593Smuzhiyun * TPS65910 and TPS65911
267*4882a593Smuzhiyun */
268*4882a593Smuzhiyun if ((reg >= TPS65910_VIO) && (reg <= TPS65910_VDAC)) {
269*4882a593Smuzhiyun /* Check for non-existing register */
270*4882a593Smuzhiyun if (tps65910_chip_id(tps65910) == TPS65910)
271*4882a593Smuzhiyun if ((reg == TPS65911_VDDCTRL_OP) ||
272*4882a593Smuzhiyun (reg == TPS65911_VDDCTRL_SR))
273*4882a593Smuzhiyun return true;
274*4882a593Smuzhiyun return false;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun return true;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static const struct regmap_config tps65910_regmap_config = {
280*4882a593Smuzhiyun .reg_bits = 8,
281*4882a593Smuzhiyun .val_bits = 8,
282*4882a593Smuzhiyun .volatile_reg = is_volatile_reg,
283*4882a593Smuzhiyun .max_register = TPS65910_MAX_REGISTER - 1,
284*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun
tps65910_ck32k_init(struct tps65910 * tps65910,struct tps65910_board * pmic_pdata)287*4882a593Smuzhiyun static int tps65910_ck32k_init(struct tps65910 *tps65910,
288*4882a593Smuzhiyun struct tps65910_board *pmic_pdata)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun int ret;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (!pmic_pdata->en_ck32k_xtal)
293*4882a593Smuzhiyun return 0;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun ret = tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
296*4882a593Smuzhiyun DEVCTRL_CK32K_CTRL_MASK);
297*4882a593Smuzhiyun if (ret < 0) {
298*4882a593Smuzhiyun dev_err(tps65910->dev, "clear ck32k_ctrl failed: %d\n", ret);
299*4882a593Smuzhiyun return ret;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return 0;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
tps65910_sleepinit(struct tps65910 * tps65910,struct tps65910_board * pmic_pdata)305*4882a593Smuzhiyun static int tps65910_sleepinit(struct tps65910 *tps65910,
306*4882a593Smuzhiyun struct tps65910_board *pmic_pdata)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun struct device *dev;
309*4882a593Smuzhiyun int ret;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun if (!pmic_pdata->en_dev_slp)
312*4882a593Smuzhiyun return 0;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun dev = tps65910->dev;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* enabling SLEEP device state */
317*4882a593Smuzhiyun ret = tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL,
318*4882a593Smuzhiyun DEVCTRL_DEV_SLP_MASK);
319*4882a593Smuzhiyun if (ret < 0) {
320*4882a593Smuzhiyun dev_err(dev, "set dev_slp failed: %d\n", ret);
321*4882a593Smuzhiyun goto err_sleep_init;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun if (pmic_pdata->slp_keepon.therm_keepon) {
325*4882a593Smuzhiyun ret = tps65910_reg_set_bits(tps65910,
326*4882a593Smuzhiyun TPS65910_SLEEP_KEEP_RES_ON,
327*4882a593Smuzhiyun SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK);
328*4882a593Smuzhiyun if (ret < 0) {
329*4882a593Smuzhiyun dev_err(dev, "set therm_keepon failed: %d\n", ret);
330*4882a593Smuzhiyun goto disable_dev_slp;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun if (pmic_pdata->slp_keepon.clkout32k_keepon) {
335*4882a593Smuzhiyun ret = tps65910_reg_set_bits(tps65910,
336*4882a593Smuzhiyun TPS65910_SLEEP_KEEP_RES_ON,
337*4882a593Smuzhiyun SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK);
338*4882a593Smuzhiyun if (ret < 0) {
339*4882a593Smuzhiyun dev_err(dev, "set clkout32k_keepon failed: %d\n", ret);
340*4882a593Smuzhiyun goto disable_dev_slp;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun if (pmic_pdata->slp_keepon.i2chs_keepon) {
345*4882a593Smuzhiyun ret = tps65910_reg_set_bits(tps65910,
346*4882a593Smuzhiyun TPS65910_SLEEP_KEEP_RES_ON,
347*4882a593Smuzhiyun SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK);
348*4882a593Smuzhiyun if (ret < 0) {
349*4882a593Smuzhiyun dev_err(dev, "set i2chs_keepon failed: %d\n", ret);
350*4882a593Smuzhiyun goto disable_dev_slp;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun return 0;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun disable_dev_slp:
357*4882a593Smuzhiyun tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
358*4882a593Smuzhiyun DEVCTRL_DEV_SLP_MASK);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun err_sleep_init:
361*4882a593Smuzhiyun return ret;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun #ifdef CONFIG_OF
365*4882a593Smuzhiyun static const struct of_device_id tps65910_of_match[] = {
366*4882a593Smuzhiyun { .compatible = "ti,tps65910", .data = (void *)TPS65910},
367*4882a593Smuzhiyun { .compatible = "ti,tps65911", .data = (void *)TPS65911},
368*4882a593Smuzhiyun { },
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun
tps65910_parse_dt(struct i2c_client * client,unsigned long * chip_id)371*4882a593Smuzhiyun static struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
372*4882a593Smuzhiyun unsigned long *chip_id)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun struct device_node *np = client->dev.of_node;
375*4882a593Smuzhiyun struct tps65910_board *board_info;
376*4882a593Smuzhiyun unsigned int prop;
377*4882a593Smuzhiyun const struct of_device_id *match;
378*4882a593Smuzhiyun int ret;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun match = of_match_device(tps65910_of_match, &client->dev);
381*4882a593Smuzhiyun if (!match) {
382*4882a593Smuzhiyun dev_err(&client->dev, "Failed to find matching dt id\n");
383*4882a593Smuzhiyun return NULL;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun *chip_id = (unsigned long)match->data;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun board_info = devm_kzalloc(&client->dev, sizeof(*board_info),
389*4882a593Smuzhiyun GFP_KERNEL);
390*4882a593Smuzhiyun if (!board_info)
391*4882a593Smuzhiyun return NULL;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun ret = of_property_read_u32(np, "ti,vmbch-threshold", &prop);
394*4882a593Smuzhiyun if (!ret)
395*4882a593Smuzhiyun board_info->vmbch_threshold = prop;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun ret = of_property_read_u32(np, "ti,vmbch2-threshold", &prop);
398*4882a593Smuzhiyun if (!ret)
399*4882a593Smuzhiyun board_info->vmbch2_threshold = prop;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun prop = of_property_read_bool(np, "ti,en-ck32k-xtal");
402*4882a593Smuzhiyun board_info->en_ck32k_xtal = prop;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun prop = of_property_read_bool(np, "ti,sleep-enable");
405*4882a593Smuzhiyun board_info->en_dev_slp = prop;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun prop = of_property_read_bool(np, "ti,sleep-keep-therm");
408*4882a593Smuzhiyun board_info->slp_keepon.therm_keepon = prop;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun prop = of_property_read_bool(np, "ti,sleep-keep-ck32k");
411*4882a593Smuzhiyun board_info->slp_keepon.clkout32k_keepon = prop;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun prop = of_property_read_bool(np, "ti,sleep-keep-hsclk");
414*4882a593Smuzhiyun board_info->slp_keepon.i2chs_keepon = prop;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun board_info->irq = client->irq;
417*4882a593Smuzhiyun board_info->irq_base = -1;
418*4882a593Smuzhiyun board_info->pm_off = of_property_read_bool(np,
419*4882a593Smuzhiyun "ti,system-power-controller");
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun return board_info;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun #else
424*4882a593Smuzhiyun static inline
tps65910_parse_dt(struct i2c_client * client,unsigned long * chip_id)425*4882a593Smuzhiyun struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
426*4882a593Smuzhiyun unsigned long *chip_id)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun return NULL;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun #endif
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun static struct i2c_client *tps65910_i2c_client;
tps65910_power_off(void)433*4882a593Smuzhiyun static void tps65910_power_off(void)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun struct tps65910 *tps65910;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun tps65910 = dev_get_drvdata(&tps65910_i2c_client->dev);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun if (tps65910_reg_set_bits(tps65910, TPS65910_DEVCTRL,
440*4882a593Smuzhiyun DEVCTRL_PWR_OFF_MASK) < 0)
441*4882a593Smuzhiyun return;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
444*4882a593Smuzhiyun DEVCTRL_DEV_ON_MASK);
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun
tps65910_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)447*4882a593Smuzhiyun static int tps65910_i2c_probe(struct i2c_client *i2c,
448*4882a593Smuzhiyun const struct i2c_device_id *id)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun struct tps65910 *tps65910;
451*4882a593Smuzhiyun struct tps65910_board *pmic_plat_data;
452*4882a593Smuzhiyun struct tps65910_board *of_pmic_plat_data = NULL;
453*4882a593Smuzhiyun struct tps65910_platform_data *init_data;
454*4882a593Smuzhiyun unsigned long chip_id = id->driver_data;
455*4882a593Smuzhiyun int ret;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun pmic_plat_data = dev_get_platdata(&i2c->dev);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun if (!pmic_plat_data && i2c->dev.of_node) {
460*4882a593Smuzhiyun pmic_plat_data = tps65910_parse_dt(i2c, &chip_id);
461*4882a593Smuzhiyun of_pmic_plat_data = pmic_plat_data;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun if (!pmic_plat_data)
465*4882a593Smuzhiyun return -EINVAL;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun init_data = devm_kzalloc(&i2c->dev, sizeof(*init_data), GFP_KERNEL);
468*4882a593Smuzhiyun if (init_data == NULL)
469*4882a593Smuzhiyun return -ENOMEM;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun tps65910 = devm_kzalloc(&i2c->dev, sizeof(*tps65910), GFP_KERNEL);
472*4882a593Smuzhiyun if (tps65910 == NULL)
473*4882a593Smuzhiyun return -ENOMEM;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun tps65910->of_plat_data = of_pmic_plat_data;
476*4882a593Smuzhiyun i2c_set_clientdata(i2c, tps65910);
477*4882a593Smuzhiyun tps65910->dev = &i2c->dev;
478*4882a593Smuzhiyun tps65910->i2c_client = i2c;
479*4882a593Smuzhiyun tps65910->id = chip_id;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun /* Work around silicon erratum SWCZ010: the tps65910 may miss the
482*4882a593Smuzhiyun * first I2C transfer. So issue a dummy transfer before the first
483*4882a593Smuzhiyun * real transfer.
484*4882a593Smuzhiyun */
485*4882a593Smuzhiyun i2c_master_send(i2c, "", 1);
486*4882a593Smuzhiyun tps65910->regmap = devm_regmap_init_i2c(i2c, &tps65910_regmap_config);
487*4882a593Smuzhiyun if (IS_ERR(tps65910->regmap)) {
488*4882a593Smuzhiyun ret = PTR_ERR(tps65910->regmap);
489*4882a593Smuzhiyun dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
490*4882a593Smuzhiyun return ret;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun init_data->irq = pmic_plat_data->irq;
494*4882a593Smuzhiyun init_data->irq_base = pmic_plat_data->irq_base;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun tps65910_irq_init(tps65910, init_data->irq, init_data);
497*4882a593Smuzhiyun tps65910_ck32k_init(tps65910, pmic_plat_data);
498*4882a593Smuzhiyun tps65910_sleepinit(tps65910, pmic_plat_data);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun if (pmic_plat_data->pm_off && !pm_power_off) {
501*4882a593Smuzhiyun tps65910_i2c_client = i2c;
502*4882a593Smuzhiyun pm_power_off = tps65910_power_off;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun ret = devm_mfd_add_devices(tps65910->dev, -1,
506*4882a593Smuzhiyun tps65910s, ARRAY_SIZE(tps65910s),
507*4882a593Smuzhiyun NULL, 0,
508*4882a593Smuzhiyun regmap_irq_get_domain(tps65910->irq_data));
509*4882a593Smuzhiyun if (ret < 0) {
510*4882a593Smuzhiyun dev_err(&i2c->dev, "mfd_add_devices failed: %d\n", ret);
511*4882a593Smuzhiyun return ret;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun return ret;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static const struct i2c_device_id tps65910_i2c_id[] = {
518*4882a593Smuzhiyun { "tps65910", TPS65910 },
519*4882a593Smuzhiyun { "tps65911", TPS65911 },
520*4882a593Smuzhiyun { }
521*4882a593Smuzhiyun };
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun static struct i2c_driver tps65910_i2c_driver = {
524*4882a593Smuzhiyun .driver = {
525*4882a593Smuzhiyun .name = "tps65910",
526*4882a593Smuzhiyun .of_match_table = of_match_ptr(tps65910_of_match),
527*4882a593Smuzhiyun },
528*4882a593Smuzhiyun .probe = tps65910_i2c_probe,
529*4882a593Smuzhiyun .id_table = tps65910_i2c_id,
530*4882a593Smuzhiyun };
531*4882a593Smuzhiyun
tps65910_i2c_init(void)532*4882a593Smuzhiyun static int __init tps65910_i2c_init(void)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun return i2c_add_driver(&tps65910_i2c_driver);
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun /* init early so consumer devices can complete system boot */
537*4882a593Smuzhiyun subsys_initcall(tps65910_i2c_init);
538