xref: /OK3568_Linux_fs/kernel/drivers/mfd/tps65218.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Driver for TPS65218 Integrated power management chipsets
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
7*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License version 2 as
8*4882a593Smuzhiyun  * published by the Free Software Foundation.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11*4882a593Smuzhiyun  * kind, whether expressed or implied; without even the implied warranty
12*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13*4882a593Smuzhiyun  * GNU General Public License version 2 for more details.
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/device.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/i2c.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/regmap.h>
24*4882a593Smuzhiyun #include <linux/err.h>
25*4882a593Smuzhiyun #include <linux/of.h>
26*4882a593Smuzhiyun #include <linux/of_device.h>
27*4882a593Smuzhiyun #include <linux/irq.h>
28*4882a593Smuzhiyun #include <linux/interrupt.h>
29*4882a593Smuzhiyun #include <linux/mutex.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <linux/mfd/core.h>
32*4882a593Smuzhiyun #include <linux/mfd/tps65218.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define TPS65218_PASSWORD_REGS_UNLOCK   0x7D
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun static const struct mfd_cell tps65218_cells[] = {
37*4882a593Smuzhiyun 	{
38*4882a593Smuzhiyun 		.name = "tps65218-pwrbutton",
39*4882a593Smuzhiyun 		.of_compatible = "ti,tps65218-pwrbutton",
40*4882a593Smuzhiyun 	},
41*4882a593Smuzhiyun 	{
42*4882a593Smuzhiyun 		.name = "tps65218-gpio",
43*4882a593Smuzhiyun 		.of_compatible = "ti,tps65218-gpio",
44*4882a593Smuzhiyun 	},
45*4882a593Smuzhiyun 	{ .name = "tps65218-regulator", },
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun  * tps65218_reg_write: Write a single tps65218 register.
50*4882a593Smuzhiyun  *
51*4882a593Smuzhiyun  * @tps: Device to write to.
52*4882a593Smuzhiyun  * @reg: Register to write to.
53*4882a593Smuzhiyun  * @val: Value to write.
54*4882a593Smuzhiyun  * @level: Password protected level
55*4882a593Smuzhiyun  */
tps65218_reg_write(struct tps65218 * tps,unsigned int reg,unsigned int val,unsigned int level)56*4882a593Smuzhiyun int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
57*4882a593Smuzhiyun 			unsigned int val, unsigned int level)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	int ret;
60*4882a593Smuzhiyun 	unsigned int xor_reg_val;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	switch (level) {
63*4882a593Smuzhiyun 	case TPS65218_PROTECT_NONE:
64*4882a593Smuzhiyun 		return regmap_write(tps->regmap, reg, val);
65*4882a593Smuzhiyun 	case TPS65218_PROTECT_L1:
66*4882a593Smuzhiyun 		xor_reg_val = reg ^ TPS65218_PASSWORD_REGS_UNLOCK;
67*4882a593Smuzhiyun 		ret = regmap_write(tps->regmap, TPS65218_REG_PASSWORD,
68*4882a593Smuzhiyun 							xor_reg_val);
69*4882a593Smuzhiyun 		if (ret < 0)
70*4882a593Smuzhiyun 			return ret;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 		return regmap_write(tps->regmap, reg, val);
73*4882a593Smuzhiyun 	default:
74*4882a593Smuzhiyun 		return -EINVAL;
75*4882a593Smuzhiyun 	}
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65218_reg_write);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /**
80*4882a593Smuzhiyun  * tps65218_update_bits: Modify bits w.r.t mask, val and level.
81*4882a593Smuzhiyun  *
82*4882a593Smuzhiyun  * @tps: Device to write to.
83*4882a593Smuzhiyun  * @reg: Register to read-write to.
84*4882a593Smuzhiyun  * @mask: Mask.
85*4882a593Smuzhiyun  * @val: Value to write.
86*4882a593Smuzhiyun  * @level: Password protected level
87*4882a593Smuzhiyun  */
tps65218_update_bits(struct tps65218 * tps,unsigned int reg,unsigned int mask,unsigned int val,unsigned int level)88*4882a593Smuzhiyun static int tps65218_update_bits(struct tps65218 *tps, unsigned int reg,
89*4882a593Smuzhiyun 		unsigned int mask, unsigned int val, unsigned int level)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	int ret;
92*4882a593Smuzhiyun 	unsigned int data;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	ret = regmap_read(tps->regmap, reg, &data);
95*4882a593Smuzhiyun 	if (ret) {
96*4882a593Smuzhiyun 		dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
97*4882a593Smuzhiyun 		return ret;
98*4882a593Smuzhiyun 	}
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	data &= ~mask;
101*4882a593Smuzhiyun 	data |= val & mask;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	mutex_lock(&tps->tps_lock);
104*4882a593Smuzhiyun 	ret = tps65218_reg_write(tps, reg, data, level);
105*4882a593Smuzhiyun 	if (ret)
106*4882a593Smuzhiyun 		dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
107*4882a593Smuzhiyun 	mutex_unlock(&tps->tps_lock);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	return ret;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
tps65218_set_bits(struct tps65218 * tps,unsigned int reg,unsigned int mask,unsigned int val,unsigned int level)112*4882a593Smuzhiyun int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
113*4882a593Smuzhiyun 		unsigned int mask, unsigned int val, unsigned int level)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	return tps65218_update_bits(tps, reg, mask, val, level);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65218_set_bits);
118*4882a593Smuzhiyun 
tps65218_clear_bits(struct tps65218 * tps,unsigned int reg,unsigned int mask,unsigned int level)119*4882a593Smuzhiyun int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
120*4882a593Smuzhiyun 		unsigned int mask, unsigned int level)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	return tps65218_update_bits(tps, reg, mask, 0, level);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65218_clear_bits);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static const struct regmap_range tps65218_yes_ranges[] = {
127*4882a593Smuzhiyun 	regmap_reg_range(TPS65218_REG_INT1, TPS65218_REG_INT2),
128*4882a593Smuzhiyun 	regmap_reg_range(TPS65218_REG_STATUS, TPS65218_REG_STATUS),
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static const struct regmap_access_table tps65218_volatile_table = {
132*4882a593Smuzhiyun 	.yes_ranges = tps65218_yes_ranges,
133*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges),
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static const struct regmap_config tps65218_regmap_config = {
137*4882a593Smuzhiyun 	.reg_bits = 8,
138*4882a593Smuzhiyun 	.val_bits = 8,
139*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
140*4882a593Smuzhiyun 	.volatile_table = &tps65218_volatile_table,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static const struct regmap_irq tps65218_irqs[] = {
144*4882a593Smuzhiyun 	/* INT1 IRQs */
145*4882a593Smuzhiyun 	[TPS65218_PRGC_IRQ] = {
146*4882a593Smuzhiyun 		.mask = TPS65218_INT1_PRGC,
147*4882a593Smuzhiyun 	},
148*4882a593Smuzhiyun 	[TPS65218_CC_AQC_IRQ] = {
149*4882a593Smuzhiyun 		.mask = TPS65218_INT1_CC_AQC,
150*4882a593Smuzhiyun 	},
151*4882a593Smuzhiyun 	[TPS65218_HOT_IRQ] = {
152*4882a593Smuzhiyun 		.mask = TPS65218_INT1_HOT,
153*4882a593Smuzhiyun 	},
154*4882a593Smuzhiyun 	[TPS65218_PB_IRQ] = {
155*4882a593Smuzhiyun 		.mask = TPS65218_INT1_PB,
156*4882a593Smuzhiyun 	},
157*4882a593Smuzhiyun 	[TPS65218_AC_IRQ] = {
158*4882a593Smuzhiyun 		.mask = TPS65218_INT1_AC,
159*4882a593Smuzhiyun 	},
160*4882a593Smuzhiyun 	[TPS65218_VPRG_IRQ] = {
161*4882a593Smuzhiyun 		.mask = TPS65218_INT1_VPRG,
162*4882a593Smuzhiyun 	},
163*4882a593Smuzhiyun 	[TPS65218_INVALID1_IRQ] = {
164*4882a593Smuzhiyun 	},
165*4882a593Smuzhiyun 	[TPS65218_INVALID2_IRQ] = {
166*4882a593Smuzhiyun 	},
167*4882a593Smuzhiyun 	/* INT2 IRQs*/
168*4882a593Smuzhiyun 	[TPS65218_LS1_I_IRQ] = {
169*4882a593Smuzhiyun 		.mask = TPS65218_INT2_LS1_I,
170*4882a593Smuzhiyun 		.reg_offset = 1,
171*4882a593Smuzhiyun 	},
172*4882a593Smuzhiyun 	[TPS65218_LS2_I_IRQ] = {
173*4882a593Smuzhiyun 		.mask = TPS65218_INT2_LS2_I,
174*4882a593Smuzhiyun 		.reg_offset = 1,
175*4882a593Smuzhiyun 	},
176*4882a593Smuzhiyun 	[TPS65218_LS3_I_IRQ] = {
177*4882a593Smuzhiyun 		.mask = TPS65218_INT2_LS3_I,
178*4882a593Smuzhiyun 		.reg_offset = 1,
179*4882a593Smuzhiyun 	},
180*4882a593Smuzhiyun 	[TPS65218_LS1_F_IRQ] = {
181*4882a593Smuzhiyun 		.mask = TPS65218_INT2_LS1_F,
182*4882a593Smuzhiyun 		.reg_offset = 1,
183*4882a593Smuzhiyun 	},
184*4882a593Smuzhiyun 	[TPS65218_LS2_F_IRQ] = {
185*4882a593Smuzhiyun 		.mask = TPS65218_INT2_LS2_F,
186*4882a593Smuzhiyun 		.reg_offset = 1,
187*4882a593Smuzhiyun 	},
188*4882a593Smuzhiyun 	[TPS65218_LS3_F_IRQ] = {
189*4882a593Smuzhiyun 		.mask = TPS65218_INT2_LS3_F,
190*4882a593Smuzhiyun 		.reg_offset = 1,
191*4882a593Smuzhiyun 	},
192*4882a593Smuzhiyun 	[TPS65218_INVALID3_IRQ] = {
193*4882a593Smuzhiyun 	},
194*4882a593Smuzhiyun 	[TPS65218_INVALID4_IRQ] = {
195*4882a593Smuzhiyun 	},
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static struct regmap_irq_chip tps65218_irq_chip = {
199*4882a593Smuzhiyun 	.name = "tps65218",
200*4882a593Smuzhiyun 	.irqs = tps65218_irqs,
201*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(tps65218_irqs),
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	.num_regs = 2,
204*4882a593Smuzhiyun 	.mask_base = TPS65218_REG_INT_MASK1,
205*4882a593Smuzhiyun 	.status_base = TPS65218_REG_INT1,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct of_device_id of_tps65218_match_table[] = {
209*4882a593Smuzhiyun 	{ .compatible = "ti,tps65218", },
210*4882a593Smuzhiyun 	{}
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_tps65218_match_table);
213*4882a593Smuzhiyun 
tps65218_voltage_set_strict(struct tps65218 * tps)214*4882a593Smuzhiyun static int tps65218_voltage_set_strict(struct tps65218 *tps)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	u32 strict;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	if (of_property_read_u32(tps->dev->of_node,
219*4882a593Smuzhiyun 				 "ti,strict-supply-voltage-supervision",
220*4882a593Smuzhiyun 				 &strict))
221*4882a593Smuzhiyun 		return 0;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	if (strict != 0 && strict != 1) {
224*4882a593Smuzhiyun 		dev_err(tps->dev,
225*4882a593Smuzhiyun 			"Invalid ti,strict-supply-voltage-supervision value\n");
226*4882a593Smuzhiyun 		return -EINVAL;
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	tps65218_update_bits(tps, TPS65218_REG_CONFIG1,
230*4882a593Smuzhiyun 			     TPS65218_CONFIG1_STRICT,
231*4882a593Smuzhiyun 			     strict ? TPS65218_CONFIG1_STRICT : 0,
232*4882a593Smuzhiyun 			     TPS65218_PROTECT_L1);
233*4882a593Smuzhiyun 	return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
tps65218_voltage_set_uv_hyst(struct tps65218 * tps)236*4882a593Smuzhiyun static int tps65218_voltage_set_uv_hyst(struct tps65218 *tps)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	u32 hyst;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	if (of_property_read_u32(tps->dev->of_node,
241*4882a593Smuzhiyun 				 "ti,under-voltage-hyst-microvolt", &hyst))
242*4882a593Smuzhiyun 		return 0;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	if (hyst != 400000 && hyst != 200000) {
245*4882a593Smuzhiyun 		dev_err(tps->dev,
246*4882a593Smuzhiyun 			"Invalid ti,under-voltage-hyst-microvolt value\n");
247*4882a593Smuzhiyun 		return -EINVAL;
248*4882a593Smuzhiyun 	}
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	tps65218_update_bits(tps, TPS65218_REG_CONFIG2,
251*4882a593Smuzhiyun 			     TPS65218_CONFIG2_UVLOHYS,
252*4882a593Smuzhiyun 			     hyst == 400000 ? TPS65218_CONFIG2_UVLOHYS : 0,
253*4882a593Smuzhiyun 			     TPS65218_PROTECT_L1);
254*4882a593Smuzhiyun 	return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
tps65218_voltage_set_uvlo(struct tps65218 * tps)257*4882a593Smuzhiyun static int tps65218_voltage_set_uvlo(struct tps65218 *tps)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	u32 uvlo;
260*4882a593Smuzhiyun 	int uvloval;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	if (of_property_read_u32(tps->dev->of_node,
263*4882a593Smuzhiyun 				 "ti,under-voltage-limit-microvolt", &uvlo))
264*4882a593Smuzhiyun 		return 0;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	switch (uvlo) {
267*4882a593Smuzhiyun 	case 2750000:
268*4882a593Smuzhiyun 		uvloval = TPS65218_CONFIG1_UVLO_2750000;
269*4882a593Smuzhiyun 		break;
270*4882a593Smuzhiyun 	case 2950000:
271*4882a593Smuzhiyun 		uvloval = TPS65218_CONFIG1_UVLO_2950000;
272*4882a593Smuzhiyun 		break;
273*4882a593Smuzhiyun 	case 3250000:
274*4882a593Smuzhiyun 		uvloval = TPS65218_CONFIG1_UVLO_3250000;
275*4882a593Smuzhiyun 		break;
276*4882a593Smuzhiyun 	case 3350000:
277*4882a593Smuzhiyun 		uvloval = TPS65218_CONFIG1_UVLO_3350000;
278*4882a593Smuzhiyun 		break;
279*4882a593Smuzhiyun 	default:
280*4882a593Smuzhiyun 		dev_err(tps->dev,
281*4882a593Smuzhiyun 			"Invalid ti,under-voltage-limit-microvolt value\n");
282*4882a593Smuzhiyun 		return -EINVAL;
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	tps65218_update_bits(tps, TPS65218_REG_CONFIG1,
286*4882a593Smuzhiyun 			     TPS65218_CONFIG1_UVLO_MASK, uvloval,
287*4882a593Smuzhiyun 			     TPS65218_PROTECT_L1);
288*4882a593Smuzhiyun 	return 0;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun 
tps65218_probe(struct i2c_client * client,const struct i2c_device_id * ids)291*4882a593Smuzhiyun static int tps65218_probe(struct i2c_client *client,
292*4882a593Smuzhiyun 				const struct i2c_device_id *ids)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun 	struct tps65218 *tps;
295*4882a593Smuzhiyun 	int ret;
296*4882a593Smuzhiyun 	unsigned int chipid;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
299*4882a593Smuzhiyun 	if (!tps)
300*4882a593Smuzhiyun 		return -ENOMEM;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	i2c_set_clientdata(client, tps);
303*4882a593Smuzhiyun 	tps->dev = &client->dev;
304*4882a593Smuzhiyun 	tps->irq = client->irq;
305*4882a593Smuzhiyun 	tps->regmap = devm_regmap_init_i2c(client, &tps65218_regmap_config);
306*4882a593Smuzhiyun 	if (IS_ERR(tps->regmap)) {
307*4882a593Smuzhiyun 		ret = PTR_ERR(tps->regmap);
308*4882a593Smuzhiyun 		dev_err(tps->dev, "Failed to allocate register map: %d\n",
309*4882a593Smuzhiyun 			ret);
310*4882a593Smuzhiyun 		return ret;
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	mutex_init(&tps->tps_lock);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, tps->irq,
316*4882a593Smuzhiyun 				       IRQF_ONESHOT, 0, &tps65218_irq_chip,
317*4882a593Smuzhiyun 				       &tps->irq_data);
318*4882a593Smuzhiyun 	if (ret < 0)
319*4882a593Smuzhiyun 		return ret;
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	ret = regmap_read(tps->regmap, TPS65218_REG_CHIPID, &chipid);
322*4882a593Smuzhiyun 	if (ret) {
323*4882a593Smuzhiyun 		dev_err(tps->dev, "Failed to read chipid: %d\n", ret);
324*4882a593Smuzhiyun 		return ret;
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	tps->rev = chipid & TPS65218_CHIPID_REV_MASK;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	ret = tps65218_voltage_set_strict(tps);
330*4882a593Smuzhiyun 	if (ret)
331*4882a593Smuzhiyun 		return ret;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	ret = tps65218_voltage_set_uvlo(tps);
334*4882a593Smuzhiyun 	if (ret)
335*4882a593Smuzhiyun 		return ret;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	ret = tps65218_voltage_set_uv_hyst(tps);
338*4882a593Smuzhiyun 	if (ret)
339*4882a593Smuzhiyun 		return ret;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65218_cells,
342*4882a593Smuzhiyun 			      ARRAY_SIZE(tps65218_cells), NULL, 0,
343*4882a593Smuzhiyun 			      regmap_irq_get_domain(tps->irq_data));
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun static const struct i2c_device_id tps65218_id_table[] = {
349*4882a593Smuzhiyun 	{ "tps65218", TPS65218 },
350*4882a593Smuzhiyun 	{ },
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, tps65218_id_table);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun static struct i2c_driver tps65218_driver = {
355*4882a593Smuzhiyun 	.driver		= {
356*4882a593Smuzhiyun 		.name	= "tps65218",
357*4882a593Smuzhiyun 		.of_match_table = of_tps65218_match_table,
358*4882a593Smuzhiyun 	},
359*4882a593Smuzhiyun 	.probe		= tps65218_probe,
360*4882a593Smuzhiyun 	.id_table       = tps65218_id_table,
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun module_i2c_driver(tps65218_driver);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
366*4882a593Smuzhiyun MODULE_DESCRIPTION("TPS65218 chip family multi-function driver");
367*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
368