1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * tps65217.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * TPS65217 chip family multi-function driver
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
9*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
10*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
14*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15*4882a593Smuzhiyun * GNU General Public License for more details.
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/device.h>
19*4882a593Smuzhiyun #include <linux/err.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/irq.h>
24*4882a593Smuzhiyun #include <linux/irqdomain.h>
25*4882a593Smuzhiyun #include <linux/kernel.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/of.h>
28*4882a593Smuzhiyun #include <linux/of_device.h>
29*4882a593Smuzhiyun #include <linux/platform_device.h>
30*4882a593Smuzhiyun #include <linux/regmap.h>
31*4882a593Smuzhiyun #include <linux/slab.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <linux/mfd/core.h>
34*4882a593Smuzhiyun #include <linux/mfd/tps65217.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static struct resource charger_resources[] = {
37*4882a593Smuzhiyun DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_AC, "AC"),
38*4882a593Smuzhiyun DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_USB, "USB"),
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct resource pb_resources[] = {
42*4882a593Smuzhiyun DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_PB, "PB"),
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
tps65217_irq_lock(struct irq_data * data)45*4882a593Smuzhiyun static void tps65217_irq_lock(struct irq_data *data)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct tps65217 *tps = irq_data_get_irq_chip_data(data);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun mutex_lock(&tps->irq_lock);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
tps65217_irq_sync_unlock(struct irq_data * data)52*4882a593Smuzhiyun static void tps65217_irq_sync_unlock(struct irq_data *data)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct tps65217 *tps = irq_data_get_irq_chip_data(data);
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
58*4882a593Smuzhiyun tps->irq_mask, TPS65217_PROTECT_NONE);
59*4882a593Smuzhiyun if (ret != 0)
60*4882a593Smuzhiyun dev_err(tps->dev, "Failed to sync IRQ masks\n");
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun mutex_unlock(&tps->irq_lock);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
tps65217_irq_enable(struct irq_data * data)65*4882a593Smuzhiyun static void tps65217_irq_enable(struct irq_data *data)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct tps65217 *tps = irq_data_get_irq_chip_data(data);
68*4882a593Smuzhiyun u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun tps->irq_mask &= ~mask;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
tps65217_irq_disable(struct irq_data * data)73*4882a593Smuzhiyun static void tps65217_irq_disable(struct irq_data *data)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun struct tps65217 *tps = irq_data_get_irq_chip_data(data);
76*4882a593Smuzhiyun u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun tps->irq_mask |= mask;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static struct irq_chip tps65217_irq_chip = {
82*4882a593Smuzhiyun .name = "tps65217",
83*4882a593Smuzhiyun .irq_bus_lock = tps65217_irq_lock,
84*4882a593Smuzhiyun .irq_bus_sync_unlock = tps65217_irq_sync_unlock,
85*4882a593Smuzhiyun .irq_enable = tps65217_irq_enable,
86*4882a593Smuzhiyun .irq_disable = tps65217_irq_disable,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct mfd_cell tps65217s[] = {
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun .name = "tps65217-pmic",
92*4882a593Smuzhiyun .of_compatible = "ti,tps65217-pmic",
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun .name = "tps65217-bl",
96*4882a593Smuzhiyun .of_compatible = "ti,tps65217-bl",
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun .name = "tps65217-charger",
100*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(charger_resources),
101*4882a593Smuzhiyun .resources = charger_resources,
102*4882a593Smuzhiyun .of_compatible = "ti,tps65217-charger",
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun .name = "tps65217-pwrbutton",
106*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(pb_resources),
107*4882a593Smuzhiyun .resources = pb_resources,
108*4882a593Smuzhiyun .of_compatible = "ti,tps65217-pwrbutton",
109*4882a593Smuzhiyun },
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
tps65217_irq_thread(int irq,void * data)112*4882a593Smuzhiyun static irqreturn_t tps65217_irq_thread(int irq, void *data)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun struct tps65217 *tps = data;
115*4882a593Smuzhiyun unsigned int status;
116*4882a593Smuzhiyun bool handled = false;
117*4882a593Smuzhiyun int i;
118*4882a593Smuzhiyun int ret;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun ret = tps65217_reg_read(tps, TPS65217_REG_INT, &status);
121*4882a593Smuzhiyun if (ret < 0) {
122*4882a593Smuzhiyun dev_err(tps->dev, "Failed to read IRQ status: %d\n",
123*4882a593Smuzhiyun ret);
124*4882a593Smuzhiyun return IRQ_NONE;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun for (i = 0; i < TPS65217_NUM_IRQ; i++) {
128*4882a593Smuzhiyun if (status & BIT(i)) {
129*4882a593Smuzhiyun handle_nested_irq(irq_find_mapping(tps->irq_domain, i));
130*4882a593Smuzhiyun handled = true;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (handled)
135*4882a593Smuzhiyun return IRQ_HANDLED;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return IRQ_NONE;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
tps65217_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)140*4882a593Smuzhiyun static int tps65217_irq_map(struct irq_domain *h, unsigned int virq,
141*4882a593Smuzhiyun irq_hw_number_t hw)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct tps65217 *tps = h->host_data;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun irq_set_chip_data(virq, tps);
146*4882a593Smuzhiyun irq_set_chip_and_handler(virq, &tps65217_irq_chip, handle_edge_irq);
147*4882a593Smuzhiyun irq_set_nested_thread(virq, 1);
148*4882a593Smuzhiyun irq_set_parent(virq, tps->irq);
149*4882a593Smuzhiyun irq_set_noprobe(virq);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun return 0;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun static const struct irq_domain_ops tps65217_irq_domain_ops = {
155*4882a593Smuzhiyun .map = tps65217_irq_map,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
tps65217_irq_init(struct tps65217 * tps,int irq)158*4882a593Smuzhiyun static int tps65217_irq_init(struct tps65217 *tps, int irq)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun int ret;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun mutex_init(&tps->irq_lock);
163*4882a593Smuzhiyun tps->irq = irq;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Mask all interrupt sources */
166*4882a593Smuzhiyun tps->irq_mask = TPS65217_INT_MASK;
167*4882a593Smuzhiyun tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
168*4882a593Smuzhiyun TPS65217_INT_MASK, TPS65217_PROTECT_NONE);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun tps->irq_domain = irq_domain_add_linear(tps->dev->of_node,
171*4882a593Smuzhiyun TPS65217_NUM_IRQ, &tps65217_irq_domain_ops, tps);
172*4882a593Smuzhiyun if (!tps->irq_domain) {
173*4882a593Smuzhiyun dev_err(tps->dev, "Could not create IRQ domain\n");
174*4882a593Smuzhiyun return -ENOMEM;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ret = devm_request_threaded_irq(tps->dev, irq, NULL,
178*4882a593Smuzhiyun tps65217_irq_thread, IRQF_ONESHOT,
179*4882a593Smuzhiyun "tps65217-irq", tps);
180*4882a593Smuzhiyun if (ret) {
181*4882a593Smuzhiyun dev_err(tps->dev, "Failed to request IRQ %d: %d\n",
182*4882a593Smuzhiyun irq, ret);
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun enable_irq_wake(irq);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun return 0;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /**
192*4882a593Smuzhiyun * tps65217_reg_read: Read a single tps65217 register.
193*4882a593Smuzhiyun *
194*4882a593Smuzhiyun * @tps: Device to read from.
195*4882a593Smuzhiyun * @reg: Register to read.
196*4882a593Smuzhiyun * @val: Contians the value
197*4882a593Smuzhiyun */
tps65217_reg_read(struct tps65217 * tps,unsigned int reg,unsigned int * val)198*4882a593Smuzhiyun int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
199*4882a593Smuzhiyun unsigned int *val)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun return regmap_read(tps->regmap, reg, val);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65217_reg_read);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /**
206*4882a593Smuzhiyun * tps65217_reg_write: Write a single tps65217 register.
207*4882a593Smuzhiyun *
208*4882a593Smuzhiyun * @tps: Device to write to.
209*4882a593Smuzhiyun * @reg: Register to write to.
210*4882a593Smuzhiyun * @val: Value to write.
211*4882a593Smuzhiyun * @level: Password protected level
212*4882a593Smuzhiyun */
tps65217_reg_write(struct tps65217 * tps,unsigned int reg,unsigned int val,unsigned int level)213*4882a593Smuzhiyun int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
214*4882a593Smuzhiyun unsigned int val, unsigned int level)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun int ret;
217*4882a593Smuzhiyun unsigned int xor_reg_val;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun switch (level) {
220*4882a593Smuzhiyun case TPS65217_PROTECT_NONE:
221*4882a593Smuzhiyun return regmap_write(tps->regmap, reg, val);
222*4882a593Smuzhiyun case TPS65217_PROTECT_L1:
223*4882a593Smuzhiyun xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
224*4882a593Smuzhiyun ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
225*4882a593Smuzhiyun xor_reg_val);
226*4882a593Smuzhiyun if (ret < 0)
227*4882a593Smuzhiyun return ret;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return regmap_write(tps->regmap, reg, val);
230*4882a593Smuzhiyun case TPS65217_PROTECT_L2:
231*4882a593Smuzhiyun xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
232*4882a593Smuzhiyun ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
233*4882a593Smuzhiyun xor_reg_val);
234*4882a593Smuzhiyun if (ret < 0)
235*4882a593Smuzhiyun return ret;
236*4882a593Smuzhiyun ret = regmap_write(tps->regmap, reg, val);
237*4882a593Smuzhiyun if (ret < 0)
238*4882a593Smuzhiyun return ret;
239*4882a593Smuzhiyun ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
240*4882a593Smuzhiyun xor_reg_val);
241*4882a593Smuzhiyun if (ret < 0)
242*4882a593Smuzhiyun return ret;
243*4882a593Smuzhiyun return regmap_write(tps->regmap, reg, val);
244*4882a593Smuzhiyun default:
245*4882a593Smuzhiyun return -EINVAL;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65217_reg_write);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /**
251*4882a593Smuzhiyun * tps65217_update_bits: Modify bits w.r.t mask, val and level.
252*4882a593Smuzhiyun *
253*4882a593Smuzhiyun * @tps: Device to write to.
254*4882a593Smuzhiyun * @reg: Register to read-write to.
255*4882a593Smuzhiyun * @mask: Mask.
256*4882a593Smuzhiyun * @val: Value to write.
257*4882a593Smuzhiyun * @level: Password protected level
258*4882a593Smuzhiyun */
tps65217_update_bits(struct tps65217 * tps,unsigned int reg,unsigned int mask,unsigned int val,unsigned int level)259*4882a593Smuzhiyun static int tps65217_update_bits(struct tps65217 *tps, unsigned int reg,
260*4882a593Smuzhiyun unsigned int mask, unsigned int val, unsigned int level)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun int ret;
263*4882a593Smuzhiyun unsigned int data;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun ret = tps65217_reg_read(tps, reg, &data);
266*4882a593Smuzhiyun if (ret) {
267*4882a593Smuzhiyun dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
268*4882a593Smuzhiyun return ret;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun data &= ~mask;
272*4882a593Smuzhiyun data |= val & mask;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun ret = tps65217_reg_write(tps, reg, data, level);
275*4882a593Smuzhiyun if (ret)
276*4882a593Smuzhiyun dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun return ret;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
tps65217_set_bits(struct tps65217 * tps,unsigned int reg,unsigned int mask,unsigned int val,unsigned int level)281*4882a593Smuzhiyun int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
282*4882a593Smuzhiyun unsigned int mask, unsigned int val, unsigned int level)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun return tps65217_update_bits(tps, reg, mask, val, level);
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65217_set_bits);
287*4882a593Smuzhiyun
tps65217_clear_bits(struct tps65217 * tps,unsigned int reg,unsigned int mask,unsigned int level)288*4882a593Smuzhiyun int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
289*4882a593Smuzhiyun unsigned int mask, unsigned int level)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun return tps65217_update_bits(tps, reg, mask, 0, level);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(tps65217_clear_bits);
294*4882a593Smuzhiyun
tps65217_volatile_reg(struct device * dev,unsigned int reg)295*4882a593Smuzhiyun static bool tps65217_volatile_reg(struct device *dev, unsigned int reg)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun switch (reg) {
298*4882a593Smuzhiyun case TPS65217_REG_INT:
299*4882a593Smuzhiyun return true;
300*4882a593Smuzhiyun default:
301*4882a593Smuzhiyun return false;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun static const struct regmap_config tps65217_regmap_config = {
306*4882a593Smuzhiyun .reg_bits = 8,
307*4882a593Smuzhiyun .val_bits = 8,
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun .max_register = TPS65217_REG_MAX,
310*4882a593Smuzhiyun .volatile_reg = tps65217_volatile_reg,
311*4882a593Smuzhiyun };
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun static const struct of_device_id tps65217_of_match[] = {
314*4882a593Smuzhiyun { .compatible = "ti,tps65217"},
315*4882a593Smuzhiyun { /* sentinel */ },
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tps65217_of_match);
318*4882a593Smuzhiyun
tps65217_probe(struct i2c_client * client)319*4882a593Smuzhiyun static int tps65217_probe(struct i2c_client *client)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct tps65217 *tps;
322*4882a593Smuzhiyun unsigned int version;
323*4882a593Smuzhiyun bool status_off = false;
324*4882a593Smuzhiyun int ret;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun status_off = of_property_read_bool(client->dev.of_node,
327*4882a593Smuzhiyun "ti,pmic-shutdown-controller");
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
330*4882a593Smuzhiyun if (!tps)
331*4882a593Smuzhiyun return -ENOMEM;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun i2c_set_clientdata(client, tps);
334*4882a593Smuzhiyun tps->dev = &client->dev;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun tps->regmap = devm_regmap_init_i2c(client, &tps65217_regmap_config);
337*4882a593Smuzhiyun if (IS_ERR(tps->regmap)) {
338*4882a593Smuzhiyun ret = PTR_ERR(tps->regmap);
339*4882a593Smuzhiyun dev_err(tps->dev, "Failed to allocate register map: %d\n",
340*4882a593Smuzhiyun ret);
341*4882a593Smuzhiyun return ret;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun if (client->irq) {
345*4882a593Smuzhiyun tps65217_irq_init(tps, client->irq);
346*4882a593Smuzhiyun } else {
347*4882a593Smuzhiyun int i;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun /* Don't tell children about IRQ resources which won't fire */
350*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(tps65217s); i++)
351*4882a593Smuzhiyun tps65217s[i].num_resources = 0;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun ret = devm_mfd_add_devices(tps->dev, -1, tps65217s,
355*4882a593Smuzhiyun ARRAY_SIZE(tps65217s), NULL, 0,
356*4882a593Smuzhiyun tps->irq_domain);
357*4882a593Smuzhiyun if (ret < 0) {
358*4882a593Smuzhiyun dev_err(tps->dev, "mfd_add_devices failed: %d\n", ret);
359*4882a593Smuzhiyun return ret;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun ret = tps65217_reg_read(tps, TPS65217_REG_CHIPID, &version);
363*4882a593Smuzhiyun if (ret < 0) {
364*4882a593Smuzhiyun dev_err(tps->dev, "Failed to read revision register: %d\n",
365*4882a593Smuzhiyun ret);
366*4882a593Smuzhiyun return ret;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun /* Set the PMIC to shutdown on PWR_EN toggle */
370*4882a593Smuzhiyun if (status_off) {
371*4882a593Smuzhiyun ret = tps65217_set_bits(tps, TPS65217_REG_STATUS,
372*4882a593Smuzhiyun TPS65217_STATUS_OFF, TPS65217_STATUS_OFF,
373*4882a593Smuzhiyun TPS65217_PROTECT_NONE);
374*4882a593Smuzhiyun if (ret)
375*4882a593Smuzhiyun dev_warn(tps->dev, "unable to set the status OFF\n");
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun dev_info(tps->dev, "TPS65217 ID %#x version 1.%d\n",
379*4882a593Smuzhiyun (version & TPS65217_CHIPID_CHIP_MASK) >> 4,
380*4882a593Smuzhiyun version & TPS65217_CHIPID_REV_MASK);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun return 0;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
tps65217_remove(struct i2c_client * client)385*4882a593Smuzhiyun static int tps65217_remove(struct i2c_client *client)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun struct tps65217 *tps = i2c_get_clientdata(client);
388*4882a593Smuzhiyun unsigned int virq;
389*4882a593Smuzhiyun int i;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun for (i = 0; i < TPS65217_NUM_IRQ; i++) {
392*4882a593Smuzhiyun virq = irq_find_mapping(tps->irq_domain, i);
393*4882a593Smuzhiyun if (virq)
394*4882a593Smuzhiyun irq_dispose_mapping(virq);
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun irq_domain_remove(tps->irq_domain);
398*4882a593Smuzhiyun tps->irq_domain = NULL;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun return 0;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun static const struct i2c_device_id tps65217_id_table[] = {
404*4882a593Smuzhiyun {"tps65217", TPS65217},
405*4882a593Smuzhiyun { /* sentinel */ }
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, tps65217_id_table);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun static struct i2c_driver tps65217_driver = {
410*4882a593Smuzhiyun .driver = {
411*4882a593Smuzhiyun .name = "tps65217",
412*4882a593Smuzhiyun .of_match_table = tps65217_of_match,
413*4882a593Smuzhiyun },
414*4882a593Smuzhiyun .id_table = tps65217_id_table,
415*4882a593Smuzhiyun .probe_new = tps65217_probe,
416*4882a593Smuzhiyun .remove = tps65217_remove,
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun
tps65217_init(void)419*4882a593Smuzhiyun static int __init tps65217_init(void)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun return i2c_add_driver(&tps65217_driver);
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun subsys_initcall(tps65217_init);
424*4882a593Smuzhiyun
tps65217_exit(void)425*4882a593Smuzhiyun static void __exit tps65217_exit(void)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun i2c_del_driver(&tps65217_driver);
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun module_exit(tps65217_exit);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun MODULE_AUTHOR("AnilKumar Ch <anilkumar@ti.com>");
432*4882a593Smuzhiyun MODULE_DESCRIPTION("TPS65217 chip family multi-function driver");
433*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
434