1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Core driver for TI TPS65090 PMIC family
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Venu Byravarasu <vbyravarasu@nvidia.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/mutex.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/mfd/core.h>
18*4882a593Smuzhiyun #include <linux/mfd/tps65090.h>
19*4882a593Smuzhiyun #include <linux/of.h>
20*4882a593Smuzhiyun #include <linux/of_device.h>
21*4882a593Smuzhiyun #include <linux/err.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define NUM_INT_REG 2
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define TPS65090_INT1_MASK_VAC_STATUS_CHANGE 1
26*4882a593Smuzhiyun #define TPS65090_INT1_MASK_VSYS_STATUS_CHANGE 2
27*4882a593Smuzhiyun #define TPS65090_INT1_MASK_BAT_STATUS_CHANGE 3
28*4882a593Smuzhiyun #define TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE 4
29*4882a593Smuzhiyun #define TPS65090_INT1_MASK_CHARGING_COMPLETE 5
30*4882a593Smuzhiyun #define TPS65090_INT1_MASK_OVERLOAD_DCDC1 6
31*4882a593Smuzhiyun #define TPS65090_INT1_MASK_OVERLOAD_DCDC2 7
32*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_DCDC3 0
33*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET1 1
34*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET2 2
35*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET3 3
36*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET4 4
37*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET5 5
38*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET6 6
39*4882a593Smuzhiyun #define TPS65090_INT2_MASK_OVERLOAD_FET7 7
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct resource charger_resources[] = {
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun .start = TPS65090_IRQ_VAC_STATUS_CHANGE,
44*4882a593Smuzhiyun .end = TPS65090_IRQ_VAC_STATUS_CHANGE,
45*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun enum tps65090_cells {
50*4882a593Smuzhiyun PMIC = 0,
51*4882a593Smuzhiyun CHARGER = 1,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static struct mfd_cell tps65090s[] = {
55*4882a593Smuzhiyun [PMIC] = {
56*4882a593Smuzhiyun .name = "tps65090-pmic",
57*4882a593Smuzhiyun },
58*4882a593Smuzhiyun [CHARGER] = {
59*4882a593Smuzhiyun .name = "tps65090-charger",
60*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(charger_resources),
61*4882a593Smuzhiyun .resources = &charger_resources[0],
62*4882a593Smuzhiyun .of_compatible = "ti,tps65090-charger",
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static const struct regmap_irq tps65090_irqs[] = {
67*4882a593Smuzhiyun /* INT1 IRQs*/
68*4882a593Smuzhiyun [TPS65090_IRQ_VAC_STATUS_CHANGE] = {
69*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_VAC_STATUS_CHANGE,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun [TPS65090_IRQ_VSYS_STATUS_CHANGE] = {
72*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_VSYS_STATUS_CHANGE,
73*4882a593Smuzhiyun },
74*4882a593Smuzhiyun [TPS65090_IRQ_BAT_STATUS_CHANGE] = {
75*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_BAT_STATUS_CHANGE,
76*4882a593Smuzhiyun },
77*4882a593Smuzhiyun [TPS65090_IRQ_CHARGING_STATUS_CHANGE] = {
78*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun [TPS65090_IRQ_CHARGING_COMPLETE] = {
81*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_CHARGING_COMPLETE,
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_DCDC1] = {
84*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_OVERLOAD_DCDC1,
85*4882a593Smuzhiyun },
86*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_DCDC2] = {
87*4882a593Smuzhiyun .mask = TPS65090_INT1_MASK_OVERLOAD_DCDC2,
88*4882a593Smuzhiyun },
89*4882a593Smuzhiyun /* INT2 IRQs*/
90*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_DCDC3] = {
91*4882a593Smuzhiyun .reg_offset = 1,
92*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_DCDC3,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET1] = {
95*4882a593Smuzhiyun .reg_offset = 1,
96*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET1,
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET2] = {
99*4882a593Smuzhiyun .reg_offset = 1,
100*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET2,
101*4882a593Smuzhiyun },
102*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET3] = {
103*4882a593Smuzhiyun .reg_offset = 1,
104*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET3,
105*4882a593Smuzhiyun },
106*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET4] = {
107*4882a593Smuzhiyun .reg_offset = 1,
108*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET4,
109*4882a593Smuzhiyun },
110*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET5] = {
111*4882a593Smuzhiyun .reg_offset = 1,
112*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET5,
113*4882a593Smuzhiyun },
114*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET6] = {
115*4882a593Smuzhiyun .reg_offset = 1,
116*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET6,
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun [TPS65090_IRQ_OVERLOAD_FET7] = {
119*4882a593Smuzhiyun .reg_offset = 1,
120*4882a593Smuzhiyun .mask = TPS65090_INT2_MASK_OVERLOAD_FET7,
121*4882a593Smuzhiyun },
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static struct regmap_irq_chip tps65090_irq_chip = {
125*4882a593Smuzhiyun .name = "tps65090",
126*4882a593Smuzhiyun .irqs = tps65090_irqs,
127*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(tps65090_irqs),
128*4882a593Smuzhiyun .num_regs = NUM_INT_REG,
129*4882a593Smuzhiyun .status_base = TPS65090_REG_INTR_STS,
130*4882a593Smuzhiyun .mask_base = TPS65090_REG_INTR_MASK,
131*4882a593Smuzhiyun .mask_invert = true,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
is_volatile_reg(struct device * dev,unsigned int reg)134*4882a593Smuzhiyun static bool is_volatile_reg(struct device *dev, unsigned int reg)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun /* Nearly all registers have status bits mixed in, except a few */
137*4882a593Smuzhiyun switch (reg) {
138*4882a593Smuzhiyun case TPS65090_REG_INTR_MASK:
139*4882a593Smuzhiyun case TPS65090_REG_INTR_MASK2:
140*4882a593Smuzhiyun case TPS65090_REG_CG_CTRL0:
141*4882a593Smuzhiyun case TPS65090_REG_CG_CTRL1:
142*4882a593Smuzhiyun case TPS65090_REG_CG_CTRL2:
143*4882a593Smuzhiyun case TPS65090_REG_CG_CTRL3:
144*4882a593Smuzhiyun case TPS65090_REG_CG_CTRL4:
145*4882a593Smuzhiyun case TPS65090_REG_CG_CTRL5:
146*4882a593Smuzhiyun return false;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun return true;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct regmap_config tps65090_regmap_config = {
152*4882a593Smuzhiyun .reg_bits = 8,
153*4882a593Smuzhiyun .val_bits = 8,
154*4882a593Smuzhiyun .max_register = TPS65090_MAX_REG,
155*4882a593Smuzhiyun .num_reg_defaults_raw = TPS65090_NUM_REGS,
156*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
157*4882a593Smuzhiyun .volatile_reg = is_volatile_reg,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #ifdef CONFIG_OF
161*4882a593Smuzhiyun static const struct of_device_id tps65090_of_match[] = {
162*4882a593Smuzhiyun { .compatible = "ti,tps65090",},
163*4882a593Smuzhiyun {},
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun #endif
166*4882a593Smuzhiyun
tps65090_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)167*4882a593Smuzhiyun static int tps65090_i2c_probe(struct i2c_client *client,
168*4882a593Smuzhiyun const struct i2c_device_id *id)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun struct tps65090_platform_data *pdata = dev_get_platdata(&client->dev);
171*4882a593Smuzhiyun int irq_base = 0;
172*4882a593Smuzhiyun struct tps65090 *tps65090;
173*4882a593Smuzhiyun int ret;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (!pdata && !client->dev.of_node) {
176*4882a593Smuzhiyun dev_err(&client->dev,
177*4882a593Smuzhiyun "tps65090 requires platform data or of_node\n");
178*4882a593Smuzhiyun return -EINVAL;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (pdata)
182*4882a593Smuzhiyun irq_base = pdata->irq_base;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun tps65090 = devm_kzalloc(&client->dev, sizeof(*tps65090), GFP_KERNEL);
185*4882a593Smuzhiyun if (!tps65090)
186*4882a593Smuzhiyun return -ENOMEM;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun tps65090->dev = &client->dev;
189*4882a593Smuzhiyun i2c_set_clientdata(client, tps65090);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun tps65090->rmap = devm_regmap_init_i2c(client, &tps65090_regmap_config);
192*4882a593Smuzhiyun if (IS_ERR(tps65090->rmap)) {
193*4882a593Smuzhiyun ret = PTR_ERR(tps65090->rmap);
194*4882a593Smuzhiyun dev_err(&client->dev, "regmap_init failed with err: %d\n", ret);
195*4882a593Smuzhiyun return ret;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (client->irq) {
199*4882a593Smuzhiyun ret = regmap_add_irq_chip(tps65090->rmap, client->irq,
200*4882a593Smuzhiyun IRQF_ONESHOT | IRQF_TRIGGER_LOW, irq_base,
201*4882a593Smuzhiyun &tps65090_irq_chip, &tps65090->irq_data);
202*4882a593Smuzhiyun if (ret) {
203*4882a593Smuzhiyun dev_err(&client->dev,
204*4882a593Smuzhiyun "IRQ init failed with err: %d\n", ret);
205*4882a593Smuzhiyun return ret;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun } else {
208*4882a593Smuzhiyun /* Don't tell children they have an IRQ that'll never fire */
209*4882a593Smuzhiyun tps65090s[CHARGER].num_resources = 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun ret = mfd_add_devices(tps65090->dev, -1, tps65090s,
213*4882a593Smuzhiyun ARRAY_SIZE(tps65090s), NULL,
214*4882a593Smuzhiyun 0, regmap_irq_get_domain(tps65090->irq_data));
215*4882a593Smuzhiyun if (ret) {
216*4882a593Smuzhiyun dev_err(&client->dev, "add mfd devices failed with err: %d\n",
217*4882a593Smuzhiyun ret);
218*4882a593Smuzhiyun goto err_irq_exit;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun return 0;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun err_irq_exit:
224*4882a593Smuzhiyun if (client->irq)
225*4882a593Smuzhiyun regmap_del_irq_chip(client->irq, tps65090->irq_data);
226*4882a593Smuzhiyun return ret;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun static const struct i2c_device_id tps65090_id_table[] = {
231*4882a593Smuzhiyun { "tps65090", 0 },
232*4882a593Smuzhiyun { },
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static struct i2c_driver tps65090_driver = {
236*4882a593Smuzhiyun .driver = {
237*4882a593Smuzhiyun .name = "tps65090",
238*4882a593Smuzhiyun .suppress_bind_attrs = true,
239*4882a593Smuzhiyun .of_match_table = of_match_ptr(tps65090_of_match),
240*4882a593Smuzhiyun },
241*4882a593Smuzhiyun .probe = tps65090_i2c_probe,
242*4882a593Smuzhiyun .id_table = tps65090_id_table,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
tps65090_init(void)245*4882a593Smuzhiyun static int __init tps65090_init(void)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun return i2c_add_driver(&tps65090_driver);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun subsys_initcall(tps65090_init);
250