1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * timberdale.h timberdale FPGA MFD driver defines 4*4882a593Smuzhiyun * Copyright (c) 2009 Intel Corporation 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Supports: 8*4882a593Smuzhiyun * Timberdale FPGA 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef MFD_TIMBERDALE_H 12*4882a593Smuzhiyun #define MFD_TIMBERDALE_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DRV_VERSION "0.3" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* This driver only support versions >= 3.8 and < 4.0 */ 17*4882a593Smuzhiyun #define TIMB_SUPPORTED_MAJOR 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* This driver only support minor >= 8 */ 20*4882a593Smuzhiyun #define TIMB_REQUIRED_MINOR 8 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Registers of the control area */ 23*4882a593Smuzhiyun #define TIMB_REV_MAJOR 0x00 24*4882a593Smuzhiyun #define TIMB_REV_MINOR 0x04 25*4882a593Smuzhiyun #define TIMB_HW_CONFIG 0x08 26*4882a593Smuzhiyun #define TIMB_SW_RST 0x40 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* bits in the TIMB_HW_CONFIG register */ 29*4882a593Smuzhiyun #define TIMB_HW_CONFIG_SPI_8BIT 0x80 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define TIMB_HW_VER_MASK 0x0f 32*4882a593Smuzhiyun #define TIMB_HW_VER0 0x00 33*4882a593Smuzhiyun #define TIMB_HW_VER1 0x01 34*4882a593Smuzhiyun #define TIMB_HW_VER2 0x02 35*4882a593Smuzhiyun #define TIMB_HW_VER3 0x03 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define OCORESOFFSET 0x0 38*4882a593Smuzhiyun #define OCORESEND 0x1f 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define SPIOFFSET 0x80 41*4882a593Smuzhiyun #define SPIEND 0xff 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define UARTLITEOFFSET 0x100 44*4882a593Smuzhiyun #define UARTLITEEND 0x10f 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define RDSOFFSET 0x180 47*4882a593Smuzhiyun #define RDSEND 0x183 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define ETHOFFSET 0x300 50*4882a593Smuzhiyun #define ETHEND 0x3ff 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define GPIOOFFSET 0x400 53*4882a593Smuzhiyun #define GPIOEND 0x7ff 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CHIPCTLOFFSET 0x800 56*4882a593Smuzhiyun #define CHIPCTLEND 0x8ff 57*4882a593Smuzhiyun #define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define INTCOFFSET 0xc00 60*4882a593Smuzhiyun #define INTCEND 0xfff 61*4882a593Smuzhiyun #define INTCSIZE (INTCEND - INTCOFFSET) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define MOSTOFFSET 0x1000 64*4882a593Smuzhiyun #define MOSTEND 0x13ff 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define UARTOFFSET 0x1400 67*4882a593Smuzhiyun #define UARTEND 0x17ff 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define XIICOFFSET 0x1800 70*4882a593Smuzhiyun #define XIICEND 0x19ff 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define I2SOFFSET 0x1C00 73*4882a593Smuzhiyun #define I2SEND 0x1fff 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define LOGIWOFFSET 0x30000 76*4882a593Smuzhiyun #define LOGIWEND 0x37fff 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define MLCOREOFFSET 0x40000 79*4882a593Smuzhiyun #define MLCOREEND 0x43fff 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define DMAOFFSET 0x01000000 82*4882a593Smuzhiyun #define DMAEND 0x013fffff 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* SDHC0 is placed in PCI bar 1 */ 85*4882a593Smuzhiyun #define SDHC0OFFSET 0x00 86*4882a593Smuzhiyun #define SDHC0END 0xff 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* SDHC1 is placed in PCI bar 2 */ 89*4882a593Smuzhiyun #define SDHC1OFFSET 0x00 90*4882a593Smuzhiyun #define SDHC1END 0xff 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define PCI_VENDOR_ID_TIMB 0x10ee 93*4882a593Smuzhiyun #define PCI_DEVICE_ID_TIMB 0xa123 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define IRQ_TIMBERDALE_INIC 0 96*4882a593Smuzhiyun #define IRQ_TIMBERDALE_MLB 1 97*4882a593Smuzhiyun #define IRQ_TIMBERDALE_GPIO 2 98*4882a593Smuzhiyun #define IRQ_TIMBERDALE_I2C 3 99*4882a593Smuzhiyun #define IRQ_TIMBERDALE_UART 4 100*4882a593Smuzhiyun #define IRQ_TIMBERDALE_DMA 5 101*4882a593Smuzhiyun #define IRQ_TIMBERDALE_I2S 6 102*4882a593Smuzhiyun #define IRQ_TIMBERDALE_TSC_INT 7 103*4882a593Smuzhiyun #define IRQ_TIMBERDALE_SDHC 8 104*4882a593Smuzhiyun #define IRQ_TIMBERDALE_ADV7180 9 105*4882a593Smuzhiyun #define IRQ_TIMBERDALE_ETHSW_IF 10 106*4882a593Smuzhiyun #define IRQ_TIMBERDALE_SPI 11 107*4882a593Smuzhiyun #define IRQ_TIMBERDALE_UARTLITE 12 108*4882a593Smuzhiyun #define IRQ_TIMBERDALE_MLCORE 13 109*4882a593Smuzhiyun #define IRQ_TIMBERDALE_MLCORE_BUF 14 110*4882a593Smuzhiyun #define IRQ_TIMBERDALE_RDS 15 111*4882a593Smuzhiyun #define TIMBERDALE_NR_IRQS 16 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define GPIO_PIN_ASCB 8 114*4882a593Smuzhiyun #define GPIO_PIN_INIC_RST 14 115*4882a593Smuzhiyun #define GPIO_PIN_BT_RST 15 116*4882a593Smuzhiyun #define GPIO_NR_PINS 16 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* DMA Channels */ 119*4882a593Smuzhiyun #define DMA_UART_RX 0 120*4882a593Smuzhiyun #define DMA_UART_TX 1 121*4882a593Smuzhiyun #define DMA_MLB_RX 2 122*4882a593Smuzhiyun #define DMA_MLB_TX 3 123*4882a593Smuzhiyun #define DMA_VIDEO_RX 4 124*4882a593Smuzhiyun #define DMA_VIDEO_DROP 5 125*4882a593Smuzhiyun #define DMA_SDHCI_RX 6 126*4882a593Smuzhiyun #define DMA_SDHCI_TX 7 127*4882a593Smuzhiyun #define DMA_ETH_RX 8 128*4882a593Smuzhiyun #define DMA_ETH_TX 9 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif 131