1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Toshiba T7L66XB core mfd support
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (c) 2005, 2007, 2008 Ian Molton
7*4882a593Smuzhiyun * Copyright (c) 2008 Dmitry Baryshkov
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * T7L66 features:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Supported in this driver:
12*4882a593Smuzhiyun * SD/MMC
13*4882a593Smuzhiyun * SM/NAND flash controller
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * As yet not supported
16*4882a593Smuzhiyun * GPIO interface (on NAND pins)
17*4882a593Smuzhiyun * Serial interface
18*4882a593Smuzhiyun * TFT 'interface converter'
19*4882a593Smuzhiyun * PCMCIA interface logic
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <linux/kernel.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/err.h>
25*4882a593Smuzhiyun #include <linux/io.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun #include <linux/irq.h>
28*4882a593Smuzhiyun #include <linux/clk.h>
29*4882a593Smuzhiyun #include <linux/platform_device.h>
30*4882a593Smuzhiyun #include <linux/mfd/core.h>
31*4882a593Smuzhiyun #include <linux/mfd/tmio.h>
32*4882a593Smuzhiyun #include <linux/mfd/t7l66xb.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun enum {
35*4882a593Smuzhiyun T7L66XB_CELL_NAND,
36*4882a593Smuzhiyun T7L66XB_CELL_MMC,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const struct resource t7l66xb_mmc_resources[] = {
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun .start = 0x800,
42*4882a593Smuzhiyun .end = 0x9ff,
43*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
44*4882a593Smuzhiyun },
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun .start = IRQ_T7L66XB_MMC,
47*4882a593Smuzhiyun .end = IRQ_T7L66XB_MMC,
48*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
49*4882a593Smuzhiyun },
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define SCR_REVID 0x08 /* b Revision ID */
53*4882a593Smuzhiyun #define SCR_IMR 0x42 /* b Interrupt Mask */
54*4882a593Smuzhiyun #define SCR_DEV_CTL 0xe0 /* b Device control */
55*4882a593Smuzhiyun #define SCR_ISR 0xe1 /* b Interrupt Status */
56*4882a593Smuzhiyun #define SCR_GPO_OC 0xf0 /* b GPO output control */
57*4882a593Smuzhiyun #define SCR_GPO_OS 0xf1 /* b GPO output enable */
58*4882a593Smuzhiyun #define SCR_GPI_S 0xf2 /* w GPI status */
59*4882a593Smuzhiyun #define SCR_APDC 0xf8 /* b Active pullup down ctrl */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define SCR_DEV_CTL_USB BIT(0) /* USB enable */
62*4882a593Smuzhiyun #define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun struct t7l66xb {
67*4882a593Smuzhiyun void __iomem *scr;
68*4882a593Smuzhiyun /* Lock to protect registers requiring read/modify/write ops. */
69*4882a593Smuzhiyun raw_spinlock_t lock;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct resource rscr;
72*4882a593Smuzhiyun struct clk *clk48m;
73*4882a593Smuzhiyun struct clk *clk32k;
74*4882a593Smuzhiyun int irq;
75*4882a593Smuzhiyun int irq_base;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
79*4882a593Smuzhiyun
t7l66xb_mmc_enable(struct platform_device * mmc)80*4882a593Smuzhiyun static int t7l66xb_mmc_enable(struct platform_device *mmc)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
83*4882a593Smuzhiyun unsigned long flags;
84*4882a593Smuzhiyun u8 dev_ctl;
85*4882a593Smuzhiyun int ret;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun ret = clk_prepare_enable(t7l66xb->clk32k);
88*4882a593Smuzhiyun if (ret)
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun raw_spin_lock_irqsave(&t7l66xb->lock, flags);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
94*4882a593Smuzhiyun dev_ctl |= SCR_DEV_CTL_MMC;
95*4882a593Smuzhiyun tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
100*4882a593Smuzhiyun t7l66xb_mmc_resources[0].start & 0xfffe);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
t7l66xb_mmc_disable(struct platform_device * mmc)105*4882a593Smuzhiyun static int t7l66xb_mmc_disable(struct platform_device *mmc)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
108*4882a593Smuzhiyun unsigned long flags;
109*4882a593Smuzhiyun u8 dev_ctl;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun raw_spin_lock_irqsave(&t7l66xb->lock, flags);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
114*4882a593Smuzhiyun dev_ctl &= ~SCR_DEV_CTL_MMC;
115*4882a593Smuzhiyun tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun clk_disable_unprepare(t7l66xb->clk32k);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
t7l66xb_mmc_pwr(struct platform_device * mmc,int state)124*4882a593Smuzhiyun static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
t7l66xb_mmc_clk_div(struct platform_device * mmc,int state)131*4882a593Smuzhiyun static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun static struct tmio_mmc_data t7166xb_mmc_data = {
141*4882a593Smuzhiyun .hclk = 24000000,
142*4882a593Smuzhiyun .set_pwr = t7l66xb_mmc_pwr,
143*4882a593Smuzhiyun .set_clk_div = t7l66xb_mmc_clk_div,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static const struct resource t7l66xb_nand_resources[] = {
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun .start = 0xc00,
149*4882a593Smuzhiyun .end = 0xc07,
150*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun .start = 0x0100,
154*4882a593Smuzhiyun .end = 0x01ff,
155*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
156*4882a593Smuzhiyun },
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun .start = IRQ_T7L66XB_NAND,
159*4882a593Smuzhiyun .end = IRQ_T7L66XB_NAND,
160*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
161*4882a593Smuzhiyun },
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static struct mfd_cell t7l66xb_cells[] = {
165*4882a593Smuzhiyun [T7L66XB_CELL_MMC] = {
166*4882a593Smuzhiyun .name = "tmio-mmc",
167*4882a593Smuzhiyun .enable = t7l66xb_mmc_enable,
168*4882a593Smuzhiyun .disable = t7l66xb_mmc_disable,
169*4882a593Smuzhiyun .platform_data = &t7166xb_mmc_data,
170*4882a593Smuzhiyun .pdata_size = sizeof(t7166xb_mmc_data),
171*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
172*4882a593Smuzhiyun .resources = t7l66xb_mmc_resources,
173*4882a593Smuzhiyun },
174*4882a593Smuzhiyun [T7L66XB_CELL_NAND] = {
175*4882a593Smuzhiyun .name = "tmio-nand",
176*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
177*4882a593Smuzhiyun .resources = t7l66xb_nand_resources,
178*4882a593Smuzhiyun },
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* Handle the T7L66XB interrupt mux */
t7l66xb_irq(struct irq_desc * desc)184*4882a593Smuzhiyun static void t7l66xb_irq(struct irq_desc *desc)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
187*4882a593Smuzhiyun unsigned int isr;
188*4882a593Smuzhiyun unsigned int i, irq_base;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun irq_base = t7l66xb->irq_base;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
193*4882a593Smuzhiyun ~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
194*4882a593Smuzhiyun for (i = 0; i < T7L66XB_NR_IRQS; i++)
195*4882a593Smuzhiyun if (isr & (1 << i))
196*4882a593Smuzhiyun generic_handle_irq(irq_base + i);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
t7l66xb_irq_mask(struct irq_data * data)199*4882a593Smuzhiyun static void t7l66xb_irq_mask(struct irq_data *data)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
202*4882a593Smuzhiyun unsigned long flags;
203*4882a593Smuzhiyun u8 imr;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun raw_spin_lock_irqsave(&t7l66xb->lock, flags);
206*4882a593Smuzhiyun imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
207*4882a593Smuzhiyun imr |= 1 << (data->irq - t7l66xb->irq_base);
208*4882a593Smuzhiyun tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
209*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
t7l66xb_irq_unmask(struct irq_data * data)212*4882a593Smuzhiyun static void t7l66xb_irq_unmask(struct irq_data *data)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
215*4882a593Smuzhiyun unsigned long flags;
216*4882a593Smuzhiyun u8 imr;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun raw_spin_lock_irqsave(&t7l66xb->lock, flags);
219*4882a593Smuzhiyun imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
220*4882a593Smuzhiyun imr &= ~(1 << (data->irq - t7l66xb->irq_base));
221*4882a593Smuzhiyun tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
222*4882a593Smuzhiyun raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static struct irq_chip t7l66xb_chip = {
226*4882a593Smuzhiyun .name = "t7l66xb",
227*4882a593Smuzhiyun .irq_ack = t7l66xb_irq_mask,
228*4882a593Smuzhiyun .irq_mask = t7l66xb_irq_mask,
229*4882a593Smuzhiyun .irq_unmask = t7l66xb_irq_unmask,
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* Install the IRQ handler */
t7l66xb_attach_irq(struct platform_device * dev)235*4882a593Smuzhiyun static void t7l66xb_attach_irq(struct platform_device *dev)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
238*4882a593Smuzhiyun unsigned int irq, irq_base;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun irq_base = t7l66xb->irq_base;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
243*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
244*4882a593Smuzhiyun irq_set_chip_data(irq, t7l66xb);
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
248*4882a593Smuzhiyun irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
t7l66xb_detach_irq(struct platform_device * dev)251*4882a593Smuzhiyun static void t7l66xb_detach_irq(struct platform_device *dev)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
254*4882a593Smuzhiyun unsigned int irq, irq_base;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun irq_base = t7l66xb->irq_base;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
261*4882a593Smuzhiyun irq_set_chip(irq, NULL);
262*4882a593Smuzhiyun irq_set_chip_data(irq, NULL);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun #ifdef CONFIG_PM
t7l66xb_suspend(struct platform_device * dev,pm_message_t state)269*4882a593Smuzhiyun static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
272*4882a593Smuzhiyun struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (pdata && pdata->suspend)
275*4882a593Smuzhiyun pdata->suspend(dev);
276*4882a593Smuzhiyun clk_disable_unprepare(t7l66xb->clk48m);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun return 0;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
t7l66xb_resume(struct platform_device * dev)281*4882a593Smuzhiyun static int t7l66xb_resume(struct platform_device *dev)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
284*4882a593Smuzhiyun struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
285*4882a593Smuzhiyun int ret;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun ret = clk_prepare_enable(t7l66xb->clk48m);
288*4882a593Smuzhiyun if (ret)
289*4882a593Smuzhiyun return ret;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if (pdata && pdata->resume)
292*4882a593Smuzhiyun pdata->resume(dev);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
295*4882a593Smuzhiyun t7l66xb_mmc_resources[0].start & 0xfffe);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun #else
300*4882a593Smuzhiyun #define t7l66xb_suspend NULL
301*4882a593Smuzhiyun #define t7l66xb_resume NULL
302*4882a593Smuzhiyun #endif
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
305*4882a593Smuzhiyun
t7l66xb_probe(struct platform_device * dev)306*4882a593Smuzhiyun static int t7l66xb_probe(struct platform_device *dev)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
309*4882a593Smuzhiyun struct t7l66xb *t7l66xb;
310*4882a593Smuzhiyun struct resource *iomem, *rscr;
311*4882a593Smuzhiyun int ret;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (!pdata)
314*4882a593Smuzhiyun return -EINVAL;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
317*4882a593Smuzhiyun if (!iomem)
318*4882a593Smuzhiyun return -EINVAL;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
321*4882a593Smuzhiyun if (!t7l66xb)
322*4882a593Smuzhiyun return -ENOMEM;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun raw_spin_lock_init(&t7l66xb->lock);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun platform_set_drvdata(dev, t7l66xb);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun ret = platform_get_irq(dev, 0);
329*4882a593Smuzhiyun if (ret >= 0)
330*4882a593Smuzhiyun t7l66xb->irq = ret;
331*4882a593Smuzhiyun else
332*4882a593Smuzhiyun goto err_noirq;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun t7l66xb->irq_base = pdata->irq_base;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
337*4882a593Smuzhiyun if (IS_ERR(t7l66xb->clk32k)) {
338*4882a593Smuzhiyun ret = PTR_ERR(t7l66xb->clk32k);
339*4882a593Smuzhiyun goto err_clk32k_get;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
343*4882a593Smuzhiyun if (IS_ERR(t7l66xb->clk48m)) {
344*4882a593Smuzhiyun ret = PTR_ERR(t7l66xb->clk48m);
345*4882a593Smuzhiyun goto err_clk48m_get;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun rscr = &t7l66xb->rscr;
349*4882a593Smuzhiyun rscr->name = "t7l66xb-core";
350*4882a593Smuzhiyun rscr->start = iomem->start;
351*4882a593Smuzhiyun rscr->end = iomem->start + 0xff;
352*4882a593Smuzhiyun rscr->flags = IORESOURCE_MEM;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun ret = request_resource(iomem, rscr);
355*4882a593Smuzhiyun if (ret)
356*4882a593Smuzhiyun goto err_request_scr;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
359*4882a593Smuzhiyun if (!t7l66xb->scr) {
360*4882a593Smuzhiyun ret = -ENOMEM;
361*4882a593Smuzhiyun goto err_ioremap;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun ret = clk_prepare_enable(t7l66xb->clk48m);
365*4882a593Smuzhiyun if (ret)
366*4882a593Smuzhiyun goto err_clk_enable;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun if (pdata->enable)
369*4882a593Smuzhiyun pdata->enable(dev);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun /* Mask all interrupts */
372*4882a593Smuzhiyun tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
375*4882a593Smuzhiyun dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
376*4882a593Smuzhiyun (unsigned long)iomem->start, t7l66xb->irq);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun t7l66xb_attach_irq(dev);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
381*4882a593Smuzhiyun t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun ret = mfd_add_devices(&dev->dev, dev->id,
384*4882a593Smuzhiyun t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
385*4882a593Smuzhiyun iomem, t7l66xb->irq_base, NULL);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun if (!ret)
388*4882a593Smuzhiyun return 0;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun t7l66xb_detach_irq(dev);
391*4882a593Smuzhiyun clk_disable_unprepare(t7l66xb->clk48m);
392*4882a593Smuzhiyun err_clk_enable:
393*4882a593Smuzhiyun iounmap(t7l66xb->scr);
394*4882a593Smuzhiyun err_ioremap:
395*4882a593Smuzhiyun release_resource(&t7l66xb->rscr);
396*4882a593Smuzhiyun err_request_scr:
397*4882a593Smuzhiyun clk_put(t7l66xb->clk48m);
398*4882a593Smuzhiyun err_clk48m_get:
399*4882a593Smuzhiyun clk_put(t7l66xb->clk32k);
400*4882a593Smuzhiyun err_clk32k_get:
401*4882a593Smuzhiyun err_noirq:
402*4882a593Smuzhiyun kfree(t7l66xb);
403*4882a593Smuzhiyun return ret;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
t7l66xb_remove(struct platform_device * dev)406*4882a593Smuzhiyun static int t7l66xb_remove(struct platform_device *dev)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun clk_disable_unprepare(t7l66xb->clk48m);
411*4882a593Smuzhiyun clk_put(t7l66xb->clk48m);
412*4882a593Smuzhiyun clk_disable_unprepare(t7l66xb->clk32k);
413*4882a593Smuzhiyun clk_put(t7l66xb->clk32k);
414*4882a593Smuzhiyun t7l66xb_detach_irq(dev);
415*4882a593Smuzhiyun iounmap(t7l66xb->scr);
416*4882a593Smuzhiyun release_resource(&t7l66xb->rscr);
417*4882a593Smuzhiyun mfd_remove_devices(&dev->dev);
418*4882a593Smuzhiyun kfree(t7l66xb);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun return 0;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun static struct platform_driver t7l66xb_platform_driver = {
424*4882a593Smuzhiyun .driver = {
425*4882a593Smuzhiyun .name = "t7l66xb",
426*4882a593Smuzhiyun },
427*4882a593Smuzhiyun .suspend = t7l66xb_suspend,
428*4882a593Smuzhiyun .resume = t7l66xb_resume,
429*4882a593Smuzhiyun .probe = t7l66xb_probe,
430*4882a593Smuzhiyun .remove = t7l66xb_remove,
431*4882a593Smuzhiyun };
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun /*--------------------------------------------------------------------------*/
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun module_platform_driver(t7l66xb_platform_driver);
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
438*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
439*4882a593Smuzhiyun MODULE_AUTHOR("Ian Molton");
440*4882a593Smuzhiyun MODULE_ALIAS("platform:t7l66xb");
441