1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Core driver for STw4810/STw4811
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 ST-Ericsson SA
6*4882a593Smuzhiyun * Written on behalf of Linaro for ST-Ericsson
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Linus Walleij <linus.walleij@linaro.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/mfd/core.h>
15*4882a593Smuzhiyun #include <linux/mfd/stw481x.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/spinlock.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * This driver can only access the non-USB portions of STw4811, the register
23*4882a593Smuzhiyun * range 0x00-0x10 dealing with USB is bound to the two special I2C pins used
24*4882a593Smuzhiyun * for USB control.
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Registers inside the power control address space */
28*4882a593Smuzhiyun #define STW_PC_VCORE_SEL 0x05U
29*4882a593Smuzhiyun #define STW_PC_VAUX_SEL 0x06U
30*4882a593Smuzhiyun #define STW_PC_VPLL_SEL 0x07U
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /**
33*4882a593Smuzhiyun * stw481x_get_pctl_reg() - get a power control register
34*4882a593Smuzhiyun * @stw481x: handle to the stw481x chip
35*4882a593Smuzhiyun * @reg: power control register to fetch
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * The power control registers is a set of one-time-programmable registers
38*4882a593Smuzhiyun * in its own register space, accessed by writing addess bits to these
39*4882a593Smuzhiyun * two registers: bits 7,6,5 of PCTL_REG_LO corresponds to the 3 LSBs of
40*4882a593Smuzhiyun * the address and bits 8,9 of PCTL_REG_HI corresponds to the 2 MSBs of
41*4882a593Smuzhiyun * the address, forming an address space of 5 bits, i.e. 32 registers
42*4882a593Smuzhiyun * 0x00 ... 0x1f can be obtained.
43*4882a593Smuzhiyun */
stw481x_get_pctl_reg(struct stw481x * stw481x,u8 reg)44*4882a593Smuzhiyun static int stw481x_get_pctl_reg(struct stw481x *stw481x, u8 reg)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun u8 msb = (reg >> 3) & 0x03;
47*4882a593Smuzhiyun u8 lsb = (reg << 5) & 0xe0;
48*4882a593Smuzhiyun unsigned int val;
49*4882a593Smuzhiyun u8 vrfy;
50*4882a593Smuzhiyun int ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun ret = regmap_write(stw481x->map, STW_PCTL_REG_HI, msb);
53*4882a593Smuzhiyun if (ret)
54*4882a593Smuzhiyun return ret;
55*4882a593Smuzhiyun ret = regmap_write(stw481x->map, STW_PCTL_REG_LO, lsb);
56*4882a593Smuzhiyun if (ret)
57*4882a593Smuzhiyun return ret;
58*4882a593Smuzhiyun ret = regmap_read(stw481x->map, STW_PCTL_REG_HI, &val);
59*4882a593Smuzhiyun if (ret)
60*4882a593Smuzhiyun return ret;
61*4882a593Smuzhiyun vrfy = (val & 0x03) << 3;
62*4882a593Smuzhiyun ret = regmap_read(stw481x->map, STW_PCTL_REG_LO, &val);
63*4882a593Smuzhiyun if (ret)
64*4882a593Smuzhiyun return ret;
65*4882a593Smuzhiyun vrfy |= ((val >> 5) & 0x07);
66*4882a593Smuzhiyun if (vrfy != reg)
67*4882a593Smuzhiyun return -EIO;
68*4882a593Smuzhiyun return (val >> 1) & 0x0f;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
stw481x_startup(struct stw481x * stw481x)71*4882a593Smuzhiyun static int stw481x_startup(struct stw481x *stw481x)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun /* Voltages multiplied by 100 */
74*4882a593Smuzhiyun static const u8 vcore_val[] = {
75*4882a593Smuzhiyun 100, 105, 110, 115, 120, 122, 124, 126, 128,
76*4882a593Smuzhiyun 130, 132, 134, 136, 138, 140, 145
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun static const u8 vpll_val[] = { 105, 120, 130, 180 };
79*4882a593Smuzhiyun static const u8 vaux_val[] = { 15, 18, 25, 28 };
80*4882a593Smuzhiyun u8 vcore;
81*4882a593Smuzhiyun u8 vcore_slp;
82*4882a593Smuzhiyun u8 vpll;
83*4882a593Smuzhiyun u8 vaux;
84*4882a593Smuzhiyun bool vaux_en;
85*4882a593Smuzhiyun bool it_warn;
86*4882a593Smuzhiyun int ret;
87*4882a593Smuzhiyun unsigned int val;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun ret = regmap_read(stw481x->map, STW_CONF1, &val);
90*4882a593Smuzhiyun if (ret)
91*4882a593Smuzhiyun return ret;
92*4882a593Smuzhiyun vaux_en = !!(val & STW_CONF1_PDN_VAUX);
93*4882a593Smuzhiyun it_warn = !!(val & STW_CONF1_IT_WARN);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "voltages %s\n",
96*4882a593Smuzhiyun (val & STW_CONF1_V_MONITORING) ? "OK" : "LOW");
97*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "MMC level shifter %s\n",
98*4882a593Smuzhiyun (val & STW_CONF1_MMC_LS_STATUS) ? "high impedance" : "ON");
99*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "VMMC: %s\n",
100*4882a593Smuzhiyun (val & STW_CONF1_PDN_VMMC) ? "ON" : "disabled");
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "STw481x power control registers:\n");
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun ret = stw481x_get_pctl_reg(stw481x, STW_PC_VCORE_SEL);
105*4882a593Smuzhiyun if (ret < 0)
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun vcore = ret & 0x0f;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun ret = stw481x_get_pctl_reg(stw481x, STW_PC_VAUX_SEL);
110*4882a593Smuzhiyun if (ret < 0)
111*4882a593Smuzhiyun return ret;
112*4882a593Smuzhiyun vaux = (ret >> 2) & 3;
113*4882a593Smuzhiyun vpll = (ret >> 4) & 1; /* Save bit 4 */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ret = stw481x_get_pctl_reg(stw481x, STW_PC_VPLL_SEL);
116*4882a593Smuzhiyun if (ret < 0)
117*4882a593Smuzhiyun return ret;
118*4882a593Smuzhiyun vpll |= (ret >> 1) & 2;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "VCORE: %u.%uV %s\n",
121*4882a593Smuzhiyun vcore_val[vcore] / 100, vcore_val[vcore] % 100,
122*4882a593Smuzhiyun (ret & 4) ? "ON" : "OFF");
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "VPLL: %u.%uV %s\n",
125*4882a593Smuzhiyun vpll_val[vpll] / 100, vpll_val[vpll] % 100,
126*4882a593Smuzhiyun (ret & 0x10) ? "ON" : "OFF");
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "VAUX: %u.%uV %s\n",
129*4882a593Smuzhiyun vaux_val[vaux] / 10, vaux_val[vaux] % 10,
130*4882a593Smuzhiyun vaux_en ? "ON" : "OFF");
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun ret = regmap_read(stw481x->map, STW_CONF2, &val);
133*4882a593Smuzhiyun if (ret)
134*4882a593Smuzhiyun return ret;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "TWARN: %s threshold, %s\n",
137*4882a593Smuzhiyun it_warn ? "below" : "above",
138*4882a593Smuzhiyun (val & STW_CONF2_MASK_TWARN) ?
139*4882a593Smuzhiyun "enabled" : "mask through VDDOK");
140*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "VMMC: %s\n",
141*4882a593Smuzhiyun (val & STW_CONF2_VMMC_EXT) ? "internal" : "external");
142*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "IT WAKE UP: %s\n",
143*4882a593Smuzhiyun (val & STW_CONF2_MASK_IT_WAKE_UP) ? "enabled" : "masked");
144*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "GPO1: %s\n",
145*4882a593Smuzhiyun (val & STW_CONF2_GPO1) ? "low" : "high impedance");
146*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "GPO2: %s\n",
147*4882a593Smuzhiyun (val & STW_CONF2_GPO2) ? "low" : "high impedance");
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ret = regmap_read(stw481x->map, STW_VCORE_SLEEP, &val);
150*4882a593Smuzhiyun if (ret)
151*4882a593Smuzhiyun return ret;
152*4882a593Smuzhiyun vcore_slp = val & 0x0f;
153*4882a593Smuzhiyun dev_info(&stw481x->client->dev, "VCORE SLEEP: %u.%uV\n",
154*4882a593Smuzhiyun vcore_val[vcore_slp] / 100, vcore_val[vcore_slp] % 100);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun * MFD cells - we have one cell which is selected operation
161*4882a593Smuzhiyun * mode, and we always have a GPIO cell.
162*4882a593Smuzhiyun */
163*4882a593Smuzhiyun static struct mfd_cell stw481x_cells[] = {
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun .of_compatible = "st,stw481x-vmmc",
166*4882a593Smuzhiyun .name = "stw481x-vmmc-regulator",
167*4882a593Smuzhiyun .id = -1,
168*4882a593Smuzhiyun },
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const struct regmap_config stw481x_regmap_config = {
172*4882a593Smuzhiyun .reg_bits = 8,
173*4882a593Smuzhiyun .val_bits = 8,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
stw481x_probe(struct i2c_client * client,const struct i2c_device_id * id)176*4882a593Smuzhiyun static int stw481x_probe(struct i2c_client *client,
177*4882a593Smuzhiyun const struct i2c_device_id *id)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun struct stw481x *stw481x;
180*4882a593Smuzhiyun int ret;
181*4882a593Smuzhiyun int i;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun stw481x = devm_kzalloc(&client->dev, sizeof(*stw481x), GFP_KERNEL);
184*4882a593Smuzhiyun if (!stw481x)
185*4882a593Smuzhiyun return -ENOMEM;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun i2c_set_clientdata(client, stw481x);
188*4882a593Smuzhiyun stw481x->client = client;
189*4882a593Smuzhiyun stw481x->map = devm_regmap_init_i2c(client, &stw481x_regmap_config);
190*4882a593Smuzhiyun if (IS_ERR(stw481x->map)) {
191*4882a593Smuzhiyun ret = PTR_ERR(stw481x->map);
192*4882a593Smuzhiyun dev_err(&client->dev, "Failed to allocate register map: %d\n",
193*4882a593Smuzhiyun ret);
194*4882a593Smuzhiyun return ret;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun ret = stw481x_startup(stw481x);
198*4882a593Smuzhiyun if (ret) {
199*4882a593Smuzhiyun dev_err(&client->dev, "chip initialization failed\n");
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /* Set up and register the platform devices. */
204*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(stw481x_cells); i++) {
205*4882a593Smuzhiyun /* One state holder for all drivers, this is simple */
206*4882a593Smuzhiyun stw481x_cells[i].platform_data = stw481x;
207*4882a593Smuzhiyun stw481x_cells[i].pdata_size = sizeof(*stw481x);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun ret = devm_mfd_add_devices(&client->dev, 0, stw481x_cells,
211*4882a593Smuzhiyun ARRAY_SIZE(stw481x_cells), NULL, 0, NULL);
212*4882a593Smuzhiyun if (ret)
213*4882a593Smuzhiyun return ret;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun dev_info(&client->dev, "initialized STw481x device\n");
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /*
221*4882a593Smuzhiyun * This ID table is completely unused, as this is a pure
222*4882a593Smuzhiyun * device-tree probed driver, but it has to be here due to
223*4882a593Smuzhiyun * the structure of the I2C core.
224*4882a593Smuzhiyun */
225*4882a593Smuzhiyun static const struct i2c_device_id stw481x_id[] = {
226*4882a593Smuzhiyun { "stw481x", 0 },
227*4882a593Smuzhiyun { },
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, stw481x_id);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const struct of_device_id stw481x_match[] = {
232*4882a593Smuzhiyun { .compatible = "st,stw4810", },
233*4882a593Smuzhiyun { .compatible = "st,stw4811", },
234*4882a593Smuzhiyun { },
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stw481x_match);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static struct i2c_driver stw481x_driver = {
239*4882a593Smuzhiyun .driver = {
240*4882a593Smuzhiyun .name = "stw481x",
241*4882a593Smuzhiyun .of_match_table = stw481x_match,
242*4882a593Smuzhiyun },
243*4882a593Smuzhiyun .probe = stw481x_probe,
244*4882a593Smuzhiyun .id_table = stw481x_id,
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun module_i2c_driver(stw481x_driver);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun MODULE_AUTHOR("Linus Walleij");
250*4882a593Smuzhiyun MODULE_DESCRIPTION("STw481x PMIC driver");
251*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
252