xref: /OK3568_Linux_fs/kernel/drivers/mfd/stpmic1.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) STMicroelectronics 2018
3*4882a593Smuzhiyun // Author: Pascal Paillet <p.paillet@st.com>
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <linux/i2c.h>
6*4882a593Smuzhiyun #include <linux/interrupt.h>
7*4882a593Smuzhiyun #include <linux/mfd/core.h>
8*4882a593Smuzhiyun #include <linux/mfd/stpmic1.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_irq.h>
12*4882a593Smuzhiyun #include <linux/of_platform.h>
13*4882a593Smuzhiyun #include <linux/pm_wakeirq.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <dt-bindings/mfd/st,stpmic1.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define STPMIC1_MAIN_IRQ 0
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun static const struct regmap_range stpmic1_readable_ranges[] = {
21*4882a593Smuzhiyun 	regmap_reg_range(TURN_ON_SR, VERSION_SR),
22*4882a593Smuzhiyun 	regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
23*4882a593Smuzhiyun 	regmap_reg_range(BST_SW_CR, BST_SW_CR),
24*4882a593Smuzhiyun 	regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
25*4882a593Smuzhiyun 	regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
26*4882a593Smuzhiyun 	regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
27*4882a593Smuzhiyun 	regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
28*4882a593Smuzhiyun 	regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
29*4882a593Smuzhiyun 	regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static const struct regmap_range stpmic1_writeable_ranges[] = {
33*4882a593Smuzhiyun 	regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
34*4882a593Smuzhiyun 	regmap_reg_range(BST_SW_CR, BST_SW_CR),
35*4882a593Smuzhiyun 	regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
36*4882a593Smuzhiyun 	regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
37*4882a593Smuzhiyun 	regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static const struct regmap_range stpmic1_volatile_ranges[] = {
41*4882a593Smuzhiyun 	regmap_reg_range(TURN_ON_SR, VERSION_SR),
42*4882a593Smuzhiyun 	regmap_reg_range(WCHDG_CR, WCHDG_CR),
43*4882a593Smuzhiyun 	regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
44*4882a593Smuzhiyun 	regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static const struct regmap_access_table stpmic1_readable_table = {
48*4882a593Smuzhiyun 	.yes_ranges = stpmic1_readable_ranges,
49*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun static const struct regmap_access_table stpmic1_writeable_table = {
53*4882a593Smuzhiyun 	.yes_ranges = stpmic1_writeable_ranges,
54*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun static const struct regmap_access_table stpmic1_volatile_table = {
58*4882a593Smuzhiyun 	.yes_ranges = stpmic1_volatile_ranges,
59*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static const struct regmap_config stpmic1_regmap_config = {
63*4882a593Smuzhiyun 	.reg_bits = 8,
64*4882a593Smuzhiyun 	.val_bits = 8,
65*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
66*4882a593Smuzhiyun 	.max_register = PMIC_MAX_REGISTER_ADDRESS,
67*4882a593Smuzhiyun 	.rd_table = &stpmic1_readable_table,
68*4882a593Smuzhiyun 	.wr_table = &stpmic1_writeable_table,
69*4882a593Smuzhiyun 	.volatile_table = &stpmic1_volatile_table,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static const struct regmap_irq stpmic1_irqs[] = {
73*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
74*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
75*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
76*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
77*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
78*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
79*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
80*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
83*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
84*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
85*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
86*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
87*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
88*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
89*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
92*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
93*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
94*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
95*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
96*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
97*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
98*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
101*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
102*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
103*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
104*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
105*4882a593Smuzhiyun 	REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
109*4882a593Smuzhiyun 	.name = "pmic_irq",
110*4882a593Smuzhiyun 	.status_base = INT_PENDING_R1,
111*4882a593Smuzhiyun 	.mask_base = INT_CLEAR_MASK_R1,
112*4882a593Smuzhiyun 	.unmask_base = INT_SET_MASK_R1,
113*4882a593Smuzhiyun 	.ack_base = INT_CLEAR_R1,
114*4882a593Smuzhiyun 	.num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
115*4882a593Smuzhiyun 	.irqs = stpmic1_irqs,
116*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(stpmic1_irqs),
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
stpmic1_probe(struct i2c_client * i2c,const struct i2c_device_id * id)119*4882a593Smuzhiyun static int stpmic1_probe(struct i2c_client *i2c,
120*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct stpmic1 *ddata;
123*4882a593Smuzhiyun 	struct device *dev = &i2c->dev;
124*4882a593Smuzhiyun 	int ret;
125*4882a593Smuzhiyun 	struct device_node *np = dev->of_node;
126*4882a593Smuzhiyun 	u32 reg;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
129*4882a593Smuzhiyun 	if (!ddata)
130*4882a593Smuzhiyun 		return -ENOMEM;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, ddata);
133*4882a593Smuzhiyun 	ddata->dev = dev;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
136*4882a593Smuzhiyun 	if (IS_ERR(ddata->regmap))
137*4882a593Smuzhiyun 		return PTR_ERR(ddata->regmap);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
140*4882a593Smuzhiyun 	if (ddata->irq < 0) {
141*4882a593Smuzhiyun 		dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
142*4882a593Smuzhiyun 		return ddata->irq;
143*4882a593Smuzhiyun 	}
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	ret = regmap_read(ddata->regmap, VERSION_SR, &reg);
146*4882a593Smuzhiyun 	if (ret) {
147*4882a593Smuzhiyun 		dev_err(dev, "Unable to read PMIC version\n");
148*4882a593Smuzhiyun 		return ret;
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 	dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	/* Initialize PMIC IRQ Chip & associated IRQ domains */
153*4882a593Smuzhiyun 	ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
154*4882a593Smuzhiyun 				       IRQF_ONESHOT | IRQF_SHARED,
155*4882a593Smuzhiyun 				       0, &stpmic1_regmap_irq_chip,
156*4882a593Smuzhiyun 				       &ddata->irq_data);
157*4882a593Smuzhiyun 	if (ret) {
158*4882a593Smuzhiyun 		dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
159*4882a593Smuzhiyun 		return ret;
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return devm_of_platform_populate(dev);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
stpmic1_suspend(struct device * dev)166*4882a593Smuzhiyun static int stpmic1_suspend(struct device *dev)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct i2c_client *i2c = to_i2c_client(dev);
169*4882a593Smuzhiyun 	struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	disable_irq(pmic_dev->irq);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
stpmic1_resume(struct device * dev)176*4882a593Smuzhiyun static int stpmic1_resume(struct device *dev)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct i2c_client *i2c = to_i2c_client(dev);
179*4882a593Smuzhiyun 	struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
180*4882a593Smuzhiyun 	int ret;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	ret = regcache_sync(pmic_dev->regmap);
183*4882a593Smuzhiyun 	if (ret)
184*4882a593Smuzhiyun 		return ret;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	enable_irq(pmic_dev->irq);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	return 0;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun #endif
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun static const struct of_device_id stpmic1_of_match[] = {
195*4882a593Smuzhiyun 	{ .compatible = "st,stpmic1", },
196*4882a593Smuzhiyun 	{},
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stpmic1_of_match);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static struct i2c_driver stpmic1_driver = {
201*4882a593Smuzhiyun 	.driver = {
202*4882a593Smuzhiyun 		.name = "stpmic1",
203*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(stpmic1_of_match),
204*4882a593Smuzhiyun 		.pm = &stpmic1_pm,
205*4882a593Smuzhiyun 	},
206*4882a593Smuzhiyun 	.probe = stpmic1_probe,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun module_i2c_driver(stpmic1_driver);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
212*4882a593Smuzhiyun MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
213*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
214