1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/mfd/si476x-cmd.c -- Subroutines implementing command
4*4882a593Smuzhiyun * protocol of si476x series of chips
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2012 Innovative Converged Devices(ICD)
7*4882a593Smuzhiyun * Copyright (C) 2013 Andrey Smirnov
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/completion.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/atomic.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/device.h>
18*4882a593Smuzhiyun #include <linux/gpio.h>
19*4882a593Smuzhiyun #include <linux/videodev2.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/mfd/si476x-core.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <asm/unaligned.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define msb(x) ((u8)((u16) x >> 8))
26*4882a593Smuzhiyun #define lsb(x) ((u8)((u16) x & 0x00FF))
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define CMD_POWER_UP 0x01
31*4882a593Smuzhiyun #define CMD_POWER_UP_A10_NRESP 1
32*4882a593Smuzhiyun #define CMD_POWER_UP_A10_NARGS 5
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define CMD_POWER_UP_A20_NRESP 1
35*4882a593Smuzhiyun #define CMD_POWER_UP_A20_NARGS 5
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define POWER_UP_DELAY_MS 110
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define CMD_POWER_DOWN 0x11
40*4882a593Smuzhiyun #define CMD_POWER_DOWN_A10_NRESP 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define CMD_POWER_DOWN_A20_NRESP 1
43*4882a593Smuzhiyun #define CMD_POWER_DOWN_A20_NARGS 1
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define CMD_FUNC_INFO 0x12
46*4882a593Smuzhiyun #define CMD_FUNC_INFO_NRESP 7
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define CMD_SET_PROPERTY 0x13
49*4882a593Smuzhiyun #define CMD_SET_PROPERTY_NARGS 5
50*4882a593Smuzhiyun #define CMD_SET_PROPERTY_NRESP 1
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define CMD_GET_PROPERTY 0x14
53*4882a593Smuzhiyun #define CMD_GET_PROPERTY_NARGS 3
54*4882a593Smuzhiyun #define CMD_GET_PROPERTY_NRESP 4
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define CMD_AGC_STATUS 0x17
57*4882a593Smuzhiyun #define CMD_AGC_STATUS_NRESP_A10 2
58*4882a593Smuzhiyun #define CMD_AGC_STATUS_NRESP_A20 6
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define PIN_CFG_BYTE(x) (0x7F & (x))
61*4882a593Smuzhiyun #define CMD_DIG_AUDIO_PIN_CFG 0x18
62*4882a593Smuzhiyun #define CMD_DIG_AUDIO_PIN_CFG_NARGS 4
63*4882a593Smuzhiyun #define CMD_DIG_AUDIO_PIN_CFG_NRESP 5
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define CMD_ZIF_PIN_CFG 0x19
66*4882a593Smuzhiyun #define CMD_ZIF_PIN_CFG_NARGS 4
67*4882a593Smuzhiyun #define CMD_ZIF_PIN_CFG_NRESP 5
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define CMD_IC_LINK_GPO_CTL_PIN_CFG 0x1A
70*4882a593Smuzhiyun #define CMD_IC_LINK_GPO_CTL_PIN_CFG_NARGS 4
71*4882a593Smuzhiyun #define CMD_IC_LINK_GPO_CTL_PIN_CFG_NRESP 5
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define CMD_ANA_AUDIO_PIN_CFG 0x1B
74*4882a593Smuzhiyun #define CMD_ANA_AUDIO_PIN_CFG_NARGS 1
75*4882a593Smuzhiyun #define CMD_ANA_AUDIO_PIN_CFG_NRESP 2
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define CMD_INTB_PIN_CFG 0x1C
78*4882a593Smuzhiyun #define CMD_INTB_PIN_CFG_NARGS 2
79*4882a593Smuzhiyun #define CMD_INTB_PIN_CFG_A10_NRESP 6
80*4882a593Smuzhiyun #define CMD_INTB_PIN_CFG_A20_NRESP 3
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define CMD_FM_TUNE_FREQ 0x30
83*4882a593Smuzhiyun #define CMD_FM_TUNE_FREQ_A10_NARGS 5
84*4882a593Smuzhiyun #define CMD_FM_TUNE_FREQ_A20_NARGS 3
85*4882a593Smuzhiyun #define CMD_FM_TUNE_FREQ_NRESP 1
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define CMD_FM_RSQ_STATUS 0x32
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define CMD_FM_RSQ_STATUS_A10_NARGS 1
90*4882a593Smuzhiyun #define CMD_FM_RSQ_STATUS_A10_NRESP 17
91*4882a593Smuzhiyun #define CMD_FM_RSQ_STATUS_A30_NARGS 1
92*4882a593Smuzhiyun #define CMD_FM_RSQ_STATUS_A30_NRESP 23
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #define CMD_FM_SEEK_START 0x31
96*4882a593Smuzhiyun #define CMD_FM_SEEK_START_NARGS 1
97*4882a593Smuzhiyun #define CMD_FM_SEEK_START_NRESP 1
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #define CMD_FM_RDS_STATUS 0x36
100*4882a593Smuzhiyun #define CMD_FM_RDS_STATUS_NARGS 1
101*4882a593Smuzhiyun #define CMD_FM_RDS_STATUS_NRESP 16
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define CMD_FM_RDS_BLOCKCOUNT 0x37
104*4882a593Smuzhiyun #define CMD_FM_RDS_BLOCKCOUNT_NARGS 1
105*4882a593Smuzhiyun #define CMD_FM_RDS_BLOCKCOUNT_NRESP 8
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define CMD_FM_PHASE_DIVERSITY 0x38
108*4882a593Smuzhiyun #define CMD_FM_PHASE_DIVERSITY_NARGS 1
109*4882a593Smuzhiyun #define CMD_FM_PHASE_DIVERSITY_NRESP 1
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #define CMD_FM_PHASE_DIV_STATUS 0x39
112*4882a593Smuzhiyun #define CMD_FM_PHASE_DIV_STATUS_NRESP 2
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #define CMD_AM_TUNE_FREQ 0x40
115*4882a593Smuzhiyun #define CMD_AM_TUNE_FREQ_NARGS 3
116*4882a593Smuzhiyun #define CMD_AM_TUNE_FREQ_NRESP 1
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #define CMD_AM_RSQ_STATUS 0x42
119*4882a593Smuzhiyun #define CMD_AM_RSQ_STATUS_NARGS 1
120*4882a593Smuzhiyun #define CMD_AM_RSQ_STATUS_NRESP 13
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #define CMD_AM_SEEK_START 0x41
123*4882a593Smuzhiyun #define CMD_AM_SEEK_START_NARGS 1
124*4882a593Smuzhiyun #define CMD_AM_SEEK_START_NRESP 1
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #define CMD_AM_ACF_STATUS 0x45
128*4882a593Smuzhiyun #define CMD_AM_ACF_STATUS_NRESP 6
129*4882a593Smuzhiyun #define CMD_AM_ACF_STATUS_NARGS 1
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #define CMD_FM_ACF_STATUS 0x35
132*4882a593Smuzhiyun #define CMD_FM_ACF_STATUS_NRESP 8
133*4882a593Smuzhiyun #define CMD_FM_ACF_STATUS_NARGS 1
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define CMD_MAX_ARGS_COUNT (10)
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun enum si476x_acf_status_report_bits {
139*4882a593Smuzhiyun SI476X_ACF_BLEND_INT = (1 << 4),
140*4882a593Smuzhiyun SI476X_ACF_HIBLEND_INT = (1 << 3),
141*4882a593Smuzhiyun SI476X_ACF_HICUT_INT = (1 << 2),
142*4882a593Smuzhiyun SI476X_ACF_CHBW_INT = (1 << 1),
143*4882a593Smuzhiyun SI476X_ACF_SOFTMUTE_INT = (1 << 0),
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun SI476X_ACF_SMUTE = (1 << 0),
146*4882a593Smuzhiyun SI476X_ACF_SMATTN = 0x1f,
147*4882a593Smuzhiyun SI476X_ACF_PILOT = (1 << 7),
148*4882a593Smuzhiyun SI476X_ACF_STBLEND = ~SI476X_ACF_PILOT,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun enum si476x_agc_status_report_bits {
152*4882a593Smuzhiyun SI476X_AGC_MXHI = (1 << 5),
153*4882a593Smuzhiyun SI476X_AGC_MXLO = (1 << 4),
154*4882a593Smuzhiyun SI476X_AGC_LNAHI = (1 << 3),
155*4882a593Smuzhiyun SI476X_AGC_LNALO = (1 << 2),
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun enum si476x_errors {
159*4882a593Smuzhiyun SI476X_ERR_BAD_COMMAND = 0x10,
160*4882a593Smuzhiyun SI476X_ERR_BAD_ARG1 = 0x11,
161*4882a593Smuzhiyun SI476X_ERR_BAD_ARG2 = 0x12,
162*4882a593Smuzhiyun SI476X_ERR_BAD_ARG3 = 0x13,
163*4882a593Smuzhiyun SI476X_ERR_BAD_ARG4 = 0x14,
164*4882a593Smuzhiyun SI476X_ERR_BUSY = 0x18,
165*4882a593Smuzhiyun SI476X_ERR_BAD_INTERNAL_MEMORY = 0x20,
166*4882a593Smuzhiyun SI476X_ERR_BAD_PATCH = 0x30,
167*4882a593Smuzhiyun SI476X_ERR_BAD_BOOT_MODE = 0x31,
168*4882a593Smuzhiyun SI476X_ERR_BAD_PROPERTY = 0x40,
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
si476x_core_parse_and_nag_about_error(struct si476x_core * core)171*4882a593Smuzhiyun static int si476x_core_parse_and_nag_about_error(struct si476x_core *core)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun int err;
174*4882a593Smuzhiyun char *cause;
175*4882a593Smuzhiyun u8 buffer[2];
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (core->revision != SI476X_REVISION_A10) {
178*4882a593Smuzhiyun err = si476x_core_i2c_xfer(core, SI476X_I2C_RECV,
179*4882a593Smuzhiyun buffer, sizeof(buffer));
180*4882a593Smuzhiyun if (err == sizeof(buffer)) {
181*4882a593Smuzhiyun switch (buffer[1]) {
182*4882a593Smuzhiyun case SI476X_ERR_BAD_COMMAND:
183*4882a593Smuzhiyun cause = "Bad command";
184*4882a593Smuzhiyun err = -EINVAL;
185*4882a593Smuzhiyun break;
186*4882a593Smuzhiyun case SI476X_ERR_BAD_ARG1:
187*4882a593Smuzhiyun cause = "Bad argument #1";
188*4882a593Smuzhiyun err = -EINVAL;
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun case SI476X_ERR_BAD_ARG2:
191*4882a593Smuzhiyun cause = "Bad argument #2";
192*4882a593Smuzhiyun err = -EINVAL;
193*4882a593Smuzhiyun break;
194*4882a593Smuzhiyun case SI476X_ERR_BAD_ARG3:
195*4882a593Smuzhiyun cause = "Bad argument #3";
196*4882a593Smuzhiyun err = -EINVAL;
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun case SI476X_ERR_BAD_ARG4:
199*4882a593Smuzhiyun cause = "Bad argument #4";
200*4882a593Smuzhiyun err = -EINVAL;
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun case SI476X_ERR_BUSY:
203*4882a593Smuzhiyun cause = "Chip is busy";
204*4882a593Smuzhiyun err = -EBUSY;
205*4882a593Smuzhiyun break;
206*4882a593Smuzhiyun case SI476X_ERR_BAD_INTERNAL_MEMORY:
207*4882a593Smuzhiyun cause = "Bad internal memory";
208*4882a593Smuzhiyun err = -EIO;
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun case SI476X_ERR_BAD_PATCH:
211*4882a593Smuzhiyun cause = "Bad patch";
212*4882a593Smuzhiyun err = -EINVAL;
213*4882a593Smuzhiyun break;
214*4882a593Smuzhiyun case SI476X_ERR_BAD_BOOT_MODE:
215*4882a593Smuzhiyun cause = "Bad boot mode";
216*4882a593Smuzhiyun err = -EINVAL;
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun case SI476X_ERR_BAD_PROPERTY:
219*4882a593Smuzhiyun cause = "Bad property";
220*4882a593Smuzhiyun err = -EINVAL;
221*4882a593Smuzhiyun break;
222*4882a593Smuzhiyun default:
223*4882a593Smuzhiyun cause = "Unknown";
224*4882a593Smuzhiyun err = -EIO;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun dev_err(&core->client->dev,
228*4882a593Smuzhiyun "[Chip error status]: %s\n", cause);
229*4882a593Smuzhiyun } else {
230*4882a593Smuzhiyun dev_err(&core->client->dev,
231*4882a593Smuzhiyun "Failed to fetch error code\n");
232*4882a593Smuzhiyun err = (err >= 0) ? -EIO : err;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun } else {
235*4882a593Smuzhiyun err = -EIO;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun return err;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /**
242*4882a593Smuzhiyun * si476x_core_send_command() - sends a command to si476x and waits its
243*4882a593Smuzhiyun * response
244*4882a593Smuzhiyun * @core: si476x_device structure for the device we are
245*4882a593Smuzhiyun * communicating with
246*4882a593Smuzhiyun * @command: command id
247*4882a593Smuzhiyun * @args: command arguments we are sending
248*4882a593Smuzhiyun * @argn: actual size of @args
249*4882a593Smuzhiyun * @resp: buffer to place the expected response from the device
250*4882a593Smuzhiyun * @respn: actual size of @resp
251*4882a593Smuzhiyun * @usecs: amount of time to wait before reading the response (in
252*4882a593Smuzhiyun * usecs)
253*4882a593Smuzhiyun *
254*4882a593Smuzhiyun * Function returns 0 on succsess and negative error code on
255*4882a593Smuzhiyun * failure
256*4882a593Smuzhiyun */
si476x_core_send_command(struct si476x_core * core,const u8 command,const u8 args[],const int argn,u8 resp[],const int respn,const int usecs)257*4882a593Smuzhiyun static int si476x_core_send_command(struct si476x_core *core,
258*4882a593Smuzhiyun const u8 command,
259*4882a593Smuzhiyun const u8 args[],
260*4882a593Smuzhiyun const int argn,
261*4882a593Smuzhiyun u8 resp[],
262*4882a593Smuzhiyun const int respn,
263*4882a593Smuzhiyun const int usecs)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct i2c_client *client = core->client;
266*4882a593Smuzhiyun int err;
267*4882a593Smuzhiyun u8 data[CMD_MAX_ARGS_COUNT + 1];
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (argn > CMD_MAX_ARGS_COUNT) {
270*4882a593Smuzhiyun err = -ENOMEM;
271*4882a593Smuzhiyun goto exit;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (!client->adapter) {
275*4882a593Smuzhiyun err = -ENODEV;
276*4882a593Smuzhiyun goto exit;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun /* First send the command and its arguments */
280*4882a593Smuzhiyun data[0] = command;
281*4882a593Smuzhiyun memcpy(&data[1], args, argn);
282*4882a593Smuzhiyun dev_dbg(&client->dev, "Command:\n %*ph\n", argn + 1, data);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun err = si476x_core_i2c_xfer(core, SI476X_I2C_SEND,
285*4882a593Smuzhiyun (char *) data, argn + 1);
286*4882a593Smuzhiyun if (err != argn + 1) {
287*4882a593Smuzhiyun dev_err(&core->client->dev,
288*4882a593Smuzhiyun "Error while sending command 0x%02x\n",
289*4882a593Smuzhiyun command);
290*4882a593Smuzhiyun err = (err >= 0) ? -EIO : err;
291*4882a593Smuzhiyun goto exit;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun /* Set CTS to zero only after the command is send to avoid
294*4882a593Smuzhiyun * possible racing conditions when working in polling mode */
295*4882a593Smuzhiyun atomic_set(&core->cts, 0);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* if (unlikely(command == CMD_POWER_DOWN) */
298*4882a593Smuzhiyun if (!wait_event_timeout(core->command,
299*4882a593Smuzhiyun atomic_read(&core->cts),
300*4882a593Smuzhiyun usecs_to_jiffies(usecs) + 1))
301*4882a593Smuzhiyun dev_warn(&core->client->dev,
302*4882a593Smuzhiyun "(%s) [CMD 0x%02x] Answer timeout.\n",
303*4882a593Smuzhiyun __func__, command);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /*
306*4882a593Smuzhiyun When working in polling mode, for some reason the tuner will
307*4882a593Smuzhiyun report CTS bit as being set in the first status byte read,
308*4882a593Smuzhiyun but all the consequtive ones will return zeros until the
309*4882a593Smuzhiyun tuner is actually completed the POWER_UP command. To
310*4882a593Smuzhiyun workaround that we wait for second CTS to be reported
311*4882a593Smuzhiyun */
312*4882a593Smuzhiyun if (unlikely(!core->client->irq && command == CMD_POWER_UP)) {
313*4882a593Smuzhiyun if (!wait_event_timeout(core->command,
314*4882a593Smuzhiyun atomic_read(&core->cts),
315*4882a593Smuzhiyun usecs_to_jiffies(usecs) + 1))
316*4882a593Smuzhiyun dev_warn(&core->client->dev,
317*4882a593Smuzhiyun "(%s) Power up took too much time.\n",
318*4882a593Smuzhiyun __func__);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* Then get the response */
322*4882a593Smuzhiyun err = si476x_core_i2c_xfer(core, SI476X_I2C_RECV, resp, respn);
323*4882a593Smuzhiyun if (err != respn) {
324*4882a593Smuzhiyun dev_err(&core->client->dev,
325*4882a593Smuzhiyun "Error while reading response for command 0x%02x\n",
326*4882a593Smuzhiyun command);
327*4882a593Smuzhiyun err = (err >= 0) ? -EIO : err;
328*4882a593Smuzhiyun goto exit;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun dev_dbg(&client->dev, "Response:\n %*ph\n", respn, resp);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun err = 0;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun if (resp[0] & SI476X_ERR) {
335*4882a593Smuzhiyun dev_err(&core->client->dev,
336*4882a593Smuzhiyun "[CMD 0x%02x] Chip set error flag\n", command);
337*4882a593Smuzhiyun err = si476x_core_parse_and_nag_about_error(core);
338*4882a593Smuzhiyun goto exit;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun if (!(resp[0] & SI476X_CTS))
342*4882a593Smuzhiyun err = -EBUSY;
343*4882a593Smuzhiyun exit:
344*4882a593Smuzhiyun return err;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
si476x_cmd_clear_stc(struct si476x_core * core)347*4882a593Smuzhiyun static int si476x_cmd_clear_stc(struct si476x_core *core)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun int err;
350*4882a593Smuzhiyun struct si476x_rsq_status_args args = {
351*4882a593Smuzhiyun .primary = false,
352*4882a593Smuzhiyun .rsqack = false,
353*4882a593Smuzhiyun .attune = false,
354*4882a593Smuzhiyun .cancel = false,
355*4882a593Smuzhiyun .stcack = true,
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun switch (core->power_up_parameters.func) {
359*4882a593Smuzhiyun case SI476X_FUNC_FM_RECEIVER:
360*4882a593Smuzhiyun err = si476x_core_cmd_fm_rsq_status(core, &args, NULL);
361*4882a593Smuzhiyun break;
362*4882a593Smuzhiyun case SI476X_FUNC_AM_RECEIVER:
363*4882a593Smuzhiyun err = si476x_core_cmd_am_rsq_status(core, &args, NULL);
364*4882a593Smuzhiyun break;
365*4882a593Smuzhiyun default:
366*4882a593Smuzhiyun err = -EINVAL;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun return err;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
si476x_cmd_tune_seek_freq(struct si476x_core * core,uint8_t cmd,const uint8_t args[],size_t argn,uint8_t * resp,size_t respn)372*4882a593Smuzhiyun static int si476x_cmd_tune_seek_freq(struct si476x_core *core,
373*4882a593Smuzhiyun uint8_t cmd,
374*4882a593Smuzhiyun const uint8_t args[], size_t argn,
375*4882a593Smuzhiyun uint8_t *resp, size_t respn)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun int err;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun atomic_set(&core->stc, 0);
381*4882a593Smuzhiyun err = si476x_core_send_command(core, cmd, args, argn, resp, respn,
382*4882a593Smuzhiyun SI476X_TIMEOUT_TUNE);
383*4882a593Smuzhiyun if (!err) {
384*4882a593Smuzhiyun wait_event_killable(core->tuning,
385*4882a593Smuzhiyun atomic_read(&core->stc));
386*4882a593Smuzhiyun si476x_cmd_clear_stc(core);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return err;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /**
393*4882a593Smuzhiyun * si476x_cmd_func_info() - send 'FUNC_INFO' command to the device
394*4882a593Smuzhiyun * @core: device to send the command to
395*4882a593Smuzhiyun * @info: struct si476x_func_info to fill all the information
396*4882a593Smuzhiyun * returned by the command
397*4882a593Smuzhiyun *
398*4882a593Smuzhiyun * The command requests the firmware and patch version for currently
399*4882a593Smuzhiyun * loaded firmware (dependent on the function of the device FM/AM/WB)
400*4882a593Smuzhiyun *
401*4882a593Smuzhiyun * Function returns 0 on succsess and negative error code on
402*4882a593Smuzhiyun * failure
403*4882a593Smuzhiyun */
si476x_core_cmd_func_info(struct si476x_core * core,struct si476x_func_info * info)404*4882a593Smuzhiyun int si476x_core_cmd_func_info(struct si476x_core *core,
405*4882a593Smuzhiyun struct si476x_func_info *info)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun int err;
408*4882a593Smuzhiyun u8 resp[CMD_FUNC_INFO_NRESP];
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FUNC_INFO,
411*4882a593Smuzhiyun NULL, 0,
412*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
413*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun info->firmware.major = resp[1];
416*4882a593Smuzhiyun info->firmware.minor[0] = resp[2];
417*4882a593Smuzhiyun info->firmware.minor[1] = resp[3];
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun info->patch_id = ((u16) resp[4] << 8) | resp[5];
420*4882a593Smuzhiyun info->func = resp[6];
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun return err;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_func_info);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /**
427*4882a593Smuzhiyun * si476x_cmd_set_property() - send 'SET_PROPERTY' command to the device
428*4882a593Smuzhiyun * @core: device to send the command to
429*4882a593Smuzhiyun * @property: property address
430*4882a593Smuzhiyun * @value: property value
431*4882a593Smuzhiyun *
432*4882a593Smuzhiyun * Function returns 0 on succsess and negative error code on
433*4882a593Smuzhiyun * failure
434*4882a593Smuzhiyun */
si476x_core_cmd_set_property(struct si476x_core * core,u16 property,u16 value)435*4882a593Smuzhiyun int si476x_core_cmd_set_property(struct si476x_core *core,
436*4882a593Smuzhiyun u16 property, u16 value)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun u8 resp[CMD_SET_PROPERTY_NRESP];
439*4882a593Smuzhiyun const u8 args[CMD_SET_PROPERTY_NARGS] = {
440*4882a593Smuzhiyun 0x00,
441*4882a593Smuzhiyun msb(property),
442*4882a593Smuzhiyun lsb(property),
443*4882a593Smuzhiyun msb(value),
444*4882a593Smuzhiyun lsb(value),
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_SET_PROPERTY,
448*4882a593Smuzhiyun args, ARRAY_SIZE(args),
449*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
450*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_set_property);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /**
455*4882a593Smuzhiyun * si476x_cmd_get_property() - send 'GET_PROPERTY' command to the device
456*4882a593Smuzhiyun * @core: device to send the command to
457*4882a593Smuzhiyun * @property: property address
458*4882a593Smuzhiyun *
459*4882a593Smuzhiyun * Function return the value of property as u16 on success or a
460*4882a593Smuzhiyun * negative error on failure
461*4882a593Smuzhiyun */
si476x_core_cmd_get_property(struct si476x_core * core,u16 property)462*4882a593Smuzhiyun int si476x_core_cmd_get_property(struct si476x_core *core, u16 property)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun int err;
465*4882a593Smuzhiyun u8 resp[CMD_GET_PROPERTY_NRESP];
466*4882a593Smuzhiyun const u8 args[CMD_GET_PROPERTY_NARGS] = {
467*4882a593Smuzhiyun 0x00,
468*4882a593Smuzhiyun msb(property),
469*4882a593Smuzhiyun lsb(property),
470*4882a593Smuzhiyun };
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_GET_PROPERTY,
473*4882a593Smuzhiyun args, ARRAY_SIZE(args),
474*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
475*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
476*4882a593Smuzhiyun if (err < 0)
477*4882a593Smuzhiyun return err;
478*4882a593Smuzhiyun else
479*4882a593Smuzhiyun return get_unaligned_be16(resp + 2);
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_get_property);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun /**
484*4882a593Smuzhiyun * si476x_cmd_dig_audio_pin_cfg() - send 'DIG_AUDIO_PIN_CFG' command to
485*4882a593Smuzhiyun * the device
486*4882a593Smuzhiyun * @core: device to send the command to
487*4882a593Smuzhiyun * @dclk: DCLK pin function configuration:
488*4882a593Smuzhiyun * #SI476X_DCLK_NOOP - do not modify the behaviour
489*4882a593Smuzhiyun * #SI476X_DCLK_TRISTATE - put the pin in tristate condition,
490*4882a593Smuzhiyun * enable 1MOhm pulldown
491*4882a593Smuzhiyun * #SI476X_DCLK_DAUDIO - set the pin to be a part of digital
492*4882a593Smuzhiyun * audio interface
493*4882a593Smuzhiyun * @dfs: DFS pin function configuration:
494*4882a593Smuzhiyun * #SI476X_DFS_NOOP - do not modify the behaviour
495*4882a593Smuzhiyun * #SI476X_DFS_TRISTATE - put the pin in tristate condition,
496*4882a593Smuzhiyun * enable 1MOhm pulldown
497*4882a593Smuzhiyun * SI476X_DFS_DAUDIO - set the pin to be a part of digital
498*4882a593Smuzhiyun * audio interface
499*4882a593Smuzhiyun * @dout: - DOUT pin function configuration:
500*4882a593Smuzhiyun * SI476X_DOUT_NOOP - do not modify the behaviour
501*4882a593Smuzhiyun * SI476X_DOUT_TRISTATE - put the pin in tristate condition,
502*4882a593Smuzhiyun * enable 1MOhm pulldown
503*4882a593Smuzhiyun * SI476X_DOUT_I2S_OUTPUT - set this pin to be digital out on I2S
504*4882a593Smuzhiyun * port 1
505*4882a593Smuzhiyun * SI476X_DOUT_I2S_INPUT - set this pin to be digital in on I2S
506*4882a593Smuzhiyun * port 1
507*4882a593Smuzhiyun * @xout: - XOUT pin function configuration:
508*4882a593Smuzhiyun * SI476X_XOUT_NOOP - do not modify the behaviour
509*4882a593Smuzhiyun * SI476X_XOUT_TRISTATE - put the pin in tristate condition,
510*4882a593Smuzhiyun * enable 1MOhm pulldown
511*4882a593Smuzhiyun * SI476X_XOUT_I2S_INPUT - set this pin to be digital in on I2S
512*4882a593Smuzhiyun * port 1
513*4882a593Smuzhiyun * SI476X_XOUT_MODE_SELECT - set this pin to be the input that
514*4882a593Smuzhiyun * selects the mode of the I2S audio
515*4882a593Smuzhiyun * combiner (analog or HD)
516*4882a593Smuzhiyun * [SI4761/63/65/67 Only]
517*4882a593Smuzhiyun *
518*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
519*4882a593Smuzhiyun */
si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core * core,enum si476x_dclk_config dclk,enum si476x_dfs_config dfs,enum si476x_dout_config dout,enum si476x_xout_config xout)520*4882a593Smuzhiyun int si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *core,
521*4882a593Smuzhiyun enum si476x_dclk_config dclk,
522*4882a593Smuzhiyun enum si476x_dfs_config dfs,
523*4882a593Smuzhiyun enum si476x_dout_config dout,
524*4882a593Smuzhiyun enum si476x_xout_config xout)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun u8 resp[CMD_DIG_AUDIO_PIN_CFG_NRESP];
527*4882a593Smuzhiyun const u8 args[CMD_DIG_AUDIO_PIN_CFG_NARGS] = {
528*4882a593Smuzhiyun PIN_CFG_BYTE(dclk),
529*4882a593Smuzhiyun PIN_CFG_BYTE(dfs),
530*4882a593Smuzhiyun PIN_CFG_BYTE(dout),
531*4882a593Smuzhiyun PIN_CFG_BYTE(xout),
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_DIG_AUDIO_PIN_CFG,
535*4882a593Smuzhiyun args, ARRAY_SIZE(args),
536*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
537*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_dig_audio_pin_cfg);
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /**
542*4882a593Smuzhiyun * si476x_cmd_zif_pin_cfg - send 'ZIF_PIN_CFG_COMMAND'
543*4882a593Smuzhiyun * @core: - device to send the command to
544*4882a593Smuzhiyun * @iqclk: - IQCL pin function configuration:
545*4882a593Smuzhiyun * SI476X_IQCLK_NOOP - do not modify the behaviour
546*4882a593Smuzhiyun * SI476X_IQCLK_TRISTATE - put the pin in tristate condition,
547*4882a593Smuzhiyun * enable 1MOhm pulldown
548*4882a593Smuzhiyun * SI476X_IQCLK_IQ - set pin to be a part of I/Q interace
549*4882a593Smuzhiyun * in master mode
550*4882a593Smuzhiyun * @iqfs: - IQFS pin function configuration:
551*4882a593Smuzhiyun * SI476X_IQFS_NOOP - do not modify the behaviour
552*4882a593Smuzhiyun * SI476X_IQFS_TRISTATE - put the pin in tristate condition,
553*4882a593Smuzhiyun * enable 1MOhm pulldown
554*4882a593Smuzhiyun * SI476X_IQFS_IQ - set pin to be a part of I/Q interace
555*4882a593Smuzhiyun * in master mode
556*4882a593Smuzhiyun * @iout: - IOUT pin function configuration:
557*4882a593Smuzhiyun * SI476X_IOUT_NOOP - do not modify the behaviour
558*4882a593Smuzhiyun * SI476X_IOUT_TRISTATE - put the pin in tristate condition,
559*4882a593Smuzhiyun * enable 1MOhm pulldown
560*4882a593Smuzhiyun * SI476X_IOUT_OUTPUT - set pin to be I out
561*4882a593Smuzhiyun * @qout: - QOUT pin function configuration:
562*4882a593Smuzhiyun * SI476X_QOUT_NOOP - do not modify the behaviour
563*4882a593Smuzhiyun * SI476X_QOUT_TRISTATE - put the pin in tristate condition,
564*4882a593Smuzhiyun * enable 1MOhm pulldown
565*4882a593Smuzhiyun * SI476X_QOUT_OUTPUT - set pin to be Q out
566*4882a593Smuzhiyun *
567*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
568*4882a593Smuzhiyun */
si476x_core_cmd_zif_pin_cfg(struct si476x_core * core,enum si476x_iqclk_config iqclk,enum si476x_iqfs_config iqfs,enum si476x_iout_config iout,enum si476x_qout_config qout)569*4882a593Smuzhiyun int si476x_core_cmd_zif_pin_cfg(struct si476x_core *core,
570*4882a593Smuzhiyun enum si476x_iqclk_config iqclk,
571*4882a593Smuzhiyun enum si476x_iqfs_config iqfs,
572*4882a593Smuzhiyun enum si476x_iout_config iout,
573*4882a593Smuzhiyun enum si476x_qout_config qout)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun u8 resp[CMD_ZIF_PIN_CFG_NRESP];
576*4882a593Smuzhiyun const u8 args[CMD_ZIF_PIN_CFG_NARGS] = {
577*4882a593Smuzhiyun PIN_CFG_BYTE(iqclk),
578*4882a593Smuzhiyun PIN_CFG_BYTE(iqfs),
579*4882a593Smuzhiyun PIN_CFG_BYTE(iout),
580*4882a593Smuzhiyun PIN_CFG_BYTE(qout),
581*4882a593Smuzhiyun };
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_ZIF_PIN_CFG,
584*4882a593Smuzhiyun args, ARRAY_SIZE(args),
585*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
586*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_zif_pin_cfg);
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /**
591*4882a593Smuzhiyun * si476x_cmd_ic_link_gpo_ctl_pin_cfg - send
592*4882a593Smuzhiyun * 'IC_LINK_GPIO_CTL_PIN_CFG' comand to the device
593*4882a593Smuzhiyun * @core: - device to send the command to
594*4882a593Smuzhiyun * @icin: - ICIN pin function configuration:
595*4882a593Smuzhiyun * SI476X_ICIN_NOOP - do not modify the behaviour
596*4882a593Smuzhiyun * SI476X_ICIN_TRISTATE - put the pin in tristate condition,
597*4882a593Smuzhiyun * enable 1MOhm pulldown
598*4882a593Smuzhiyun * SI476X_ICIN_GPO1_HIGH - set pin to be an output, drive it high
599*4882a593Smuzhiyun * SI476X_ICIN_GPO1_LOW - set pin to be an output, drive it low
600*4882a593Smuzhiyun * SI476X_ICIN_IC_LINK - set the pin to be a part of Inter-Chip link
601*4882a593Smuzhiyun * @icip: - ICIP pin function configuration:
602*4882a593Smuzhiyun * SI476X_ICIP_NOOP - do not modify the behaviour
603*4882a593Smuzhiyun * SI476X_ICIP_TRISTATE - put the pin in tristate condition,
604*4882a593Smuzhiyun * enable 1MOhm pulldown
605*4882a593Smuzhiyun * SI476X_ICIP_GPO1_HIGH - set pin to be an output, drive it high
606*4882a593Smuzhiyun * SI476X_ICIP_GPO1_LOW - set pin to be an output, drive it low
607*4882a593Smuzhiyun * SI476X_ICIP_IC_LINK - set the pin to be a part of Inter-Chip link
608*4882a593Smuzhiyun * @icon: - ICON pin function configuration:
609*4882a593Smuzhiyun * SI476X_ICON_NOOP - do not modify the behaviour
610*4882a593Smuzhiyun * SI476X_ICON_TRISTATE - put the pin in tristate condition,
611*4882a593Smuzhiyun * enable 1MOhm pulldown
612*4882a593Smuzhiyun * SI476X_ICON_I2S - set the pin to be a part of audio
613*4882a593Smuzhiyun * interface in slave mode (DCLK)
614*4882a593Smuzhiyun * SI476X_ICON_IC_LINK - set the pin to be a part of Inter-Chip link
615*4882a593Smuzhiyun * @icop: - ICOP pin function configuration:
616*4882a593Smuzhiyun * SI476X_ICOP_NOOP - do not modify the behaviour
617*4882a593Smuzhiyun * SI476X_ICOP_TRISTATE - put the pin in tristate condition,
618*4882a593Smuzhiyun * enable 1MOhm pulldown
619*4882a593Smuzhiyun * SI476X_ICOP_I2S - set the pin to be a part of audio
620*4882a593Smuzhiyun * interface in slave mode (DOUT)
621*4882a593Smuzhiyun * [Si4761/63/65/67 Only]
622*4882a593Smuzhiyun * SI476X_ICOP_IC_LINK - set the pin to be a part of Inter-Chip link
623*4882a593Smuzhiyun *
624*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
625*4882a593Smuzhiyun */
si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core * core,enum si476x_icin_config icin,enum si476x_icip_config icip,enum si476x_icon_config icon,enum si476x_icop_config icop)626*4882a593Smuzhiyun int si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core *core,
627*4882a593Smuzhiyun enum si476x_icin_config icin,
628*4882a593Smuzhiyun enum si476x_icip_config icip,
629*4882a593Smuzhiyun enum si476x_icon_config icon,
630*4882a593Smuzhiyun enum si476x_icop_config icop)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun u8 resp[CMD_IC_LINK_GPO_CTL_PIN_CFG_NRESP];
633*4882a593Smuzhiyun const u8 args[CMD_IC_LINK_GPO_CTL_PIN_CFG_NARGS] = {
634*4882a593Smuzhiyun PIN_CFG_BYTE(icin),
635*4882a593Smuzhiyun PIN_CFG_BYTE(icip),
636*4882a593Smuzhiyun PIN_CFG_BYTE(icon),
637*4882a593Smuzhiyun PIN_CFG_BYTE(icop),
638*4882a593Smuzhiyun };
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_IC_LINK_GPO_CTL_PIN_CFG,
641*4882a593Smuzhiyun args, ARRAY_SIZE(args),
642*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
643*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_ic_link_gpo_ctl_pin_cfg);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /**
648*4882a593Smuzhiyun * si476x_cmd_ana_audio_pin_cfg - send 'ANA_AUDIO_PIN_CFG' to the
649*4882a593Smuzhiyun * device
650*4882a593Smuzhiyun * @core: - device to send the command to
651*4882a593Smuzhiyun * @lrout: - LROUT pin function configuration:
652*4882a593Smuzhiyun * SI476X_LROUT_NOOP - do not modify the behaviour
653*4882a593Smuzhiyun * SI476X_LROUT_TRISTATE - put the pin in tristate condition,
654*4882a593Smuzhiyun * enable 1MOhm pulldown
655*4882a593Smuzhiyun * SI476X_LROUT_AUDIO - set pin to be audio output
656*4882a593Smuzhiyun * SI476X_LROUT_MPX - set pin to be MPX output
657*4882a593Smuzhiyun *
658*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
659*4882a593Smuzhiyun */
si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core * core,enum si476x_lrout_config lrout)660*4882a593Smuzhiyun int si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core *core,
661*4882a593Smuzhiyun enum si476x_lrout_config lrout)
662*4882a593Smuzhiyun {
663*4882a593Smuzhiyun u8 resp[CMD_ANA_AUDIO_PIN_CFG_NRESP];
664*4882a593Smuzhiyun const u8 args[CMD_ANA_AUDIO_PIN_CFG_NARGS] = {
665*4882a593Smuzhiyun PIN_CFG_BYTE(lrout),
666*4882a593Smuzhiyun };
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_ANA_AUDIO_PIN_CFG,
669*4882a593Smuzhiyun args, ARRAY_SIZE(args),
670*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
671*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_ana_audio_pin_cfg);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun /**
677*4882a593Smuzhiyun * si476x_cmd_intb_pin_cfg - send 'INTB_PIN_CFG' command to the device
678*4882a593Smuzhiyun * @core: - device to send the command to
679*4882a593Smuzhiyun * @intb: - INTB pin function configuration:
680*4882a593Smuzhiyun * SI476X_INTB_NOOP - do not modify the behaviour
681*4882a593Smuzhiyun * SI476X_INTB_TRISTATE - put the pin in tristate condition,
682*4882a593Smuzhiyun * enable 1MOhm pulldown
683*4882a593Smuzhiyun * SI476X_INTB_DAUDIO - set pin to be a part of digital
684*4882a593Smuzhiyun * audio interface in slave mode
685*4882a593Smuzhiyun * SI476X_INTB_IRQ - set pin to be an interrupt request line
686*4882a593Smuzhiyun * @a1: - A1 pin function configuration:
687*4882a593Smuzhiyun * SI476X_A1_NOOP - do not modify the behaviour
688*4882a593Smuzhiyun * SI476X_A1_TRISTATE - put the pin in tristate condition,
689*4882a593Smuzhiyun * enable 1MOhm pulldown
690*4882a593Smuzhiyun * SI476X_A1_IRQ - set pin to be an interrupt request line
691*4882a593Smuzhiyun *
692*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
693*4882a593Smuzhiyun */
si476x_core_cmd_intb_pin_cfg_a10(struct si476x_core * core,enum si476x_intb_config intb,enum si476x_a1_config a1)694*4882a593Smuzhiyun static int si476x_core_cmd_intb_pin_cfg_a10(struct si476x_core *core,
695*4882a593Smuzhiyun enum si476x_intb_config intb,
696*4882a593Smuzhiyun enum si476x_a1_config a1)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun u8 resp[CMD_INTB_PIN_CFG_A10_NRESP];
699*4882a593Smuzhiyun const u8 args[CMD_INTB_PIN_CFG_NARGS] = {
700*4882a593Smuzhiyun PIN_CFG_BYTE(intb),
701*4882a593Smuzhiyun PIN_CFG_BYTE(a1),
702*4882a593Smuzhiyun };
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_INTB_PIN_CFG,
705*4882a593Smuzhiyun args, ARRAY_SIZE(args),
706*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
707*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
si476x_core_cmd_intb_pin_cfg_a20(struct si476x_core * core,enum si476x_intb_config intb,enum si476x_a1_config a1)710*4882a593Smuzhiyun static int si476x_core_cmd_intb_pin_cfg_a20(struct si476x_core *core,
711*4882a593Smuzhiyun enum si476x_intb_config intb,
712*4882a593Smuzhiyun enum si476x_a1_config a1)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun u8 resp[CMD_INTB_PIN_CFG_A20_NRESP];
715*4882a593Smuzhiyun const u8 args[CMD_INTB_PIN_CFG_NARGS] = {
716*4882a593Smuzhiyun PIN_CFG_BYTE(intb),
717*4882a593Smuzhiyun PIN_CFG_BYTE(a1),
718*4882a593Smuzhiyun };
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_INTB_PIN_CFG,
721*4882a593Smuzhiyun args, ARRAY_SIZE(args),
722*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
723*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun /**
729*4882a593Smuzhiyun * si476x_cmd_am_rsq_status - send 'AM_RSQ_STATUS' command to the
730*4882a593Smuzhiyun * device
731*4882a593Smuzhiyun * @core: - device to send the command to
732*4882a593Smuzhiyun * @rsqargs: - pointer to a structure containing a group of sub-args
733*4882a593Smuzhiyun * relevant to sending the RSQ status command
734*4882a593Smuzhiyun * @report: - all signal quality information retured by the command
735*4882a593Smuzhiyun * (if NULL then the output of the command is ignored)
736*4882a593Smuzhiyun *
737*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
738*4882a593Smuzhiyun */
si476x_core_cmd_am_rsq_status(struct si476x_core * core,struct si476x_rsq_status_args * rsqargs,struct si476x_rsq_status_report * report)739*4882a593Smuzhiyun int si476x_core_cmd_am_rsq_status(struct si476x_core *core,
740*4882a593Smuzhiyun struct si476x_rsq_status_args *rsqargs,
741*4882a593Smuzhiyun struct si476x_rsq_status_report *report)
742*4882a593Smuzhiyun {
743*4882a593Smuzhiyun int err;
744*4882a593Smuzhiyun u8 resp[CMD_AM_RSQ_STATUS_NRESP];
745*4882a593Smuzhiyun const u8 args[CMD_AM_RSQ_STATUS_NARGS] = {
746*4882a593Smuzhiyun rsqargs->rsqack << 3 | rsqargs->attune << 2 |
747*4882a593Smuzhiyun rsqargs->cancel << 1 | rsqargs->stcack,
748*4882a593Smuzhiyun };
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_AM_RSQ_STATUS,
751*4882a593Smuzhiyun args, ARRAY_SIZE(args),
752*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
753*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
754*4882a593Smuzhiyun /*
755*4882a593Smuzhiyun * Besides getting received signal quality information this
756*4882a593Smuzhiyun * command can be used to just acknowledge different interrupt
757*4882a593Smuzhiyun * flags in those cases it is useless to copy and parse
758*4882a593Smuzhiyun * received data so user can pass NULL, and thus avoid
759*4882a593Smuzhiyun * unnecessary copying.
760*4882a593Smuzhiyun */
761*4882a593Smuzhiyun if (!report)
762*4882a593Smuzhiyun return err;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun report->snrhint = 0x08 & resp[1];
765*4882a593Smuzhiyun report->snrlint = 0x04 & resp[1];
766*4882a593Smuzhiyun report->rssihint = 0x02 & resp[1];
767*4882a593Smuzhiyun report->rssilint = 0x01 & resp[1];
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun report->bltf = 0x80 & resp[2];
770*4882a593Smuzhiyun report->snr_ready = 0x20 & resp[2];
771*4882a593Smuzhiyun report->rssiready = 0x08 & resp[2];
772*4882a593Smuzhiyun report->afcrl = 0x02 & resp[2];
773*4882a593Smuzhiyun report->valid = 0x01 & resp[2];
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun report->readfreq = get_unaligned_be16(resp + 3);
776*4882a593Smuzhiyun report->freqoff = resp[5];
777*4882a593Smuzhiyun report->rssi = resp[6];
778*4882a593Smuzhiyun report->snr = resp[7];
779*4882a593Smuzhiyun report->lassi = resp[9];
780*4882a593Smuzhiyun report->hassi = resp[10];
781*4882a593Smuzhiyun report->mult = resp[11];
782*4882a593Smuzhiyun report->dev = resp[12];
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun return err;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_am_rsq_status);
787*4882a593Smuzhiyun
si476x_core_cmd_fm_acf_status(struct si476x_core * core,struct si476x_acf_status_report * report)788*4882a593Smuzhiyun int si476x_core_cmd_fm_acf_status(struct si476x_core *core,
789*4882a593Smuzhiyun struct si476x_acf_status_report *report)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun int err;
792*4882a593Smuzhiyun u8 resp[CMD_FM_ACF_STATUS_NRESP];
793*4882a593Smuzhiyun const u8 args[CMD_FM_ACF_STATUS_NARGS] = {
794*4882a593Smuzhiyun 0x0,
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun if (!report)
798*4882a593Smuzhiyun return -EINVAL;
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_ACF_STATUS,
801*4882a593Smuzhiyun args, ARRAY_SIZE(args),
802*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
803*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
804*4882a593Smuzhiyun if (err < 0)
805*4882a593Smuzhiyun return err;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun report->blend_int = resp[1] & SI476X_ACF_BLEND_INT;
808*4882a593Smuzhiyun report->hblend_int = resp[1] & SI476X_ACF_HIBLEND_INT;
809*4882a593Smuzhiyun report->hicut_int = resp[1] & SI476X_ACF_HICUT_INT;
810*4882a593Smuzhiyun report->chbw_int = resp[1] & SI476X_ACF_CHBW_INT;
811*4882a593Smuzhiyun report->softmute_int = resp[1] & SI476X_ACF_SOFTMUTE_INT;
812*4882a593Smuzhiyun report->smute = resp[2] & SI476X_ACF_SMUTE;
813*4882a593Smuzhiyun report->smattn = resp[3] & SI476X_ACF_SMATTN;
814*4882a593Smuzhiyun report->chbw = resp[4];
815*4882a593Smuzhiyun report->hicut = resp[5];
816*4882a593Smuzhiyun report->hiblend = resp[6];
817*4882a593Smuzhiyun report->pilot = resp[7] & SI476X_ACF_PILOT;
818*4882a593Smuzhiyun report->stblend = resp[7] & SI476X_ACF_STBLEND;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun return err;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_acf_status);
823*4882a593Smuzhiyun
si476x_core_cmd_am_acf_status(struct si476x_core * core,struct si476x_acf_status_report * report)824*4882a593Smuzhiyun int si476x_core_cmd_am_acf_status(struct si476x_core *core,
825*4882a593Smuzhiyun struct si476x_acf_status_report *report)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun int err;
828*4882a593Smuzhiyun u8 resp[CMD_AM_ACF_STATUS_NRESP];
829*4882a593Smuzhiyun const u8 args[CMD_AM_ACF_STATUS_NARGS] = {
830*4882a593Smuzhiyun 0x0,
831*4882a593Smuzhiyun };
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (!report)
834*4882a593Smuzhiyun return -EINVAL;
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_AM_ACF_STATUS,
837*4882a593Smuzhiyun args, ARRAY_SIZE(args),
838*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
839*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
840*4882a593Smuzhiyun if (err < 0)
841*4882a593Smuzhiyun return err;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun report->blend_int = resp[1] & SI476X_ACF_BLEND_INT;
844*4882a593Smuzhiyun report->hblend_int = resp[1] & SI476X_ACF_HIBLEND_INT;
845*4882a593Smuzhiyun report->hicut_int = resp[1] & SI476X_ACF_HICUT_INT;
846*4882a593Smuzhiyun report->chbw_int = resp[1] & SI476X_ACF_CHBW_INT;
847*4882a593Smuzhiyun report->softmute_int = resp[1] & SI476X_ACF_SOFTMUTE_INT;
848*4882a593Smuzhiyun report->smute = resp[2] & SI476X_ACF_SMUTE;
849*4882a593Smuzhiyun report->smattn = resp[3] & SI476X_ACF_SMATTN;
850*4882a593Smuzhiyun report->chbw = resp[4];
851*4882a593Smuzhiyun report->hicut = resp[5];
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun return err;
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_am_acf_status);
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun /**
859*4882a593Smuzhiyun * si476x_cmd_fm_seek_start - send 'FM_SEEK_START' command to the
860*4882a593Smuzhiyun * device
861*4882a593Smuzhiyun * @core: - device to send the command to
862*4882a593Smuzhiyun * @seekup: - if set the direction of the search is 'up'
863*4882a593Smuzhiyun * @wrap: - if set seek wraps when hitting band limit
864*4882a593Smuzhiyun *
865*4882a593Smuzhiyun * This function begins search for a valid station. The station is
866*4882a593Smuzhiyun * considered valid when 'FM_VALID_SNR_THRESHOLD' and
867*4882a593Smuzhiyun * 'FM_VALID_RSSI_THRESHOLD' and 'FM_VALID_MAX_TUNE_ERROR' criteria
868*4882a593Smuzhiyun * are met.
869*4882a593Smuzhiyun } *
870*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
871*4882a593Smuzhiyun */
si476x_core_cmd_fm_seek_start(struct si476x_core * core,bool seekup,bool wrap)872*4882a593Smuzhiyun int si476x_core_cmd_fm_seek_start(struct si476x_core *core,
873*4882a593Smuzhiyun bool seekup, bool wrap)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun u8 resp[CMD_FM_SEEK_START_NRESP];
876*4882a593Smuzhiyun const u8 args[CMD_FM_SEEK_START_NARGS] = {
877*4882a593Smuzhiyun seekup << 3 | wrap << 2,
878*4882a593Smuzhiyun };
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun return si476x_cmd_tune_seek_freq(core, CMD_FM_SEEK_START,
881*4882a593Smuzhiyun args, sizeof(args),
882*4882a593Smuzhiyun resp, sizeof(resp));
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_seek_start);
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun /**
887*4882a593Smuzhiyun * si476x_cmd_fm_rds_status - send 'FM_RDS_STATUS' command to the
888*4882a593Smuzhiyun * device
889*4882a593Smuzhiyun * @core: - device to send the command to
890*4882a593Smuzhiyun * @status_only: - if set the data is not removed from RDSFIFO,
891*4882a593Smuzhiyun * RDSFIFOUSED is not decremented and data in all the
892*4882a593Smuzhiyun * rest RDS data contains the last valid info received
893*4882a593Smuzhiyun * @mtfifo: if set the command clears RDS receive FIFO
894*4882a593Smuzhiyun * @intack: if set the command clards the RDSINT bit.
895*4882a593Smuzhiyun * @report: - all signal quality information retured by the command
896*4882a593Smuzhiyun * (if NULL then the output of the command is ignored)
897*4882a593Smuzhiyun *
898*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
899*4882a593Smuzhiyun */
si476x_core_cmd_fm_rds_status(struct si476x_core * core,bool status_only,bool mtfifo,bool intack,struct si476x_rds_status_report * report)900*4882a593Smuzhiyun int si476x_core_cmd_fm_rds_status(struct si476x_core *core,
901*4882a593Smuzhiyun bool status_only,
902*4882a593Smuzhiyun bool mtfifo,
903*4882a593Smuzhiyun bool intack,
904*4882a593Smuzhiyun struct si476x_rds_status_report *report)
905*4882a593Smuzhiyun {
906*4882a593Smuzhiyun int err;
907*4882a593Smuzhiyun u8 resp[CMD_FM_RDS_STATUS_NRESP];
908*4882a593Smuzhiyun const u8 args[CMD_FM_RDS_STATUS_NARGS] = {
909*4882a593Smuzhiyun status_only << 2 | mtfifo << 1 | intack,
910*4882a593Smuzhiyun };
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_RDS_STATUS,
913*4882a593Smuzhiyun args, ARRAY_SIZE(args),
914*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
915*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
916*4882a593Smuzhiyun /*
917*4882a593Smuzhiyun * Besides getting RDS status information this command can be
918*4882a593Smuzhiyun * used to just acknowledge different interrupt flags in those
919*4882a593Smuzhiyun * cases it is useless to copy and parse received data so user
920*4882a593Smuzhiyun * can pass NULL, and thus avoid unnecessary copying.
921*4882a593Smuzhiyun */
922*4882a593Smuzhiyun if (err < 0 || report == NULL)
923*4882a593Smuzhiyun return err;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun report->rdstpptyint = 0x10 & resp[1];
926*4882a593Smuzhiyun report->rdspiint = 0x08 & resp[1];
927*4882a593Smuzhiyun report->rdssyncint = 0x02 & resp[1];
928*4882a593Smuzhiyun report->rdsfifoint = 0x01 & resp[1];
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun report->tpptyvalid = 0x10 & resp[2];
931*4882a593Smuzhiyun report->pivalid = 0x08 & resp[2];
932*4882a593Smuzhiyun report->rdssync = 0x02 & resp[2];
933*4882a593Smuzhiyun report->rdsfifolost = 0x01 & resp[2];
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun report->tp = 0x20 & resp[3];
936*4882a593Smuzhiyun report->pty = 0x1f & resp[3];
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun report->pi = get_unaligned_be16(resp + 4);
939*4882a593Smuzhiyun report->rdsfifoused = resp[6];
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun report->ble[V4L2_RDS_BLOCK_A] = 0xc0 & resp[7];
942*4882a593Smuzhiyun report->ble[V4L2_RDS_BLOCK_B] = 0x30 & resp[7];
943*4882a593Smuzhiyun report->ble[V4L2_RDS_BLOCK_C] = 0x0c & resp[7];
944*4882a593Smuzhiyun report->ble[V4L2_RDS_BLOCK_D] = 0x03 & resp[7];
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_A].block = V4L2_RDS_BLOCK_A;
947*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_A].msb = resp[8];
948*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_A].lsb = resp[9];
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_B].block = V4L2_RDS_BLOCK_B;
951*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_B].msb = resp[10];
952*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_B].lsb = resp[11];
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_C].block = V4L2_RDS_BLOCK_C;
955*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_C].msb = resp[12];
956*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_C].lsb = resp[13];
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_D].block = V4L2_RDS_BLOCK_D;
959*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_D].msb = resp[14];
960*4882a593Smuzhiyun report->rds[V4L2_RDS_BLOCK_D].lsb = resp[15];
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun return err;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_rds_status);
965*4882a593Smuzhiyun
si476x_core_cmd_fm_rds_blockcount(struct si476x_core * core,bool clear,struct si476x_rds_blockcount_report * report)966*4882a593Smuzhiyun int si476x_core_cmd_fm_rds_blockcount(struct si476x_core *core,
967*4882a593Smuzhiyun bool clear,
968*4882a593Smuzhiyun struct si476x_rds_blockcount_report *report)
969*4882a593Smuzhiyun {
970*4882a593Smuzhiyun int err;
971*4882a593Smuzhiyun u8 resp[CMD_FM_RDS_BLOCKCOUNT_NRESP];
972*4882a593Smuzhiyun const u8 args[CMD_FM_RDS_BLOCKCOUNT_NARGS] = {
973*4882a593Smuzhiyun clear,
974*4882a593Smuzhiyun };
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun if (!report)
977*4882a593Smuzhiyun return -EINVAL;
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_RDS_BLOCKCOUNT,
980*4882a593Smuzhiyun args, ARRAY_SIZE(args),
981*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
982*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun if (!err) {
985*4882a593Smuzhiyun report->expected = get_unaligned_be16(resp + 2);
986*4882a593Smuzhiyun report->received = get_unaligned_be16(resp + 4);
987*4882a593Smuzhiyun report->uncorrectable = get_unaligned_be16(resp + 6);
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun return err;
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_rds_blockcount);
993*4882a593Smuzhiyun
si476x_core_cmd_fm_phase_diversity(struct si476x_core * core,enum si476x_phase_diversity_mode mode)994*4882a593Smuzhiyun int si476x_core_cmd_fm_phase_diversity(struct si476x_core *core,
995*4882a593Smuzhiyun enum si476x_phase_diversity_mode mode)
996*4882a593Smuzhiyun {
997*4882a593Smuzhiyun u8 resp[CMD_FM_PHASE_DIVERSITY_NRESP];
998*4882a593Smuzhiyun const u8 args[CMD_FM_PHASE_DIVERSITY_NARGS] = {
999*4882a593Smuzhiyun mode & 0x07,
1000*4882a593Smuzhiyun };
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_FM_PHASE_DIVERSITY,
1003*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1004*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1005*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_phase_diversity);
1008*4882a593Smuzhiyun /**
1009*4882a593Smuzhiyun * si476x_core_cmd_fm_phase_div_status() - get the phase diversity
1010*4882a593Smuzhiyun * status
1011*4882a593Smuzhiyun *
1012*4882a593Smuzhiyun * @core: si476x device
1013*4882a593Smuzhiyun *
1014*4882a593Smuzhiyun * NOTE caller must hold core lock
1015*4882a593Smuzhiyun *
1016*4882a593Smuzhiyun * Function returns the value of the status bit in case of success and
1017*4882a593Smuzhiyun * negative error code in case of failre.
1018*4882a593Smuzhiyun */
si476x_core_cmd_fm_phase_div_status(struct si476x_core * core)1019*4882a593Smuzhiyun int si476x_core_cmd_fm_phase_div_status(struct si476x_core *core)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun int err;
1022*4882a593Smuzhiyun u8 resp[CMD_FM_PHASE_DIV_STATUS_NRESP];
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_PHASE_DIV_STATUS,
1025*4882a593Smuzhiyun NULL, 0,
1026*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1027*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun return (err < 0) ? err : resp[1];
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_phase_div_status);
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun /**
1035*4882a593Smuzhiyun * si476x_cmd_am_seek_start - send 'FM_SEEK_START' command to the
1036*4882a593Smuzhiyun * device
1037*4882a593Smuzhiyun * @core: - device to send the command to
1038*4882a593Smuzhiyun * @seekup: - if set the direction of the search is 'up'
1039*4882a593Smuzhiyun * @wrap: - if set seek wraps when hitting band limit
1040*4882a593Smuzhiyun *
1041*4882a593Smuzhiyun * This function begins search for a valid station. The station is
1042*4882a593Smuzhiyun * considered valid when 'FM_VALID_SNR_THRESHOLD' and
1043*4882a593Smuzhiyun * 'FM_VALID_RSSI_THRESHOLD' and 'FM_VALID_MAX_TUNE_ERROR' criteria
1044*4882a593Smuzhiyun * are met.
1045*4882a593Smuzhiyun *
1046*4882a593Smuzhiyun * Function returns 0 on success and negative error code on failure
1047*4882a593Smuzhiyun */
si476x_core_cmd_am_seek_start(struct si476x_core * core,bool seekup,bool wrap)1048*4882a593Smuzhiyun int si476x_core_cmd_am_seek_start(struct si476x_core *core,
1049*4882a593Smuzhiyun bool seekup, bool wrap)
1050*4882a593Smuzhiyun {
1051*4882a593Smuzhiyun u8 resp[CMD_AM_SEEK_START_NRESP];
1052*4882a593Smuzhiyun const u8 args[CMD_AM_SEEK_START_NARGS] = {
1053*4882a593Smuzhiyun seekup << 3 | wrap << 2,
1054*4882a593Smuzhiyun };
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun return si476x_cmd_tune_seek_freq(core, CMD_AM_SEEK_START,
1057*4882a593Smuzhiyun args, sizeof(args),
1058*4882a593Smuzhiyun resp, sizeof(resp));
1059*4882a593Smuzhiyun }
1060*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_am_seek_start);
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun
si476x_core_cmd_power_up_a10(struct si476x_core * core,struct si476x_power_up_args * puargs)1064*4882a593Smuzhiyun static int si476x_core_cmd_power_up_a10(struct si476x_core *core,
1065*4882a593Smuzhiyun struct si476x_power_up_args *puargs)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun u8 resp[CMD_POWER_UP_A10_NRESP];
1068*4882a593Smuzhiyun const bool intsel = (core->pinmux.a1 == SI476X_A1_IRQ);
1069*4882a593Smuzhiyun const bool ctsen = (core->client->irq != 0);
1070*4882a593Smuzhiyun const u8 args[CMD_POWER_UP_A10_NARGS] = {
1071*4882a593Smuzhiyun 0xF7, /* Reserved, always 0xF7 */
1072*4882a593Smuzhiyun 0x3F & puargs->xcload, /* First two bits are reserved to be
1073*4882a593Smuzhiyun * zeros */
1074*4882a593Smuzhiyun ctsen << 7 | intsel << 6 | 0x07, /* Last five bits
1075*4882a593Smuzhiyun * are reserved to
1076*4882a593Smuzhiyun * be written as 0x7 */
1077*4882a593Smuzhiyun puargs->func << 4 | puargs->freq,
1078*4882a593Smuzhiyun 0x11, /* Reserved, always 0x11 */
1079*4882a593Smuzhiyun };
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_POWER_UP,
1082*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1083*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1084*4882a593Smuzhiyun SI476X_TIMEOUT_POWER_UP);
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun
si476x_core_cmd_power_up_a20(struct si476x_core * core,struct si476x_power_up_args * puargs)1087*4882a593Smuzhiyun static int si476x_core_cmd_power_up_a20(struct si476x_core *core,
1088*4882a593Smuzhiyun struct si476x_power_up_args *puargs)
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun u8 resp[CMD_POWER_UP_A20_NRESP];
1091*4882a593Smuzhiyun const bool intsel = (core->pinmux.a1 == SI476X_A1_IRQ);
1092*4882a593Smuzhiyun const bool ctsen = (core->client->irq != 0);
1093*4882a593Smuzhiyun const u8 args[CMD_POWER_UP_A20_NARGS] = {
1094*4882a593Smuzhiyun puargs->ibias6x << 7 | puargs->xstart,
1095*4882a593Smuzhiyun 0x3F & puargs->xcload, /* First two bits are reserved to be
1096*4882a593Smuzhiyun * zeros */
1097*4882a593Smuzhiyun ctsen << 7 | intsel << 6 | puargs->fastboot << 5 |
1098*4882a593Smuzhiyun puargs->xbiashc << 3 | puargs->xbias,
1099*4882a593Smuzhiyun puargs->func << 4 | puargs->freq,
1100*4882a593Smuzhiyun 0x10 | puargs->xmode,
1101*4882a593Smuzhiyun };
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_POWER_UP,
1104*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1105*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1106*4882a593Smuzhiyun SI476X_TIMEOUT_POWER_UP);
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun
si476x_core_cmd_power_down_a10(struct si476x_core * core,struct si476x_power_down_args * pdargs)1109*4882a593Smuzhiyun static int si476x_core_cmd_power_down_a10(struct si476x_core *core,
1110*4882a593Smuzhiyun struct si476x_power_down_args *pdargs)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun u8 resp[CMD_POWER_DOWN_A10_NRESP];
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_POWER_DOWN,
1115*4882a593Smuzhiyun NULL, 0,
1116*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1117*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun
si476x_core_cmd_power_down_a20(struct si476x_core * core,struct si476x_power_down_args * pdargs)1120*4882a593Smuzhiyun static int si476x_core_cmd_power_down_a20(struct si476x_core *core,
1121*4882a593Smuzhiyun struct si476x_power_down_args *pdargs)
1122*4882a593Smuzhiyun {
1123*4882a593Smuzhiyun u8 resp[CMD_POWER_DOWN_A20_NRESP];
1124*4882a593Smuzhiyun const u8 args[CMD_POWER_DOWN_A20_NARGS] = {
1125*4882a593Smuzhiyun pdargs->xosc,
1126*4882a593Smuzhiyun };
1127*4882a593Smuzhiyun return si476x_core_send_command(core, CMD_POWER_DOWN,
1128*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1129*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1130*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1131*4882a593Smuzhiyun }
1132*4882a593Smuzhiyun
si476x_core_cmd_am_tune_freq_a10(struct si476x_core * core,struct si476x_tune_freq_args * tuneargs)1133*4882a593Smuzhiyun static int si476x_core_cmd_am_tune_freq_a10(struct si476x_core *core,
1134*4882a593Smuzhiyun struct si476x_tune_freq_args *tuneargs)
1135*4882a593Smuzhiyun {
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun const int am_freq = tuneargs->freq;
1138*4882a593Smuzhiyun u8 resp[CMD_AM_TUNE_FREQ_NRESP];
1139*4882a593Smuzhiyun const u8 args[CMD_AM_TUNE_FREQ_NARGS] = {
1140*4882a593Smuzhiyun (tuneargs->hd << 6),
1141*4882a593Smuzhiyun msb(am_freq),
1142*4882a593Smuzhiyun lsb(am_freq),
1143*4882a593Smuzhiyun };
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun return si476x_cmd_tune_seek_freq(core, CMD_AM_TUNE_FREQ, args,
1146*4882a593Smuzhiyun sizeof(args),
1147*4882a593Smuzhiyun resp, sizeof(resp));
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun
si476x_core_cmd_am_tune_freq_a20(struct si476x_core * core,struct si476x_tune_freq_args * tuneargs)1150*4882a593Smuzhiyun static int si476x_core_cmd_am_tune_freq_a20(struct si476x_core *core,
1151*4882a593Smuzhiyun struct si476x_tune_freq_args *tuneargs)
1152*4882a593Smuzhiyun {
1153*4882a593Smuzhiyun const int am_freq = tuneargs->freq;
1154*4882a593Smuzhiyun u8 resp[CMD_AM_TUNE_FREQ_NRESP];
1155*4882a593Smuzhiyun const u8 args[CMD_AM_TUNE_FREQ_NARGS] = {
1156*4882a593Smuzhiyun (tuneargs->zifsr << 6) | (tuneargs->injside & 0x03),
1157*4882a593Smuzhiyun msb(am_freq),
1158*4882a593Smuzhiyun lsb(am_freq),
1159*4882a593Smuzhiyun };
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun return si476x_cmd_tune_seek_freq(core, CMD_AM_TUNE_FREQ,
1162*4882a593Smuzhiyun args, sizeof(args),
1163*4882a593Smuzhiyun resp, sizeof(resp));
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
si476x_core_cmd_fm_rsq_status_a10(struct si476x_core * core,struct si476x_rsq_status_args * rsqargs,struct si476x_rsq_status_report * report)1166*4882a593Smuzhiyun static int si476x_core_cmd_fm_rsq_status_a10(struct si476x_core *core,
1167*4882a593Smuzhiyun struct si476x_rsq_status_args *rsqargs,
1168*4882a593Smuzhiyun struct si476x_rsq_status_report *report)
1169*4882a593Smuzhiyun {
1170*4882a593Smuzhiyun int err;
1171*4882a593Smuzhiyun u8 resp[CMD_FM_RSQ_STATUS_A10_NRESP];
1172*4882a593Smuzhiyun const u8 args[CMD_FM_RSQ_STATUS_A10_NARGS] = {
1173*4882a593Smuzhiyun rsqargs->rsqack << 3 | rsqargs->attune << 2 |
1174*4882a593Smuzhiyun rsqargs->cancel << 1 | rsqargs->stcack,
1175*4882a593Smuzhiyun };
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_RSQ_STATUS,
1178*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1179*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1180*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1181*4882a593Smuzhiyun /*
1182*4882a593Smuzhiyun * Besides getting received signal quality information this
1183*4882a593Smuzhiyun * command can be used to just acknowledge different interrupt
1184*4882a593Smuzhiyun * flags in those cases it is useless to copy and parse
1185*4882a593Smuzhiyun * received data so user can pass NULL, and thus avoid
1186*4882a593Smuzhiyun * unnecessary copying.
1187*4882a593Smuzhiyun */
1188*4882a593Smuzhiyun if (err < 0 || report == NULL)
1189*4882a593Smuzhiyun return err;
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun report->multhint = 0x80 & resp[1];
1192*4882a593Smuzhiyun report->multlint = 0x40 & resp[1];
1193*4882a593Smuzhiyun report->snrhint = 0x08 & resp[1];
1194*4882a593Smuzhiyun report->snrlint = 0x04 & resp[1];
1195*4882a593Smuzhiyun report->rssihint = 0x02 & resp[1];
1196*4882a593Smuzhiyun report->rssilint = 0x01 & resp[1];
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun report->bltf = 0x80 & resp[2];
1199*4882a593Smuzhiyun report->snr_ready = 0x20 & resp[2];
1200*4882a593Smuzhiyun report->rssiready = 0x08 & resp[2];
1201*4882a593Smuzhiyun report->afcrl = 0x02 & resp[2];
1202*4882a593Smuzhiyun report->valid = 0x01 & resp[2];
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun report->readfreq = get_unaligned_be16(resp + 3);
1205*4882a593Smuzhiyun report->freqoff = resp[5];
1206*4882a593Smuzhiyun report->rssi = resp[6];
1207*4882a593Smuzhiyun report->snr = resp[7];
1208*4882a593Smuzhiyun report->lassi = resp[9];
1209*4882a593Smuzhiyun report->hassi = resp[10];
1210*4882a593Smuzhiyun report->mult = resp[11];
1211*4882a593Smuzhiyun report->dev = resp[12];
1212*4882a593Smuzhiyun report->readantcap = get_unaligned_be16(resp + 13);
1213*4882a593Smuzhiyun report->assi = resp[15];
1214*4882a593Smuzhiyun report->usn = resp[16];
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun return err;
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun
si476x_core_cmd_fm_rsq_status_a20(struct si476x_core * core,struct si476x_rsq_status_args * rsqargs,struct si476x_rsq_status_report * report)1219*4882a593Smuzhiyun static int si476x_core_cmd_fm_rsq_status_a20(struct si476x_core *core,
1220*4882a593Smuzhiyun struct si476x_rsq_status_args *rsqargs,
1221*4882a593Smuzhiyun struct si476x_rsq_status_report *report)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun int err;
1224*4882a593Smuzhiyun u8 resp[CMD_FM_RSQ_STATUS_A10_NRESP];
1225*4882a593Smuzhiyun const u8 args[CMD_FM_RSQ_STATUS_A30_NARGS] = {
1226*4882a593Smuzhiyun rsqargs->primary << 4 | rsqargs->rsqack << 3 |
1227*4882a593Smuzhiyun rsqargs->attune << 2 | rsqargs->cancel << 1 |
1228*4882a593Smuzhiyun rsqargs->stcack,
1229*4882a593Smuzhiyun };
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_RSQ_STATUS,
1232*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1233*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1234*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1235*4882a593Smuzhiyun /*
1236*4882a593Smuzhiyun * Besides getting received signal quality information this
1237*4882a593Smuzhiyun * command can be used to just acknowledge different interrupt
1238*4882a593Smuzhiyun * flags in those cases it is useless to copy and parse
1239*4882a593Smuzhiyun * received data so user can pass NULL, and thus avoid
1240*4882a593Smuzhiyun * unnecessary copying.
1241*4882a593Smuzhiyun */
1242*4882a593Smuzhiyun if (err < 0 || report == NULL)
1243*4882a593Smuzhiyun return err;
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun report->multhint = 0x80 & resp[1];
1246*4882a593Smuzhiyun report->multlint = 0x40 & resp[1];
1247*4882a593Smuzhiyun report->snrhint = 0x08 & resp[1];
1248*4882a593Smuzhiyun report->snrlint = 0x04 & resp[1];
1249*4882a593Smuzhiyun report->rssihint = 0x02 & resp[1];
1250*4882a593Smuzhiyun report->rssilint = 0x01 & resp[1];
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun report->bltf = 0x80 & resp[2];
1253*4882a593Smuzhiyun report->snr_ready = 0x20 & resp[2];
1254*4882a593Smuzhiyun report->rssiready = 0x08 & resp[2];
1255*4882a593Smuzhiyun report->afcrl = 0x02 & resp[2];
1256*4882a593Smuzhiyun report->valid = 0x01 & resp[2];
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun report->readfreq = get_unaligned_be16(resp + 3);
1259*4882a593Smuzhiyun report->freqoff = resp[5];
1260*4882a593Smuzhiyun report->rssi = resp[6];
1261*4882a593Smuzhiyun report->snr = resp[7];
1262*4882a593Smuzhiyun report->lassi = resp[9];
1263*4882a593Smuzhiyun report->hassi = resp[10];
1264*4882a593Smuzhiyun report->mult = resp[11];
1265*4882a593Smuzhiyun report->dev = resp[12];
1266*4882a593Smuzhiyun report->readantcap = get_unaligned_be16(resp + 13);
1267*4882a593Smuzhiyun report->assi = resp[15];
1268*4882a593Smuzhiyun report->usn = resp[16];
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun return err;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun
si476x_core_cmd_fm_rsq_status_a30(struct si476x_core * core,struct si476x_rsq_status_args * rsqargs,struct si476x_rsq_status_report * report)1274*4882a593Smuzhiyun static int si476x_core_cmd_fm_rsq_status_a30(struct si476x_core *core,
1275*4882a593Smuzhiyun struct si476x_rsq_status_args *rsqargs,
1276*4882a593Smuzhiyun struct si476x_rsq_status_report *report)
1277*4882a593Smuzhiyun {
1278*4882a593Smuzhiyun int err;
1279*4882a593Smuzhiyun u8 resp[CMD_FM_RSQ_STATUS_A30_NRESP];
1280*4882a593Smuzhiyun const u8 args[CMD_FM_RSQ_STATUS_A30_NARGS] = {
1281*4882a593Smuzhiyun rsqargs->primary << 4 | rsqargs->rsqack << 3 |
1282*4882a593Smuzhiyun rsqargs->attune << 2 | rsqargs->cancel << 1 |
1283*4882a593Smuzhiyun rsqargs->stcack,
1284*4882a593Smuzhiyun };
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_FM_RSQ_STATUS,
1287*4882a593Smuzhiyun args, ARRAY_SIZE(args),
1288*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1289*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1290*4882a593Smuzhiyun /*
1291*4882a593Smuzhiyun * Besides getting received signal quality information this
1292*4882a593Smuzhiyun * command can be used to just acknowledge different interrupt
1293*4882a593Smuzhiyun * flags in those cases it is useless to copy and parse
1294*4882a593Smuzhiyun * received data so user can pass NULL, and thus avoid
1295*4882a593Smuzhiyun * unnecessary copying.
1296*4882a593Smuzhiyun */
1297*4882a593Smuzhiyun if (err < 0 || report == NULL)
1298*4882a593Smuzhiyun return err;
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun report->multhint = 0x80 & resp[1];
1301*4882a593Smuzhiyun report->multlint = 0x40 & resp[1];
1302*4882a593Smuzhiyun report->snrhint = 0x08 & resp[1];
1303*4882a593Smuzhiyun report->snrlint = 0x04 & resp[1];
1304*4882a593Smuzhiyun report->rssihint = 0x02 & resp[1];
1305*4882a593Smuzhiyun report->rssilint = 0x01 & resp[1];
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun report->bltf = 0x80 & resp[2];
1308*4882a593Smuzhiyun report->snr_ready = 0x20 & resp[2];
1309*4882a593Smuzhiyun report->rssiready = 0x08 & resp[2];
1310*4882a593Smuzhiyun report->injside = 0x04 & resp[2];
1311*4882a593Smuzhiyun report->afcrl = 0x02 & resp[2];
1312*4882a593Smuzhiyun report->valid = 0x01 & resp[2];
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun report->readfreq = get_unaligned_be16(resp + 3);
1315*4882a593Smuzhiyun report->freqoff = resp[5];
1316*4882a593Smuzhiyun report->rssi = resp[6];
1317*4882a593Smuzhiyun report->snr = resp[7];
1318*4882a593Smuzhiyun report->issi = resp[8];
1319*4882a593Smuzhiyun report->lassi = resp[9];
1320*4882a593Smuzhiyun report->hassi = resp[10];
1321*4882a593Smuzhiyun report->mult = resp[11];
1322*4882a593Smuzhiyun report->dev = resp[12];
1323*4882a593Smuzhiyun report->readantcap = get_unaligned_be16(resp + 13);
1324*4882a593Smuzhiyun report->assi = resp[15];
1325*4882a593Smuzhiyun report->usn = resp[16];
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun report->pilotdev = resp[17];
1328*4882a593Smuzhiyun report->rdsdev = resp[18];
1329*4882a593Smuzhiyun report->assidev = resp[19];
1330*4882a593Smuzhiyun report->strongdev = resp[20];
1331*4882a593Smuzhiyun report->rdspi = get_unaligned_be16(resp + 21);
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun return err;
1334*4882a593Smuzhiyun }
1335*4882a593Smuzhiyun
si476x_core_cmd_fm_tune_freq_a10(struct si476x_core * core,struct si476x_tune_freq_args * tuneargs)1336*4882a593Smuzhiyun static int si476x_core_cmd_fm_tune_freq_a10(struct si476x_core *core,
1337*4882a593Smuzhiyun struct si476x_tune_freq_args *tuneargs)
1338*4882a593Smuzhiyun {
1339*4882a593Smuzhiyun u8 resp[CMD_FM_TUNE_FREQ_NRESP];
1340*4882a593Smuzhiyun const u8 args[CMD_FM_TUNE_FREQ_A10_NARGS] = {
1341*4882a593Smuzhiyun (tuneargs->hd << 6) | (tuneargs->tunemode << 4)
1342*4882a593Smuzhiyun | (tuneargs->smoothmetrics << 2),
1343*4882a593Smuzhiyun msb(tuneargs->freq),
1344*4882a593Smuzhiyun lsb(tuneargs->freq),
1345*4882a593Smuzhiyun msb(tuneargs->antcap),
1346*4882a593Smuzhiyun lsb(tuneargs->antcap)
1347*4882a593Smuzhiyun };
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun return si476x_cmd_tune_seek_freq(core, CMD_FM_TUNE_FREQ,
1350*4882a593Smuzhiyun args, sizeof(args),
1351*4882a593Smuzhiyun resp, sizeof(resp));
1352*4882a593Smuzhiyun }
1353*4882a593Smuzhiyun
si476x_core_cmd_fm_tune_freq_a20(struct si476x_core * core,struct si476x_tune_freq_args * tuneargs)1354*4882a593Smuzhiyun static int si476x_core_cmd_fm_tune_freq_a20(struct si476x_core *core,
1355*4882a593Smuzhiyun struct si476x_tune_freq_args *tuneargs)
1356*4882a593Smuzhiyun {
1357*4882a593Smuzhiyun u8 resp[CMD_FM_TUNE_FREQ_NRESP];
1358*4882a593Smuzhiyun const u8 args[CMD_FM_TUNE_FREQ_A20_NARGS] = {
1359*4882a593Smuzhiyun (tuneargs->hd << 6) | (tuneargs->tunemode << 4)
1360*4882a593Smuzhiyun | (tuneargs->smoothmetrics << 2) | (tuneargs->injside),
1361*4882a593Smuzhiyun msb(tuneargs->freq),
1362*4882a593Smuzhiyun lsb(tuneargs->freq),
1363*4882a593Smuzhiyun };
1364*4882a593Smuzhiyun
1365*4882a593Smuzhiyun return si476x_cmd_tune_seek_freq(core, CMD_FM_TUNE_FREQ,
1366*4882a593Smuzhiyun args, sizeof(args),
1367*4882a593Smuzhiyun resp, sizeof(resp));
1368*4882a593Smuzhiyun }
1369*4882a593Smuzhiyun
si476x_core_cmd_agc_status_a20(struct si476x_core * core,struct si476x_agc_status_report * report)1370*4882a593Smuzhiyun static int si476x_core_cmd_agc_status_a20(struct si476x_core *core,
1371*4882a593Smuzhiyun struct si476x_agc_status_report *report)
1372*4882a593Smuzhiyun {
1373*4882a593Smuzhiyun int err;
1374*4882a593Smuzhiyun u8 resp[CMD_AGC_STATUS_NRESP_A20];
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun if (!report)
1377*4882a593Smuzhiyun return -EINVAL;
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_AGC_STATUS,
1380*4882a593Smuzhiyun NULL, 0,
1381*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1382*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1383*4882a593Smuzhiyun if (err < 0)
1384*4882a593Smuzhiyun return err;
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun report->mxhi = resp[1] & SI476X_AGC_MXHI;
1387*4882a593Smuzhiyun report->mxlo = resp[1] & SI476X_AGC_MXLO;
1388*4882a593Smuzhiyun report->lnahi = resp[1] & SI476X_AGC_LNAHI;
1389*4882a593Smuzhiyun report->lnalo = resp[1] & SI476X_AGC_LNALO;
1390*4882a593Smuzhiyun report->fmagc1 = resp[2];
1391*4882a593Smuzhiyun report->fmagc2 = resp[3];
1392*4882a593Smuzhiyun report->pgagain = resp[4];
1393*4882a593Smuzhiyun report->fmwblang = resp[5];
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun return err;
1396*4882a593Smuzhiyun }
1397*4882a593Smuzhiyun
si476x_core_cmd_agc_status_a10(struct si476x_core * core,struct si476x_agc_status_report * report)1398*4882a593Smuzhiyun static int si476x_core_cmd_agc_status_a10(struct si476x_core *core,
1399*4882a593Smuzhiyun struct si476x_agc_status_report *report)
1400*4882a593Smuzhiyun {
1401*4882a593Smuzhiyun int err;
1402*4882a593Smuzhiyun u8 resp[CMD_AGC_STATUS_NRESP_A10];
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun if (!report)
1405*4882a593Smuzhiyun return -EINVAL;
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun err = si476x_core_send_command(core, CMD_AGC_STATUS,
1408*4882a593Smuzhiyun NULL, 0,
1409*4882a593Smuzhiyun resp, ARRAY_SIZE(resp),
1410*4882a593Smuzhiyun SI476X_DEFAULT_TIMEOUT);
1411*4882a593Smuzhiyun if (err < 0)
1412*4882a593Smuzhiyun return err;
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun report->mxhi = resp[1] & SI476X_AGC_MXHI;
1415*4882a593Smuzhiyun report->mxlo = resp[1] & SI476X_AGC_MXLO;
1416*4882a593Smuzhiyun report->lnahi = resp[1] & SI476X_AGC_LNAHI;
1417*4882a593Smuzhiyun report->lnalo = resp[1] & SI476X_AGC_LNALO;
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun return err;
1420*4882a593Smuzhiyun }
1421*4882a593Smuzhiyun
1422*4882a593Smuzhiyun typedef int (*tune_freq_func_t) (struct si476x_core *core,
1423*4882a593Smuzhiyun struct si476x_tune_freq_args *tuneargs);
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun static struct {
1426*4882a593Smuzhiyun int (*power_up)(struct si476x_core *,
1427*4882a593Smuzhiyun struct si476x_power_up_args *);
1428*4882a593Smuzhiyun int (*power_down)(struct si476x_core *,
1429*4882a593Smuzhiyun struct si476x_power_down_args *);
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun tune_freq_func_t fm_tune_freq;
1432*4882a593Smuzhiyun tune_freq_func_t am_tune_freq;
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun int (*fm_rsq_status)(struct si476x_core *,
1435*4882a593Smuzhiyun struct si476x_rsq_status_args *,
1436*4882a593Smuzhiyun struct si476x_rsq_status_report *);
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun int (*agc_status)(struct si476x_core *,
1439*4882a593Smuzhiyun struct si476x_agc_status_report *);
1440*4882a593Smuzhiyun int (*intb_pin_cfg)(struct si476x_core *core,
1441*4882a593Smuzhiyun enum si476x_intb_config intb,
1442*4882a593Smuzhiyun enum si476x_a1_config a1);
1443*4882a593Smuzhiyun } si476x_cmds_vtable[] = {
1444*4882a593Smuzhiyun [SI476X_REVISION_A10] = {
1445*4882a593Smuzhiyun .power_up = si476x_core_cmd_power_up_a10,
1446*4882a593Smuzhiyun .power_down = si476x_core_cmd_power_down_a10,
1447*4882a593Smuzhiyun .fm_tune_freq = si476x_core_cmd_fm_tune_freq_a10,
1448*4882a593Smuzhiyun .am_tune_freq = si476x_core_cmd_am_tune_freq_a10,
1449*4882a593Smuzhiyun .fm_rsq_status = si476x_core_cmd_fm_rsq_status_a10,
1450*4882a593Smuzhiyun .agc_status = si476x_core_cmd_agc_status_a10,
1451*4882a593Smuzhiyun .intb_pin_cfg = si476x_core_cmd_intb_pin_cfg_a10,
1452*4882a593Smuzhiyun },
1453*4882a593Smuzhiyun [SI476X_REVISION_A20] = {
1454*4882a593Smuzhiyun .power_up = si476x_core_cmd_power_up_a20,
1455*4882a593Smuzhiyun .power_down = si476x_core_cmd_power_down_a20,
1456*4882a593Smuzhiyun .fm_tune_freq = si476x_core_cmd_fm_tune_freq_a20,
1457*4882a593Smuzhiyun .am_tune_freq = si476x_core_cmd_am_tune_freq_a20,
1458*4882a593Smuzhiyun .fm_rsq_status = si476x_core_cmd_fm_rsq_status_a20,
1459*4882a593Smuzhiyun .agc_status = si476x_core_cmd_agc_status_a20,
1460*4882a593Smuzhiyun .intb_pin_cfg = si476x_core_cmd_intb_pin_cfg_a20,
1461*4882a593Smuzhiyun },
1462*4882a593Smuzhiyun [SI476X_REVISION_A30] = {
1463*4882a593Smuzhiyun .power_up = si476x_core_cmd_power_up_a20,
1464*4882a593Smuzhiyun .power_down = si476x_core_cmd_power_down_a20,
1465*4882a593Smuzhiyun .fm_tune_freq = si476x_core_cmd_fm_tune_freq_a20,
1466*4882a593Smuzhiyun .am_tune_freq = si476x_core_cmd_am_tune_freq_a20,
1467*4882a593Smuzhiyun .fm_rsq_status = si476x_core_cmd_fm_rsq_status_a30,
1468*4882a593Smuzhiyun .agc_status = si476x_core_cmd_agc_status_a20,
1469*4882a593Smuzhiyun .intb_pin_cfg = si476x_core_cmd_intb_pin_cfg_a20,
1470*4882a593Smuzhiyun },
1471*4882a593Smuzhiyun };
1472*4882a593Smuzhiyun
si476x_core_cmd_power_up(struct si476x_core * core,struct si476x_power_up_args * args)1473*4882a593Smuzhiyun int si476x_core_cmd_power_up(struct si476x_core *core,
1474*4882a593Smuzhiyun struct si476x_power_up_args *args)
1475*4882a593Smuzhiyun {
1476*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1477*4882a593Smuzhiyun core->revision == -1);
1478*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].power_up(core, args);
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_power_up);
1481*4882a593Smuzhiyun
si476x_core_cmd_power_down(struct si476x_core * core,struct si476x_power_down_args * args)1482*4882a593Smuzhiyun int si476x_core_cmd_power_down(struct si476x_core *core,
1483*4882a593Smuzhiyun struct si476x_power_down_args *args)
1484*4882a593Smuzhiyun {
1485*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1486*4882a593Smuzhiyun core->revision == -1);
1487*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].power_down(core, args);
1488*4882a593Smuzhiyun }
1489*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_power_down);
1490*4882a593Smuzhiyun
si476x_core_cmd_fm_tune_freq(struct si476x_core * core,struct si476x_tune_freq_args * args)1491*4882a593Smuzhiyun int si476x_core_cmd_fm_tune_freq(struct si476x_core *core,
1492*4882a593Smuzhiyun struct si476x_tune_freq_args *args)
1493*4882a593Smuzhiyun {
1494*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1495*4882a593Smuzhiyun core->revision == -1);
1496*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].fm_tune_freq(core, args);
1497*4882a593Smuzhiyun }
1498*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_tune_freq);
1499*4882a593Smuzhiyun
si476x_core_cmd_am_tune_freq(struct si476x_core * core,struct si476x_tune_freq_args * args)1500*4882a593Smuzhiyun int si476x_core_cmd_am_tune_freq(struct si476x_core *core,
1501*4882a593Smuzhiyun struct si476x_tune_freq_args *args)
1502*4882a593Smuzhiyun {
1503*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1504*4882a593Smuzhiyun core->revision == -1);
1505*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].am_tune_freq(core, args);
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_am_tune_freq);
1508*4882a593Smuzhiyun
si476x_core_cmd_fm_rsq_status(struct si476x_core * core,struct si476x_rsq_status_args * args,struct si476x_rsq_status_report * report)1509*4882a593Smuzhiyun int si476x_core_cmd_fm_rsq_status(struct si476x_core *core,
1510*4882a593Smuzhiyun struct si476x_rsq_status_args *args,
1511*4882a593Smuzhiyun struct si476x_rsq_status_report *report)
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun {
1514*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1515*4882a593Smuzhiyun core->revision == -1);
1516*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].fm_rsq_status(core, args,
1517*4882a593Smuzhiyun report);
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_rsq_status);
1520*4882a593Smuzhiyun
si476x_core_cmd_agc_status(struct si476x_core * core,struct si476x_agc_status_report * report)1521*4882a593Smuzhiyun int si476x_core_cmd_agc_status(struct si476x_core *core,
1522*4882a593Smuzhiyun struct si476x_agc_status_report *report)
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun {
1525*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1526*4882a593Smuzhiyun core->revision == -1);
1527*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].agc_status(core, report);
1528*4882a593Smuzhiyun }
1529*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_agc_status);
1530*4882a593Smuzhiyun
si476x_core_cmd_intb_pin_cfg(struct si476x_core * core,enum si476x_intb_config intb,enum si476x_a1_config a1)1531*4882a593Smuzhiyun int si476x_core_cmd_intb_pin_cfg(struct si476x_core *core,
1532*4882a593Smuzhiyun enum si476x_intb_config intb,
1533*4882a593Smuzhiyun enum si476x_a1_config a1)
1534*4882a593Smuzhiyun {
1535*4882a593Smuzhiyun BUG_ON(core->revision > SI476X_REVISION_A30 ||
1536*4882a593Smuzhiyun core->revision == -1);
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun return si476x_cmds_vtable[core->revision].intb_pin_cfg(core, intb, a1);
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(si476x_core_cmd_intb_pin_cfg);
1541*4882a593Smuzhiyun
1542*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1543*4882a593Smuzhiyun MODULE_AUTHOR("Andrey Smirnov <andrew.smirnov@gmail.com>");
1544*4882a593Smuzhiyun MODULE_DESCRIPTION("API for command exchange for si476x");
1545