1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Flora Fu, MediaTek
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/interrupt.h>
8*4882a593Smuzhiyun #include <linux/ioport.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/of_irq.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/mfd/core.h>
14*4882a593Smuzhiyun #include <linux/mfd/mt6323/core.h>
15*4882a593Smuzhiyun #include <linux/mfd/mt6358/core.h>
16*4882a593Smuzhiyun #include <linux/mfd/mt6397/core.h>
17*4882a593Smuzhiyun #include <linux/mfd/mt6323/registers.h>
18*4882a593Smuzhiyun #include <linux/mfd/mt6358/registers.h>
19*4882a593Smuzhiyun #include <linux/mfd/mt6397/registers.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define MT6323_RTC_BASE 0x8000
22*4882a593Smuzhiyun #define MT6323_RTC_SIZE 0x40
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MT6358_RTC_BASE 0x0588
25*4882a593Smuzhiyun #define MT6358_RTC_SIZE 0x3c
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define MT6397_RTC_BASE 0xe000
28*4882a593Smuzhiyun #define MT6397_RTC_SIZE 0x3e
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define MT6323_PWRC_BASE 0x8000
31*4882a593Smuzhiyun #define MT6323_PWRC_SIZE 0x40
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const struct resource mt6323_rtc_resources[] = {
34*4882a593Smuzhiyun DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE),
35*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct resource mt6358_rtc_resources[] = {
39*4882a593Smuzhiyun DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
40*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6358_IRQ_RTC),
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const struct resource mt6397_rtc_resources[] = {
44*4882a593Smuzhiyun DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
45*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6397_IRQ_RTC),
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static const struct resource mt6323_keys_resources[] = {
49*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
50*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const struct resource mt6397_keys_resources[] = {
54*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
55*4882a593Smuzhiyun DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static const struct resource mt6323_pwrc_resources[] = {
59*4882a593Smuzhiyun DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE),
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static const struct mfd_cell mt6323_devs[] = {
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun .name = "mt6323-rtc",
65*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mt6323_rtc_resources),
66*4882a593Smuzhiyun .resources = mt6323_rtc_resources,
67*4882a593Smuzhiyun .of_compatible = "mediatek,mt6323-rtc",
68*4882a593Smuzhiyun }, {
69*4882a593Smuzhiyun .name = "mt6323-regulator",
70*4882a593Smuzhiyun .of_compatible = "mediatek,mt6323-regulator"
71*4882a593Smuzhiyun }, {
72*4882a593Smuzhiyun .name = "mt6323-led",
73*4882a593Smuzhiyun .of_compatible = "mediatek,mt6323-led"
74*4882a593Smuzhiyun }, {
75*4882a593Smuzhiyun .name = "mtk-pmic-keys",
76*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mt6323_keys_resources),
77*4882a593Smuzhiyun .resources = mt6323_keys_resources,
78*4882a593Smuzhiyun .of_compatible = "mediatek,mt6323-keys"
79*4882a593Smuzhiyun }, {
80*4882a593Smuzhiyun .name = "mt6323-pwrc",
81*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
82*4882a593Smuzhiyun .resources = mt6323_pwrc_resources,
83*4882a593Smuzhiyun .of_compatible = "mediatek,mt6323-pwrc"
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static const struct mfd_cell mt6358_devs[] = {
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun .name = "mt6358-regulator",
90*4882a593Smuzhiyun .of_compatible = "mediatek,mt6358-regulator"
91*4882a593Smuzhiyun }, {
92*4882a593Smuzhiyun .name = "mt6358-rtc",
93*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mt6358_rtc_resources),
94*4882a593Smuzhiyun .resources = mt6358_rtc_resources,
95*4882a593Smuzhiyun .of_compatible = "mediatek,mt6358-rtc",
96*4882a593Smuzhiyun }, {
97*4882a593Smuzhiyun .name = "mt6358-sound",
98*4882a593Smuzhiyun .of_compatible = "mediatek,mt6358-sound"
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static const struct mfd_cell mt6397_devs[] = {
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun .name = "mt6397-rtc",
105*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mt6397_rtc_resources),
106*4882a593Smuzhiyun .resources = mt6397_rtc_resources,
107*4882a593Smuzhiyun .of_compatible = "mediatek,mt6397-rtc",
108*4882a593Smuzhiyun }, {
109*4882a593Smuzhiyun .name = "mt6397-regulator",
110*4882a593Smuzhiyun .of_compatible = "mediatek,mt6397-regulator",
111*4882a593Smuzhiyun }, {
112*4882a593Smuzhiyun .name = "mt6397-codec",
113*4882a593Smuzhiyun .of_compatible = "mediatek,mt6397-codec",
114*4882a593Smuzhiyun }, {
115*4882a593Smuzhiyun .name = "mt6397-clk",
116*4882a593Smuzhiyun .of_compatible = "mediatek,mt6397-clk",
117*4882a593Smuzhiyun }, {
118*4882a593Smuzhiyun .name = "mt6397-pinctrl",
119*4882a593Smuzhiyun .of_compatible = "mediatek,mt6397-pinctrl",
120*4882a593Smuzhiyun }, {
121*4882a593Smuzhiyun .name = "mtk-pmic-keys",
122*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(mt6397_keys_resources),
123*4882a593Smuzhiyun .resources = mt6397_keys_resources,
124*4882a593Smuzhiyun .of_compatible = "mediatek,mt6397-keys"
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun struct chip_data {
129*4882a593Smuzhiyun u32 cid_addr;
130*4882a593Smuzhiyun u32 cid_shift;
131*4882a593Smuzhiyun const struct mfd_cell *cells;
132*4882a593Smuzhiyun int cell_size;
133*4882a593Smuzhiyun int (*irq_init)(struct mt6397_chip *chip);
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun static const struct chip_data mt6323_core = {
137*4882a593Smuzhiyun .cid_addr = MT6323_CID,
138*4882a593Smuzhiyun .cid_shift = 0,
139*4882a593Smuzhiyun .cells = mt6323_devs,
140*4882a593Smuzhiyun .cell_size = ARRAY_SIZE(mt6323_devs),
141*4882a593Smuzhiyun .irq_init = mt6397_irq_init,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static const struct chip_data mt6358_core = {
145*4882a593Smuzhiyun .cid_addr = MT6358_SWCID,
146*4882a593Smuzhiyun .cid_shift = 8,
147*4882a593Smuzhiyun .cells = mt6358_devs,
148*4882a593Smuzhiyun .cell_size = ARRAY_SIZE(mt6358_devs),
149*4882a593Smuzhiyun .irq_init = mt6358_irq_init,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const struct chip_data mt6397_core = {
153*4882a593Smuzhiyun .cid_addr = MT6397_CID,
154*4882a593Smuzhiyun .cid_shift = 0,
155*4882a593Smuzhiyun .cells = mt6397_devs,
156*4882a593Smuzhiyun .cell_size = ARRAY_SIZE(mt6397_devs),
157*4882a593Smuzhiyun .irq_init = mt6397_irq_init,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
mt6397_probe(struct platform_device * pdev)160*4882a593Smuzhiyun static int mt6397_probe(struct platform_device *pdev)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun int ret;
163*4882a593Smuzhiyun unsigned int id = 0;
164*4882a593Smuzhiyun struct mt6397_chip *pmic;
165*4882a593Smuzhiyun const struct chip_data *pmic_core;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
168*4882a593Smuzhiyun if (!pmic)
169*4882a593Smuzhiyun return -ENOMEM;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun pmic->dev = &pdev->dev;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun * mt6397 MFD is child device of soc pmic wrapper.
175*4882a593Smuzhiyun * Regmap is set from its parent.
176*4882a593Smuzhiyun */
177*4882a593Smuzhiyun pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
178*4882a593Smuzhiyun if (!pmic->regmap)
179*4882a593Smuzhiyun return -ENODEV;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun pmic_core = of_device_get_match_data(&pdev->dev);
182*4882a593Smuzhiyun if (!pmic_core)
183*4882a593Smuzhiyun return -ENODEV;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);
186*4882a593Smuzhiyun if (ret) {
187*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to read chip id: %d\n", ret);
188*4882a593Smuzhiyun return ret;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun pmic->chip_id = (id >> pmic_core->cid_shift) & 0xff;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun platform_set_drvdata(pdev, pmic);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun pmic->irq = platform_get_irq(pdev, 0);
196*4882a593Smuzhiyun if (pmic->irq <= 0)
197*4882a593Smuzhiyun return pmic->irq;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ret = pmic_core->irq_init(pmic);
200*4882a593Smuzhiyun if (ret)
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
204*4882a593Smuzhiyun pmic_core->cells, pmic_core->cell_size,
205*4882a593Smuzhiyun NULL, 0, pmic->irq_domain);
206*4882a593Smuzhiyun if (ret) {
207*4882a593Smuzhiyun irq_domain_remove(pmic->irq_domain);
208*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun return ret;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun static const struct of_device_id mt6397_of_match[] = {
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun .compatible = "mediatek,mt6323",
217*4882a593Smuzhiyun .data = &mt6323_core,
218*4882a593Smuzhiyun }, {
219*4882a593Smuzhiyun .compatible = "mediatek,mt6358",
220*4882a593Smuzhiyun .data = &mt6358_core,
221*4882a593Smuzhiyun }, {
222*4882a593Smuzhiyun .compatible = "mediatek,mt6397",
223*4882a593Smuzhiyun .data = &mt6397_core,
224*4882a593Smuzhiyun }, {
225*4882a593Smuzhiyun /* sentinel */
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mt6397_of_match);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun static const struct platform_device_id mt6397_id[] = {
231*4882a593Smuzhiyun { "mt6397", 0 },
232*4882a593Smuzhiyun { },
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, mt6397_id);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun static struct platform_driver mt6397_driver = {
237*4882a593Smuzhiyun .probe = mt6397_probe,
238*4882a593Smuzhiyun .driver = {
239*4882a593Smuzhiyun .name = "mt6397",
240*4882a593Smuzhiyun .of_match_table = of_match_ptr(mt6397_of_match),
241*4882a593Smuzhiyun },
242*4882a593Smuzhiyun .id_table = mt6397_id,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun module_platform_driver(mt6397_driver);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun MODULE_AUTHOR("Flora Fu, MediaTek");
248*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
249*4882a593Smuzhiyun MODULE_LICENSE("GPL");
250