1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Motorola CPCAP PMIC core driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Tony Lindgren <tony@atomide.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/mfd/core.h>
19*4882a593Smuzhiyun #include <linux/mfd/motorola-cpcap.h>
20*4882a593Smuzhiyun #include <linux/spi/spi.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define CPCAP_NR_IRQ_REG_BANKS 6
23*4882a593Smuzhiyun #define CPCAP_NR_IRQ_CHIPS 3
24*4882a593Smuzhiyun #define CPCAP_REGISTER_SIZE 4
25*4882a593Smuzhiyun #define CPCAP_REGISTER_BITS 16
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct cpcap_ddata {
28*4882a593Smuzhiyun struct spi_device *spi;
29*4882a593Smuzhiyun struct regmap_irq *irqs;
30*4882a593Smuzhiyun struct regmap_irq_chip_data *irqdata[CPCAP_NR_IRQ_CHIPS];
31*4882a593Smuzhiyun const struct regmap_config *regmap_conf;
32*4882a593Smuzhiyun struct regmap *regmap;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
cpcap_sense_irq(struct regmap * regmap,int irq)35*4882a593Smuzhiyun static int cpcap_sense_irq(struct regmap *regmap, int irq)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun int regnum = irq / CPCAP_REGISTER_BITS;
38*4882a593Smuzhiyun int mask = BIT(irq % CPCAP_REGISTER_BITS);
39*4882a593Smuzhiyun int reg = CPCAP_REG_INTS1 + (regnum * CPCAP_REGISTER_SIZE);
40*4882a593Smuzhiyun int err, val;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (reg < CPCAP_REG_INTS1 || reg > CPCAP_REG_INTS4)
43*4882a593Smuzhiyun return -EINVAL;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun err = regmap_read(regmap, reg, &val);
46*4882a593Smuzhiyun if (err)
47*4882a593Smuzhiyun return err;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return !!(val & mask);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
cpcap_sense_virq(struct regmap * regmap,int virq)52*4882a593Smuzhiyun int cpcap_sense_virq(struct regmap *regmap, int virq)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct regmap_irq_chip_data *d = irq_get_chip_data(virq);
55*4882a593Smuzhiyun int irq_base = regmap_irq_chip_get_base(d);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return cpcap_sense_irq(regmap, virq - irq_base);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cpcap_sense_virq);
60*4882a593Smuzhiyun
cpcap_check_revision(struct cpcap_ddata * cpcap)61*4882a593Smuzhiyun static int cpcap_check_revision(struct cpcap_ddata *cpcap)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun u16 vendor, rev;
64*4882a593Smuzhiyun int ret;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun ret = cpcap_get_vendor(&cpcap->spi->dev, cpcap->regmap, &vendor);
67*4882a593Smuzhiyun if (ret)
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ret = cpcap_get_revision(&cpcap->spi->dev, cpcap->regmap, &rev);
71*4882a593Smuzhiyun if (ret)
72*4882a593Smuzhiyun return ret;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun dev_info(&cpcap->spi->dev, "CPCAP vendor: %s rev: %i.%i (%x)\n",
75*4882a593Smuzhiyun vendor == CPCAP_VENDOR_ST ? "ST" : "TI",
76*4882a593Smuzhiyun CPCAP_REVISION_MAJOR(rev), CPCAP_REVISION_MINOR(rev),
77*4882a593Smuzhiyun rev);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (rev < CPCAP_REVISION_2_1) {
80*4882a593Smuzhiyun dev_info(&cpcap->spi->dev,
81*4882a593Smuzhiyun "Please add old CPCAP revision support as needed\n");
82*4882a593Smuzhiyun return -ENODEV;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * First two irq chips are the two private macro interrupt chips, the third
90*4882a593Smuzhiyun * irq chip is for register banks 1 - 4 and is available for drivers to use.
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun static struct regmap_irq_chip cpcap_irq_chip[CPCAP_NR_IRQ_CHIPS] = {
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun .name = "cpcap-m2",
95*4882a593Smuzhiyun .num_regs = 1,
96*4882a593Smuzhiyun .status_base = CPCAP_REG_MI1,
97*4882a593Smuzhiyun .ack_base = CPCAP_REG_MI1,
98*4882a593Smuzhiyun .mask_base = CPCAP_REG_MIM1,
99*4882a593Smuzhiyun .use_ack = true,
100*4882a593Smuzhiyun .clear_ack = true,
101*4882a593Smuzhiyun },
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun .name = "cpcap-m2",
104*4882a593Smuzhiyun .num_regs = 1,
105*4882a593Smuzhiyun .status_base = CPCAP_REG_MI2,
106*4882a593Smuzhiyun .ack_base = CPCAP_REG_MI2,
107*4882a593Smuzhiyun .mask_base = CPCAP_REG_MIM2,
108*4882a593Smuzhiyun .use_ack = true,
109*4882a593Smuzhiyun .clear_ack = true,
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun .name = "cpcap1-4",
113*4882a593Smuzhiyun .num_regs = 4,
114*4882a593Smuzhiyun .status_base = CPCAP_REG_INT1,
115*4882a593Smuzhiyun .ack_base = CPCAP_REG_INT1,
116*4882a593Smuzhiyun .mask_base = CPCAP_REG_INTM1,
117*4882a593Smuzhiyun .use_ack = true,
118*4882a593Smuzhiyun .clear_ack = true,
119*4882a593Smuzhiyun },
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
cpcap_init_one_regmap_irq(struct cpcap_ddata * cpcap,struct regmap_irq * rirq,int irq_base,int irq)122*4882a593Smuzhiyun static void cpcap_init_one_regmap_irq(struct cpcap_ddata *cpcap,
123*4882a593Smuzhiyun struct regmap_irq *rirq,
124*4882a593Smuzhiyun int irq_base, int irq)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun unsigned int reg_offset;
127*4882a593Smuzhiyun unsigned int bit, mask;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun reg_offset = irq - irq_base;
130*4882a593Smuzhiyun reg_offset /= cpcap->regmap_conf->val_bits;
131*4882a593Smuzhiyun reg_offset *= cpcap->regmap_conf->reg_stride;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun bit = irq % cpcap->regmap_conf->val_bits;
134*4882a593Smuzhiyun mask = (1 << bit);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun rirq->reg_offset = reg_offset;
137*4882a593Smuzhiyun rirq->mask = mask;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
cpcap_init_irq_chip(struct cpcap_ddata * cpcap,int irq_chip,int irq_start,int nr_irqs)140*4882a593Smuzhiyun static int cpcap_init_irq_chip(struct cpcap_ddata *cpcap, int irq_chip,
141*4882a593Smuzhiyun int irq_start, int nr_irqs)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct regmap_irq_chip *chip = &cpcap_irq_chip[irq_chip];
144*4882a593Smuzhiyun int i, ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun for (i = irq_start; i < irq_start + nr_irqs; i++) {
147*4882a593Smuzhiyun struct regmap_irq *rirq = &cpcap->irqs[i];
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun cpcap_init_one_regmap_irq(cpcap, rirq, irq_start, i);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun chip->irqs = &cpcap->irqs[irq_start];
152*4882a593Smuzhiyun chip->num_irqs = nr_irqs;
153*4882a593Smuzhiyun chip->irq_drv_data = cpcap;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun ret = devm_regmap_add_irq_chip(&cpcap->spi->dev, cpcap->regmap,
156*4882a593Smuzhiyun cpcap->spi->irq,
157*4882a593Smuzhiyun irq_get_trigger_type(cpcap->spi->irq) |
158*4882a593Smuzhiyun IRQF_SHARED, -1,
159*4882a593Smuzhiyun chip, &cpcap->irqdata[irq_chip]);
160*4882a593Smuzhiyun if (ret) {
161*4882a593Smuzhiyun dev_err(&cpcap->spi->dev, "could not add irq chip %i: %i\n",
162*4882a593Smuzhiyun irq_chip, ret);
163*4882a593Smuzhiyun return ret;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
cpcap_init_irq(struct cpcap_ddata * cpcap)169*4882a593Smuzhiyun static int cpcap_init_irq(struct cpcap_ddata *cpcap)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun int ret;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun cpcap->irqs = devm_kzalloc(&cpcap->spi->dev,
174*4882a593Smuzhiyun array3_size(sizeof(*cpcap->irqs),
175*4882a593Smuzhiyun CPCAP_NR_IRQ_REG_BANKS,
176*4882a593Smuzhiyun cpcap->regmap_conf->val_bits),
177*4882a593Smuzhiyun GFP_KERNEL);
178*4882a593Smuzhiyun if (!cpcap->irqs)
179*4882a593Smuzhiyun return -ENOMEM;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun ret = cpcap_init_irq_chip(cpcap, 0, 0, 16);
182*4882a593Smuzhiyun if (ret)
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ret = cpcap_init_irq_chip(cpcap, 1, 16, 16);
186*4882a593Smuzhiyun if (ret)
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun ret = cpcap_init_irq_chip(cpcap, 2, 32, 64);
190*4882a593Smuzhiyun if (ret)
191*4882a593Smuzhiyun return ret;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun enable_irq_wake(cpcap->spi->irq);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static const struct of_device_id cpcap_of_match[] = {
199*4882a593Smuzhiyun { .compatible = "motorola,cpcap", },
200*4882a593Smuzhiyun { .compatible = "st,6556002", },
201*4882a593Smuzhiyun {},
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, cpcap_of_match);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static const struct regmap_config cpcap_regmap_config = {
206*4882a593Smuzhiyun .reg_bits = 16,
207*4882a593Smuzhiyun .reg_stride = 4,
208*4882a593Smuzhiyun .pad_bits = 0,
209*4882a593Smuzhiyun .val_bits = 16,
210*4882a593Smuzhiyun .write_flag_mask = 0x8000,
211*4882a593Smuzhiyun .max_register = CPCAP_REG_ST_TEST2,
212*4882a593Smuzhiyun .cache_type = REGCACHE_NONE,
213*4882a593Smuzhiyun .reg_format_endian = REGMAP_ENDIAN_LITTLE,
214*4882a593Smuzhiyun .val_format_endian = REGMAP_ENDIAN_LITTLE,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
cpcap_suspend(struct device * dev)218*4882a593Smuzhiyun static int cpcap_suspend(struct device *dev)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct spi_device *spi = to_spi_device(dev);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun disable_irq(spi->irq);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
cpcap_resume(struct device * dev)227*4882a593Smuzhiyun static int cpcap_resume(struct device *dev)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct spi_device *spi = to_spi_device(dev);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun enable_irq(spi->irq);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun #endif
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(cpcap_pm, cpcap_suspend, cpcap_resume);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static const struct mfd_cell cpcap_mfd_devices[] = {
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun .name = "cpcap_adc",
242*4882a593Smuzhiyun .of_compatible = "motorola,mapphone-cpcap-adc",
243*4882a593Smuzhiyun }, {
244*4882a593Smuzhiyun .name = "cpcap_battery",
245*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-battery",
246*4882a593Smuzhiyun }, {
247*4882a593Smuzhiyun .name = "cpcap-charger",
248*4882a593Smuzhiyun .of_compatible = "motorola,mapphone-cpcap-charger",
249*4882a593Smuzhiyun }, {
250*4882a593Smuzhiyun .name = "cpcap-regulator",
251*4882a593Smuzhiyun .of_compatible = "motorola,mapphone-cpcap-regulator",
252*4882a593Smuzhiyun }, {
253*4882a593Smuzhiyun .name = "cpcap-rtc",
254*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-rtc",
255*4882a593Smuzhiyun }, {
256*4882a593Smuzhiyun .name = "cpcap-pwrbutton",
257*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-pwrbutton",
258*4882a593Smuzhiyun }, {
259*4882a593Smuzhiyun .name = "cpcap-usb-phy",
260*4882a593Smuzhiyun .of_compatible = "motorola,mapphone-cpcap-usb-phy",
261*4882a593Smuzhiyun }, {
262*4882a593Smuzhiyun .name = "cpcap-led",
263*4882a593Smuzhiyun .id = 0,
264*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-led-red",
265*4882a593Smuzhiyun }, {
266*4882a593Smuzhiyun .name = "cpcap-led",
267*4882a593Smuzhiyun .id = 1,
268*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-led-green",
269*4882a593Smuzhiyun }, {
270*4882a593Smuzhiyun .name = "cpcap-led",
271*4882a593Smuzhiyun .id = 2,
272*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-led-blue",
273*4882a593Smuzhiyun }, {
274*4882a593Smuzhiyun .name = "cpcap-led",
275*4882a593Smuzhiyun .id = 3,
276*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-led-adl",
277*4882a593Smuzhiyun }, {
278*4882a593Smuzhiyun .name = "cpcap-led",
279*4882a593Smuzhiyun .id = 4,
280*4882a593Smuzhiyun .of_compatible = "motorola,cpcap-led-cp",
281*4882a593Smuzhiyun }, {
282*4882a593Smuzhiyun .name = "cpcap-codec",
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun
cpcap_probe(struct spi_device * spi)286*4882a593Smuzhiyun static int cpcap_probe(struct spi_device *spi)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun const struct of_device_id *match;
289*4882a593Smuzhiyun struct cpcap_ddata *cpcap;
290*4882a593Smuzhiyun int ret;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun match = of_match_device(of_match_ptr(cpcap_of_match), &spi->dev);
293*4882a593Smuzhiyun if (!match)
294*4882a593Smuzhiyun return -ENODEV;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun cpcap = devm_kzalloc(&spi->dev, sizeof(*cpcap), GFP_KERNEL);
297*4882a593Smuzhiyun if (!cpcap)
298*4882a593Smuzhiyun return -ENOMEM;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun cpcap->spi = spi;
301*4882a593Smuzhiyun spi_set_drvdata(spi, cpcap);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun spi->bits_per_word = 16;
304*4882a593Smuzhiyun spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun ret = spi_setup(spi);
307*4882a593Smuzhiyun if (ret)
308*4882a593Smuzhiyun return ret;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun cpcap->regmap_conf = &cpcap_regmap_config;
311*4882a593Smuzhiyun cpcap->regmap = devm_regmap_init_spi(spi, &cpcap_regmap_config);
312*4882a593Smuzhiyun if (IS_ERR(cpcap->regmap)) {
313*4882a593Smuzhiyun ret = PTR_ERR(cpcap->regmap);
314*4882a593Smuzhiyun dev_err(&cpcap->spi->dev, "Failed to initialize regmap: %d\n",
315*4882a593Smuzhiyun ret);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun return ret;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun ret = cpcap_check_revision(cpcap);
321*4882a593Smuzhiyun if (ret) {
322*4882a593Smuzhiyun dev_err(&cpcap->spi->dev, "Failed to detect CPCAP: %i\n", ret);
323*4882a593Smuzhiyun return ret;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun ret = cpcap_init_irq(cpcap);
327*4882a593Smuzhiyun if (ret)
328*4882a593Smuzhiyun return ret;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* Parent SPI controller uses DMA, CPCAP and child devices do not */
331*4882a593Smuzhiyun spi->dev.coherent_dma_mask = 0;
332*4882a593Smuzhiyun spi->dev.dma_mask = &spi->dev.coherent_dma_mask;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return devm_mfd_add_devices(&spi->dev, 0, cpcap_mfd_devices,
335*4882a593Smuzhiyun ARRAY_SIZE(cpcap_mfd_devices), NULL, 0, NULL);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun static struct spi_driver cpcap_driver = {
339*4882a593Smuzhiyun .driver = {
340*4882a593Smuzhiyun .name = "cpcap-core",
341*4882a593Smuzhiyun .of_match_table = cpcap_of_match,
342*4882a593Smuzhiyun .pm = &cpcap_pm,
343*4882a593Smuzhiyun },
344*4882a593Smuzhiyun .probe = cpcap_probe,
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun module_spi_driver(cpcap_driver);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun MODULE_ALIAS("platform:cpcap");
349*4882a593Smuzhiyun MODULE_DESCRIPTION("CPCAP driver");
350*4882a593Smuzhiyun MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
351*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
352