1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/drivers/mfd/mcp-sa11x0.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2001-2005 Russell King
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SA11x0 MCP (Multimedia Communications Port) driver.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/spinlock.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun #include <linux/mfd/mcp.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <mach/hardware.h>
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun #include <linux/platform_data/mfd-mcp-sa11x0.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define DRIVER_NAME "sa11x0-mcp"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct mcp_sa11x0 {
28*4882a593Smuzhiyun void __iomem *base0;
29*4882a593Smuzhiyun void __iomem *base1;
30*4882a593Smuzhiyun u32 mccr0;
31*4882a593Smuzhiyun u32 mccr1;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Register offsets */
35*4882a593Smuzhiyun #define MCCR0(m) ((m)->base0 + 0x00)
36*4882a593Smuzhiyun #define MCDR0(m) ((m)->base0 + 0x08)
37*4882a593Smuzhiyun #define MCDR1(m) ((m)->base0 + 0x0c)
38*4882a593Smuzhiyun #define MCDR2(m) ((m)->base0 + 0x10)
39*4882a593Smuzhiyun #define MCSR(m) ((m)->base0 + 0x18)
40*4882a593Smuzhiyun #define MCCR1(m) ((m)->base1 + 0x00)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static void
mcp_sa11x0_set_telecom_divisor(struct mcp * mcp,unsigned int divisor)45*4882a593Smuzhiyun mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun divisor /= 32;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun m->mccr0 &= ~0x00007f00;
52*4882a593Smuzhiyun m->mccr0 |= divisor << 8;
53*4882a593Smuzhiyun writel_relaxed(m->mccr0, MCCR0(m));
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static void
mcp_sa11x0_set_audio_divisor(struct mcp * mcp,unsigned int divisor)57*4882a593Smuzhiyun mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun divisor /= 32;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun m->mccr0 &= ~0x0000007f;
64*4882a593Smuzhiyun m->mccr0 |= divisor;
65*4882a593Smuzhiyun writel_relaxed(m->mccr0, MCCR0(m));
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * Write data to the device. The bit should be set after 3 subframe
70*4882a593Smuzhiyun * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
71*4882a593Smuzhiyun * We really should try doing something more productive while we
72*4882a593Smuzhiyun * wait.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun static void
mcp_sa11x0_write(struct mcp * mcp,unsigned int reg,unsigned int val)75*4882a593Smuzhiyun mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
78*4882a593Smuzhiyun int ret = -ETIME;
79*4882a593Smuzhiyun int i;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m));
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
84*4882a593Smuzhiyun udelay(mcp->rw_timeout);
85*4882a593Smuzhiyun if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
86*4882a593Smuzhiyun ret = 0;
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (ret < 0)
92*4882a593Smuzhiyun printk(KERN_WARNING "mcp: write timed out\n");
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * Read data from the device. The bit should be set after 3 subframe
97*4882a593Smuzhiyun * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
98*4882a593Smuzhiyun * We really should try doing something more productive while we
99*4882a593Smuzhiyun * wait.
100*4882a593Smuzhiyun */
101*4882a593Smuzhiyun static unsigned int
mcp_sa11x0_read(struct mcp * mcp,unsigned int reg)102*4882a593Smuzhiyun mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
105*4882a593Smuzhiyun int ret = -ETIME;
106*4882a593Smuzhiyun int i;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
111*4882a593Smuzhiyun udelay(mcp->rw_timeout);
112*4882a593Smuzhiyun if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
113*4882a593Smuzhiyun ret = readl_relaxed(MCDR2(m)) & 0xffff;
114*4882a593Smuzhiyun break;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (ret < 0)
119*4882a593Smuzhiyun printk(KERN_WARNING "mcp: read timed out\n");
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return ret;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
mcp_sa11x0_enable(struct mcp * mcp)124*4882a593Smuzhiyun static void mcp_sa11x0_enable(struct mcp *mcp)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun writel(-1, MCSR(m));
129*4882a593Smuzhiyun m->mccr0 |= MCCR0_MCE;
130*4882a593Smuzhiyun writel_relaxed(m->mccr0, MCCR0(m));
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
mcp_sa11x0_disable(struct mcp * mcp)133*4882a593Smuzhiyun static void mcp_sa11x0_disable(struct mcp *mcp)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun m->mccr0 &= ~MCCR0_MCE;
138*4882a593Smuzhiyun writel_relaxed(m->mccr0, MCCR0(m));
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /*
142*4882a593Smuzhiyun * Our methods.
143*4882a593Smuzhiyun */
144*4882a593Smuzhiyun static struct mcp_ops mcp_sa11x0 = {
145*4882a593Smuzhiyun .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
146*4882a593Smuzhiyun .set_audio_divisor = mcp_sa11x0_set_audio_divisor,
147*4882a593Smuzhiyun .reg_write = mcp_sa11x0_write,
148*4882a593Smuzhiyun .reg_read = mcp_sa11x0_read,
149*4882a593Smuzhiyun .enable = mcp_sa11x0_enable,
150*4882a593Smuzhiyun .disable = mcp_sa11x0_disable,
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
mcp_sa11x0_probe(struct platform_device * dev)153*4882a593Smuzhiyun static int mcp_sa11x0_probe(struct platform_device *dev)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct mcp_plat_data *data = dev_get_platdata(&dev->dev);
156*4882a593Smuzhiyun struct resource *mem0, *mem1;
157*4882a593Smuzhiyun struct mcp_sa11x0 *m;
158*4882a593Smuzhiyun struct mcp *mcp;
159*4882a593Smuzhiyun int ret;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (!data)
162*4882a593Smuzhiyun return -ENODEV;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
165*4882a593Smuzhiyun mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
166*4882a593Smuzhiyun if (!mem0 || !mem1)
167*4882a593Smuzhiyun return -ENXIO;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (!request_mem_region(mem0->start, resource_size(mem0),
170*4882a593Smuzhiyun DRIVER_NAME)) {
171*4882a593Smuzhiyun ret = -EBUSY;
172*4882a593Smuzhiyun goto err_mem0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (!request_mem_region(mem1->start, resource_size(mem1),
176*4882a593Smuzhiyun DRIVER_NAME)) {
177*4882a593Smuzhiyun ret = -EBUSY;
178*4882a593Smuzhiyun goto err_mem1;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0));
182*4882a593Smuzhiyun if (!mcp) {
183*4882a593Smuzhiyun ret = -ENOMEM;
184*4882a593Smuzhiyun goto err_alloc;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun mcp->owner = THIS_MODULE;
188*4882a593Smuzhiyun mcp->ops = &mcp_sa11x0;
189*4882a593Smuzhiyun mcp->sclk_rate = data->sclk_rate;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun m = priv(mcp);
192*4882a593Smuzhiyun m->mccr0 = data->mccr0 | 0x7f7f;
193*4882a593Smuzhiyun m->mccr1 = data->mccr1;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun m->base0 = ioremap(mem0->start, resource_size(mem0));
196*4882a593Smuzhiyun m->base1 = ioremap(mem1->start, resource_size(mem1));
197*4882a593Smuzhiyun if (!m->base0 || !m->base1) {
198*4882a593Smuzhiyun ret = -ENOMEM;
199*4882a593Smuzhiyun goto err_ioremap;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun platform_set_drvdata(dev, mcp);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /*
205*4882a593Smuzhiyun * Initialise device. Note that we initially
206*4882a593Smuzhiyun * set the sampling rate to minimum.
207*4882a593Smuzhiyun */
208*4882a593Smuzhiyun writel_relaxed(-1, MCSR(m));
209*4882a593Smuzhiyun writel_relaxed(m->mccr1, MCCR1(m));
210*4882a593Smuzhiyun writel_relaxed(m->mccr0, MCCR0(m));
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /*
213*4882a593Smuzhiyun * Calculate the read/write timeout (us) from the bit clock
214*4882a593Smuzhiyun * rate. This is the period for 3 64-bit frames. Always
215*4882a593Smuzhiyun * round this time up.
216*4882a593Smuzhiyun */
217*4882a593Smuzhiyun mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
218*4882a593Smuzhiyun mcp->sclk_rate;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ret = mcp_host_add(mcp, data->codec_pdata);
221*4882a593Smuzhiyun if (ret == 0)
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun err_ioremap:
225*4882a593Smuzhiyun iounmap(m->base1);
226*4882a593Smuzhiyun iounmap(m->base0);
227*4882a593Smuzhiyun mcp_host_free(mcp);
228*4882a593Smuzhiyun err_alloc:
229*4882a593Smuzhiyun release_mem_region(mem1->start, resource_size(mem1));
230*4882a593Smuzhiyun err_mem1:
231*4882a593Smuzhiyun release_mem_region(mem0->start, resource_size(mem0));
232*4882a593Smuzhiyun err_mem0:
233*4882a593Smuzhiyun return ret;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
mcp_sa11x0_remove(struct platform_device * dev)236*4882a593Smuzhiyun static int mcp_sa11x0_remove(struct platform_device *dev)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun struct mcp *mcp = platform_get_drvdata(dev);
239*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(mcp);
240*4882a593Smuzhiyun struct resource *mem0, *mem1;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun if (m->mccr0 & MCCR0_MCE)
243*4882a593Smuzhiyun dev_warn(&dev->dev,
244*4882a593Smuzhiyun "device left active (missing disable call?)\n");
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
247*4882a593Smuzhiyun mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun mcp_host_del(mcp);
250*4882a593Smuzhiyun iounmap(m->base1);
251*4882a593Smuzhiyun iounmap(m->base0);
252*4882a593Smuzhiyun mcp_host_free(mcp);
253*4882a593Smuzhiyun release_mem_region(mem1->start, resource_size(mem1));
254*4882a593Smuzhiyun release_mem_region(mem0->start, resource_size(mem0));
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun return 0;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
mcp_sa11x0_suspend(struct device * dev)260*4882a593Smuzhiyun static int mcp_sa11x0_suspend(struct device *dev)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (m->mccr0 & MCCR0_MCE)
265*4882a593Smuzhiyun dev_warn(dev, "device left active (missing disable call?)\n");
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun return 0;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
mcp_sa11x0_resume(struct device * dev)272*4882a593Smuzhiyun static int mcp_sa11x0_resume(struct device *dev)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun writel_relaxed(m->mccr1, MCCR1(m));
277*4882a593Smuzhiyun writel_relaxed(m->mccr0, MCCR0(m));
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun #endif
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
284*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
285*4882a593Smuzhiyun .suspend = mcp_sa11x0_suspend,
286*4882a593Smuzhiyun .freeze = mcp_sa11x0_suspend,
287*4882a593Smuzhiyun .poweroff = mcp_sa11x0_suspend,
288*4882a593Smuzhiyun .resume_noirq = mcp_sa11x0_resume,
289*4882a593Smuzhiyun .thaw_noirq = mcp_sa11x0_resume,
290*4882a593Smuzhiyun .restore_noirq = mcp_sa11x0_resume,
291*4882a593Smuzhiyun #endif
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun static struct platform_driver mcp_sa11x0_driver = {
295*4882a593Smuzhiyun .probe = mcp_sa11x0_probe,
296*4882a593Smuzhiyun .remove = mcp_sa11x0_remove,
297*4882a593Smuzhiyun .driver = {
298*4882a593Smuzhiyun .name = DRIVER_NAME,
299*4882a593Smuzhiyun .pm = &mcp_sa11x0_pm_ops,
300*4882a593Smuzhiyun },
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /*
304*4882a593Smuzhiyun * This needs re-working
305*4882a593Smuzhiyun */
306*4882a593Smuzhiyun module_platform_driver(mcp_sa11x0_driver);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun MODULE_ALIAS("platform:" DRIVER_NAME);
309*4882a593Smuzhiyun MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
310*4882a593Smuzhiyun MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
311*4882a593Smuzhiyun MODULE_LICENSE("GPL");
312