xref: /OK3568_Linux_fs/kernel/drivers/mfd/max96755f.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Maxim max96755f MFD driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/i2c-mux.h>
12*4882a593Smuzhiyun #include <linux/extcon-provider.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/mfd/core.h>
16*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
17*4882a593Smuzhiyun #include <linux/mfd/max96755f.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun static const struct mfd_cell max96755f_devs[] = {
20*4882a593Smuzhiyun 	{
21*4882a593Smuzhiyun 		.name = "max96755f-pinctrl",
22*4882a593Smuzhiyun 		.of_compatible = "maxim,max96755f-pinctrl",
23*4882a593Smuzhiyun 	}, {
24*4882a593Smuzhiyun 		.name = "max96755f-bridge",
25*4882a593Smuzhiyun 		.of_compatible = "maxim,max96755f-bridge",
26*4882a593Smuzhiyun 	},
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static const unsigned int max96755f_cable[] = {
30*4882a593Smuzhiyun 	EXTCON_JACK_VIDEO_OUT,
31*4882a593Smuzhiyun 	EXTCON_NONE,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
max96755f_vid_sync_detected(struct max96755f * max96755f)34*4882a593Smuzhiyun static bool max96755f_vid_sync_detected(struct max96755f *max96755f)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	u32 det;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	if (regmap_read(max96755f->regmap, 0x55d, &det))
39*4882a593Smuzhiyun 		return false;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	if ((!(det & VS_DET)) || (!(det & HS_DET)))
42*4882a593Smuzhiyun 		return false;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	return true;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun 
max96755f_volatile_reg(struct device * dev,unsigned int reg)47*4882a593Smuzhiyun static bool max96755f_volatile_reg(struct device *dev, unsigned int reg)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	switch (reg) {
50*4882a593Smuzhiyun 	case 0x0002:
51*4882a593Smuzhiyun 	case 0x0053:
52*4882a593Smuzhiyun 	case 0x0057:
53*4882a593Smuzhiyun 	case 0x02be ... 0x02fc:
54*4882a593Smuzhiyun 	case 0x0311:
55*4882a593Smuzhiyun 	case 0x032a:
56*4882a593Smuzhiyun 	case 0x0330 ... 0x0331:
57*4882a593Smuzhiyun 	case 0x0385 ... 0x0387:
58*4882a593Smuzhiyun 	case 0x03a4 ... 0x03ae:
59*4882a593Smuzhiyun 		return false;
60*4882a593Smuzhiyun 	default:
61*4882a593Smuzhiyun 		return true;
62*4882a593Smuzhiyun 	}
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static const struct regmap_config max96755f_regmap_config = {
66*4882a593Smuzhiyun 	.name = "max96755f",
67*4882a593Smuzhiyun 	.reg_bits = 16,
68*4882a593Smuzhiyun 	.val_bits = 8,
69*4882a593Smuzhiyun 	.max_register = 0x1b17,
70*4882a593Smuzhiyun 	.volatile_reg = max96755f_volatile_reg,
71*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
max96755f_select(struct i2c_mux_core * muxc,u32 chan)74*4882a593Smuzhiyun static int max96755f_select(struct i2c_mux_core *muxc, u32 chan)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct max96755f *max96755f = dev_get_drvdata(muxc->dev);
77*4882a593Smuzhiyun 	u32 link_cfg, val;
78*4882a593Smuzhiyun 	int ret;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	regmap_update_bits(max96755f->regmap, 0x0001, DIS_REM_CC,
81*4882a593Smuzhiyun 			   FIELD_PREP(DIS_REM_CC, 0));
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	if (!max96755f->split_mode)
84*4882a593Smuzhiyun 		return 0;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	regmap_read(max96755f->regmap, 0x0010, &link_cfg);
87*4882a593Smuzhiyun 	if ((link_cfg & LINK_CFG) == SPLITTER_MODE)
88*4882a593Smuzhiyun 		return 0;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	if (chan == 0 && (link_cfg & LINK_CFG) != LINKA) {
91*4882a593Smuzhiyun 		regmap_update_bits(max96755f->regmap, 0x0010,
92*4882a593Smuzhiyun 				   RESET_ONESHOT | AUTO_LINK | LINK_CFG,
93*4882a593Smuzhiyun 				   FIELD_PREP(RESET_ONESHOT, 1) |
94*4882a593Smuzhiyun 				   FIELD_PREP(AUTO_LINK, 0) |
95*4882a593Smuzhiyun 				   FIELD_PREP(LINK_CFG, LINKA));
96*4882a593Smuzhiyun 	} else if (chan == 1 && (link_cfg & LINK_CFG) != LINKB) {
97*4882a593Smuzhiyun 		regmap_update_bits(max96755f->regmap, 0x0010,
98*4882a593Smuzhiyun 				   RESET_ONESHOT | AUTO_LINK | LINK_CFG,
99*4882a593Smuzhiyun 				   FIELD_PREP(RESET_ONESHOT, 1) |
100*4882a593Smuzhiyun 				   FIELD_PREP(AUTO_LINK, 0) |
101*4882a593Smuzhiyun 				   FIELD_PREP(LINK_CFG, LINKB));
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = regmap_read_poll_timeout(max96755f->regmap, 0x0013, val,
105*4882a593Smuzhiyun 				       val & LOCKED, 100,
106*4882a593Smuzhiyun 				       50 * USEC_PER_MSEC);
107*4882a593Smuzhiyun 	if (ret < 0) {
108*4882a593Smuzhiyun 		dev_err(max96755f->dev, "GMSL2 link lock timeout\n");
109*4882a593Smuzhiyun 		return ret;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
max96755f_deselect(struct i2c_mux_core * muxc,u32 chan)115*4882a593Smuzhiyun static int max96755f_deselect(struct i2c_mux_core *muxc, u32 chan)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	struct max96755f *max96755f = dev_get_drvdata(muxc->dev);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	regmap_update_bits(max96755f->regmap, 0x0001, DIS_REM_CC,
120*4882a593Smuzhiyun 			   FIELD_PREP(DIS_REM_CC, 1));
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
max96755f_power_off(void * data)125*4882a593Smuzhiyun static void max96755f_power_off(void *data)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	struct max96755f *max96755f = data;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (max96755f->reset_gpio)
130*4882a593Smuzhiyun 		gpiod_direction_output(max96755f->reset_gpio, 1);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	if (max96755f->enable_gpio)
133*4882a593Smuzhiyun 		gpiod_direction_output(max96755f->enable_gpio, 0);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (max96755f->supply)
136*4882a593Smuzhiyun 		regulator_disable(max96755f->supply);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
max96755f_power_on(struct max96755f * max96755f)139*4882a593Smuzhiyun static int max96755f_power_on(struct max96755f *max96755f)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	int ret;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	if (max96755f_vid_sync_detected(max96755f)) {
144*4882a593Smuzhiyun 		extcon_set_state(max96755f->extcon, EXTCON_JACK_VIDEO_OUT, true);
145*4882a593Smuzhiyun 		return 0;
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	if (max96755f->supply) {
149*4882a593Smuzhiyun 		ret = regulator_enable(max96755f->supply);
150*4882a593Smuzhiyun 		if (ret < 0)
151*4882a593Smuzhiyun 			return ret;
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	if (max96755f->enable_gpio) {
155*4882a593Smuzhiyun 		gpiod_direction_output(max96755f->enable_gpio, 1);
156*4882a593Smuzhiyun 		msleep(100);
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	if (max96755f->reset_gpio) {
160*4882a593Smuzhiyun 		gpiod_direction_output(max96755f->reset_gpio, 0);
161*4882a593Smuzhiyun 		msleep(100);
162*4882a593Smuzhiyun 		gpiod_direction_output(max96755f->reset_gpio, 1);
163*4882a593Smuzhiyun 		msleep(100);
164*4882a593Smuzhiyun 		gpiod_direction_output(max96755f->reset_gpio, 0);
165*4882a593Smuzhiyun 		msleep(100);
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	regmap_update_bits(max96755f->regmap, 0x0001, DIS_REM_CC,
169*4882a593Smuzhiyun 			   FIELD_PREP(DIS_REM_CC, 1));
170*4882a593Smuzhiyun 	return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
line_fault_monitor_show(struct device * device,struct device_attribute * attr,char * buf)173*4882a593Smuzhiyun static ssize_t line_fault_monitor_show(struct device *device,
174*4882a593Smuzhiyun 				       struct device_attribute *attr,
175*4882a593Smuzhiyun 				       char *buf)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	struct max96755f *max96755f = dev_get_drvdata(device);
178*4882a593Smuzhiyun 	u32 pu_lf, lf, status;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	regmap_read(max96755f->regmap, 0x0005, &pu_lf);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	/*
183*4882a593Smuzhiyun 	 * Line-fault status of wire connected to LMN0/1 pin
184*4882a593Smuzhiyun 	 *
185*4882a593Smuzhiyun 	 * 0b000: Short to battery
186*4882a593Smuzhiyun 	 * 0b001: Short to GND
187*4882a593Smuzhiyun 	 * 0b010: Normal operation
188*4882a593Smuzhiyun 	 * 0b011: Line open
189*4882a593Smuzhiyun 	 * 0b1XX: Line-to-line short
190*4882a593Smuzhiyun 	 */
191*4882a593Smuzhiyun 	regmap_read(max96755f->regmap, 0x0026, &lf);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	if (FIELD_GET(PU_LF0, pu_lf)) {
194*4882a593Smuzhiyun 		status = (lf & LF_0);
195*4882a593Smuzhiyun 		return sprintf(buf, "%d\n", status);
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	if (FIELD_GET(PU_LF1, pu_lf)) {
199*4882a593Smuzhiyun 		status = (lf & LF_1) >> 4;
200*4882a593Smuzhiyun 		return sprintf(buf, "%d\n", status);
201*4882a593Smuzhiyun 	}
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", -EINVAL);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun static DEVICE_ATTR_RO(line_fault_monitor);
207*4882a593Smuzhiyun 
patgen_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)208*4882a593Smuzhiyun static ssize_t patgen_mode_store(struct device *dev,
209*4882a593Smuzhiyun 				 struct device_attribute *attr,
210*4882a593Smuzhiyun 				 const char *buf, size_t count)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	struct max96755f *max96755f = dev_get_drvdata(dev);
213*4882a593Smuzhiyun 	u8 patgen_mode;
214*4882a593Smuzhiyun 	int ret;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	ret = kstrtou8(buf, 0, &patgen_mode);
217*4882a593Smuzhiyun 	if (ret)
218*4882a593Smuzhiyun 		return ret;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	regmap_update_bits(max96755f->regmap, 0x01e5, PATGEN_MODE,
221*4882a593Smuzhiyun 			   FIELD_PREP(PATGEN_MODE, patgen_mode));
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	return count;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun static DEVICE_ATTR_WO(patgen_mode);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static struct attribute *max96755f_attrs[] = {
228*4882a593Smuzhiyun 	&dev_attr_line_fault_monitor.attr,
229*4882a593Smuzhiyun 	&dev_attr_patgen_mode.attr,
230*4882a593Smuzhiyun 	NULL
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static const struct attribute_group max96755f_attr_group = {
234*4882a593Smuzhiyun 	.attrs = max96755f_attrs,
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun 
max96755f_sysfs_add(struct max96755f * max96755f)237*4882a593Smuzhiyun static int max96755f_sysfs_add(struct max96755f *max96755f)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	struct device *dev = max96755f->dev;
240*4882a593Smuzhiyun 	int ret;
241*4882a593Smuzhiyun 	u32 ch;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	ret = of_property_read_u32(dev->of_node, "line-fault-monitor", &ch);
244*4882a593Smuzhiyun 	if (!ret)
245*4882a593Smuzhiyun 		regmap_update_bits(max96755f->regmap, 0x0005,
246*4882a593Smuzhiyun 				   PU_LF0 << ch, PU_LF0 << ch);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	ret = devm_device_add_group(dev, &max96755f_attr_group);
249*4882a593Smuzhiyun 	if (ret) {
250*4882a593Smuzhiyun 		dev_err(dev, "failed to register sysfs. err: %d\n", ret);
251*4882a593Smuzhiyun 		return ret;
252*4882a593Smuzhiyun 	};
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
max96755f_i2c_probe(struct i2c_client * client)257*4882a593Smuzhiyun static int max96755f_i2c_probe(struct i2c_client *client)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	struct device *dev = &client->dev;
260*4882a593Smuzhiyun 	struct device_node *child;
261*4882a593Smuzhiyun 	struct max96755f *max96755f;
262*4882a593Smuzhiyun 	unsigned int nr = 0;
263*4882a593Smuzhiyun 	bool idle_disc;
264*4882a593Smuzhiyun 	int ret;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	for_each_available_child_of_node(dev->of_node, child) {
267*4882a593Smuzhiyun 		if (!of_find_property(child, "reg", NULL))
268*4882a593Smuzhiyun 			continue;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 		nr++;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	max96755f = devm_kzalloc(dev, sizeof(*max96755f), GFP_KERNEL);
274*4882a593Smuzhiyun 	if (!max96755f)
275*4882a593Smuzhiyun 		return -ENOMEM;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	idle_disc = device_property_read_bool(dev, "i2c-mux-idle-disconnect");
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	max96755f->muxc = i2c_mux_alloc(client->adapter, dev, nr, 0,
280*4882a593Smuzhiyun 					I2C_MUX_LOCKED, max96755f_select,
281*4882a593Smuzhiyun 					idle_disc ? max96755f_deselect : NULL);
282*4882a593Smuzhiyun 	if (!max96755f->muxc)
283*4882a593Smuzhiyun 		return -ENOMEM;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	if (nr == 2)
286*4882a593Smuzhiyun 		max96755f->split_mode = true;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	max96755f->dev = dev;
289*4882a593Smuzhiyun 	i2c_set_clientdata(client, max96755f);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	max96755f->supply = devm_regulator_get(dev, "power");
292*4882a593Smuzhiyun 	if (IS_ERR(max96755f->supply))
293*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(max96755f->supply),
294*4882a593Smuzhiyun 				     "failed to get power supply\n");
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	max96755f->lock_gpio = devm_gpiod_get_optional(dev, "lock", GPIOD_IN);
297*4882a593Smuzhiyun 	if (IS_ERR(max96755f->lock_gpio))
298*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(max96755f->lock_gpio),
299*4882a593Smuzhiyun 				     "failed to get lock GPIO\n");
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	max96755f->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
302*4882a593Smuzhiyun 	if (IS_ERR(max96755f->enable_gpio)) {
303*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(max96755f->enable_gpio),
304*4882a593Smuzhiyun 				     "failed to get enable GPIO\n");
305*4882a593Smuzhiyun 	}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	max96755f->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
308*4882a593Smuzhiyun 	if (IS_ERR(max96755f->reset_gpio))
309*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(max96755f->reset_gpio),
310*4882a593Smuzhiyun 				     "failed to get reset GPIO\n");
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	max96755f->regmap = devm_regmap_init_i2c(client, &max96755f_regmap_config);
313*4882a593Smuzhiyun 	if (IS_ERR(max96755f->regmap))
314*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(max96755f->regmap),
315*4882a593Smuzhiyun 				     "failed to initialize regmap");
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	max96755f->extcon = devm_extcon_dev_allocate(dev, max96755f_cable);
318*4882a593Smuzhiyun 	if (IS_ERR(max96755f->extcon))
319*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(max96755f->extcon),
320*4882a593Smuzhiyun 				     "failed to allocate extcon device\n");
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	ret = devm_extcon_dev_register(dev, max96755f->extcon);
323*4882a593Smuzhiyun 	if (ret)
324*4882a593Smuzhiyun 		return dev_err_probe(dev, ret,
325*4882a593Smuzhiyun 				     "failed to register extcon device\n");
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	ret = max96755f_power_on(max96755f);
328*4882a593Smuzhiyun 	if (ret)
329*4882a593Smuzhiyun 		return ret;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	ret = devm_add_action_or_reset(dev, max96755f_power_off, max96755f);
332*4882a593Smuzhiyun 	if (ret)
333*4882a593Smuzhiyun 		return ret;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, max96755f_devs,
336*4882a593Smuzhiyun 				   ARRAY_SIZE(max96755f_devs), NULL, 0, NULL);
337*4882a593Smuzhiyun 	if (ret)
338*4882a593Smuzhiyun 		return ret;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	for_each_available_child_of_node(dev->of_node, child) {
341*4882a593Smuzhiyun 		if (of_property_read_u32(child, "reg", &nr))
342*4882a593Smuzhiyun 			continue;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 		ret = i2c_mux_add_adapter(max96755f->muxc, 0, nr, 0);
345*4882a593Smuzhiyun 		if (ret) {
346*4882a593Smuzhiyun 			i2c_mux_del_adapters(max96755f->muxc);
347*4882a593Smuzhiyun 			return ret;
348*4882a593Smuzhiyun 		}
349*4882a593Smuzhiyun 	}
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	ret = max96755f_sysfs_add(max96755f);
352*4882a593Smuzhiyun 	if (ret)
353*4882a593Smuzhiyun 		return dev_err_probe(dev, ret, "failed to registers sysfs\n");
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun 
max96755f_i2c_remove(struct i2c_client * client)358*4882a593Smuzhiyun static int max96755f_i2c_remove(struct i2c_client *client)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun 	struct max96755f *max96755f = i2c_get_clientdata(client);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	i2c_mux_del_adapters(max96755f->muxc);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	return 0;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun 
max96755f_i2c_shutdown(struct i2c_client * client)367*4882a593Smuzhiyun static void max96755f_i2c_shutdown(struct i2c_client *client)
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun 	struct max96755f *max96755f = i2c_get_clientdata(client);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	max96755f_power_off(max96755f);
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun 
max96755f_suspend(struct device * dev)374*4882a593Smuzhiyun static int __maybe_unused max96755f_suspend(struct device *dev)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun 	struct max96755f *max96755f = dev_get_drvdata(dev);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	regcache_mark_dirty(max96755f->regmap);
379*4882a593Smuzhiyun 	regcache_cache_only(max96755f->regmap, true);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	return 0;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
max96755f_resume(struct device * dev)384*4882a593Smuzhiyun static int __maybe_unused max96755f_resume(struct device *dev)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	struct max96755f *max96755f = dev_get_drvdata(dev);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	regcache_cache_only(max96755f->regmap, false);
389*4882a593Smuzhiyun 	regcache_sync(max96755f->regmap);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	return 0;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(max96755f_pm_ops, max96755f_suspend, max96755f_resume);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun static const struct of_device_id max96755f_of_match[] = {
397*4882a593Smuzhiyun 	{ .compatible = "maxim,max96755f", },
398*4882a593Smuzhiyun 	{}
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max96755f_of_match);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun static struct i2c_driver max96755f_i2c_driver = {
403*4882a593Smuzhiyun 	.driver = {
404*4882a593Smuzhiyun 		.name = "max96755f",
405*4882a593Smuzhiyun 		.of_match_table = max96755f_of_match,
406*4882a593Smuzhiyun 		.pm = &max96755f_pm_ops,
407*4882a593Smuzhiyun 	},
408*4882a593Smuzhiyun 	.probe_new = max96755f_i2c_probe,
409*4882a593Smuzhiyun 	.remove = max96755f_i2c_remove,
410*4882a593Smuzhiyun 	.shutdown = max96755f_i2c_shutdown,
411*4882a593Smuzhiyun };
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun module_i2c_driver(max96755f_i2c_driver);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun MODULE_AUTHOR("Guochun Huang<hero.huang@rock-chips.com>");
416*4882a593Smuzhiyun MODULE_DESCRIPTION("Maxim max96755f MFD driver");
417*4882a593Smuzhiyun MODULE_LICENSE("GPL");
418