xref: /OK3568_Linux_fs/kernel/drivers/mfd/max8998-irq.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Interrupt controller support for MAX8998
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2010 Samsung Electronics Co.Ltd
6*4882a593Smuzhiyun // Author: Joonyoung Shim <jy0922.shim@samsung.com>
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/irq.h>
11*4882a593Smuzhiyun #include <linux/irqdomain.h>
12*4882a593Smuzhiyun #include <linux/mfd/max8998-private.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun struct max8998_irq_data {
15*4882a593Smuzhiyun 	int reg;
16*4882a593Smuzhiyun 	int mask;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun static struct max8998_irq_data max8998_irqs[] = {
20*4882a593Smuzhiyun 	[MAX8998_IRQ_DCINF] = {
21*4882a593Smuzhiyun 		.reg = 1,
22*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_DCINF_MASK,
23*4882a593Smuzhiyun 	},
24*4882a593Smuzhiyun 	[MAX8998_IRQ_DCINR] = {
25*4882a593Smuzhiyun 		.reg = 1,
26*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_DCINR_MASK,
27*4882a593Smuzhiyun 	},
28*4882a593Smuzhiyun 	[MAX8998_IRQ_JIGF] = {
29*4882a593Smuzhiyun 		.reg = 1,
30*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_JIGF_MASK,
31*4882a593Smuzhiyun 	},
32*4882a593Smuzhiyun 	[MAX8998_IRQ_JIGR] = {
33*4882a593Smuzhiyun 		.reg = 1,
34*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_JIGR_MASK,
35*4882a593Smuzhiyun 	},
36*4882a593Smuzhiyun 	[MAX8998_IRQ_PWRONF] = {
37*4882a593Smuzhiyun 		.reg = 1,
38*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_PWRONF_MASK,
39*4882a593Smuzhiyun 	},
40*4882a593Smuzhiyun 	[MAX8998_IRQ_PWRONR] = {
41*4882a593Smuzhiyun 		.reg = 1,
42*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_PWRONR_MASK,
43*4882a593Smuzhiyun 	},
44*4882a593Smuzhiyun 	[MAX8998_IRQ_WTSREVNT] = {
45*4882a593Smuzhiyun 		.reg = 2,
46*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_WTSREVNT_MASK,
47*4882a593Smuzhiyun 	},
48*4882a593Smuzhiyun 	[MAX8998_IRQ_SMPLEVNT] = {
49*4882a593Smuzhiyun 		.reg = 2,
50*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_SMPLEVNT_MASK,
51*4882a593Smuzhiyun 	},
52*4882a593Smuzhiyun 	[MAX8998_IRQ_ALARM1] = {
53*4882a593Smuzhiyun 		.reg = 2,
54*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_ALARM1_MASK,
55*4882a593Smuzhiyun 	},
56*4882a593Smuzhiyun 	[MAX8998_IRQ_ALARM0] = {
57*4882a593Smuzhiyun 		.reg = 2,
58*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_ALARM0_MASK,
59*4882a593Smuzhiyun 	},
60*4882a593Smuzhiyun 	[MAX8998_IRQ_ONKEY1S] = {
61*4882a593Smuzhiyun 		.reg = 3,
62*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_ONKEY1S_MASK,
63*4882a593Smuzhiyun 	},
64*4882a593Smuzhiyun 	[MAX8998_IRQ_TOPOFFR] = {
65*4882a593Smuzhiyun 		.reg = 3,
66*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_TOPOFFR_MASK,
67*4882a593Smuzhiyun 	},
68*4882a593Smuzhiyun 	[MAX8998_IRQ_DCINOVPR] = {
69*4882a593Smuzhiyun 		.reg = 3,
70*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_DCINOVPR_MASK,
71*4882a593Smuzhiyun 	},
72*4882a593Smuzhiyun 	[MAX8998_IRQ_CHGRSTF] = {
73*4882a593Smuzhiyun 		.reg = 3,
74*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_CHGRSTF_MASK,
75*4882a593Smuzhiyun 	},
76*4882a593Smuzhiyun 	[MAX8998_IRQ_DONER] = {
77*4882a593Smuzhiyun 		.reg = 3,
78*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_DONER_MASK,
79*4882a593Smuzhiyun 	},
80*4882a593Smuzhiyun 	[MAX8998_IRQ_CHGFAULT] = {
81*4882a593Smuzhiyun 		.reg = 3,
82*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_CHGFAULT_MASK,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun 	[MAX8998_IRQ_LOBAT1] = {
85*4882a593Smuzhiyun 		.reg = 4,
86*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_LOBAT1_MASK,
87*4882a593Smuzhiyun 	},
88*4882a593Smuzhiyun 	[MAX8998_IRQ_LOBAT2] = {
89*4882a593Smuzhiyun 		.reg = 4,
90*4882a593Smuzhiyun 		.mask = MAX8998_IRQ_LOBAT2_MASK,
91*4882a593Smuzhiyun 	},
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun static inline struct max8998_irq_data *
irq_to_max8998_irq(struct max8998_dev * max8998,struct irq_data * data)95*4882a593Smuzhiyun irq_to_max8998_irq(struct max8998_dev *max8998, struct irq_data *data)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	return &max8998_irqs[data->hwirq];
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
max8998_irq_lock(struct irq_data * data)100*4882a593Smuzhiyun static void max8998_irq_lock(struct irq_data *data)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	mutex_lock(&max8998->irqlock);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
max8998_irq_sync_unlock(struct irq_data * data)107*4882a593Smuzhiyun static void max8998_irq_sync_unlock(struct irq_data *data)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
110*4882a593Smuzhiyun 	int i;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
113*4882a593Smuzhiyun 		/*
114*4882a593Smuzhiyun 		 * If there's been a change in the mask write it back
115*4882a593Smuzhiyun 		 * to the hardware.
116*4882a593Smuzhiyun 		 */
117*4882a593Smuzhiyun 		if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
118*4882a593Smuzhiyun 			max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
119*4882a593Smuzhiyun 			max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
120*4882a593Smuzhiyun 					max8998->irq_masks_cur[i]);
121*4882a593Smuzhiyun 		}
122*4882a593Smuzhiyun 	}
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	mutex_unlock(&max8998->irqlock);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
max8998_irq_unmask(struct irq_data * data)127*4882a593Smuzhiyun static void max8998_irq_unmask(struct irq_data *data)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
130*4882a593Smuzhiyun 	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
max8998_irq_mask(struct irq_data * data)135*4882a593Smuzhiyun static void max8998_irq_mask(struct irq_data *data)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
138*4882a593Smuzhiyun 	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static struct irq_chip max8998_irq_chip = {
144*4882a593Smuzhiyun 	.name = "max8998",
145*4882a593Smuzhiyun 	.irq_bus_lock = max8998_irq_lock,
146*4882a593Smuzhiyun 	.irq_bus_sync_unlock = max8998_irq_sync_unlock,
147*4882a593Smuzhiyun 	.irq_mask = max8998_irq_mask,
148*4882a593Smuzhiyun 	.irq_unmask = max8998_irq_unmask,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
max8998_irq_thread(int irq,void * data)151*4882a593Smuzhiyun static irqreturn_t max8998_irq_thread(int irq, void *data)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct max8998_dev *max8998 = data;
154*4882a593Smuzhiyun 	u8 irq_reg[MAX8998_NUM_IRQ_REGS];
155*4882a593Smuzhiyun 	int ret;
156*4882a593Smuzhiyun 	int i;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
159*4882a593Smuzhiyun 			MAX8998_NUM_IRQ_REGS, irq_reg);
160*4882a593Smuzhiyun 	if (ret < 0) {
161*4882a593Smuzhiyun 		dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
162*4882a593Smuzhiyun 				ret);
163*4882a593Smuzhiyun 		return IRQ_NONE;
164*4882a593Smuzhiyun 	}
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	/* Apply masking */
167*4882a593Smuzhiyun 	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
168*4882a593Smuzhiyun 		irq_reg[i] &= ~max8998->irq_masks_cur[i];
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	/* Report */
171*4882a593Smuzhiyun 	for (i = 0; i < MAX8998_IRQ_NR; i++) {
172*4882a593Smuzhiyun 		if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
173*4882a593Smuzhiyun 			irq = irq_find_mapping(max8998->irq_domain, i);
174*4882a593Smuzhiyun 			if (WARN_ON(!irq)) {
175*4882a593Smuzhiyun 				disable_irq_nosync(max8998->irq);
176*4882a593Smuzhiyun 				return IRQ_NONE;
177*4882a593Smuzhiyun 			}
178*4882a593Smuzhiyun 			handle_nested_irq(irq);
179*4882a593Smuzhiyun 		}
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	return IRQ_HANDLED;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun 
max8998_irq_resume(struct max8998_dev * max8998)185*4882a593Smuzhiyun int max8998_irq_resume(struct max8998_dev *max8998)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	if (max8998->irq && max8998->irq_domain)
188*4882a593Smuzhiyun 		max8998_irq_thread(max8998->irq, max8998);
189*4882a593Smuzhiyun 	return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
max8998_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)192*4882a593Smuzhiyun static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
193*4882a593Smuzhiyun 					irq_hw_number_t hw)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct max8997_dev *max8998 = d->host_data;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	irq_set_chip_data(irq, max8998);
198*4882a593Smuzhiyun 	irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
199*4882a593Smuzhiyun 	irq_set_nested_thread(irq, 1);
200*4882a593Smuzhiyun 	irq_set_noprobe(irq);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct irq_domain_ops max8998_irq_domain_ops = {
206*4882a593Smuzhiyun 	.map = max8998_irq_domain_map,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
max8998_irq_init(struct max8998_dev * max8998)209*4882a593Smuzhiyun int max8998_irq_init(struct max8998_dev *max8998)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	int i;
212*4882a593Smuzhiyun 	int ret;
213*4882a593Smuzhiyun 	struct irq_domain *domain;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	if (!max8998->irq) {
216*4882a593Smuzhiyun 		dev_warn(max8998->dev,
217*4882a593Smuzhiyun 			 "No interrupt specified, no interrupts\n");
218*4882a593Smuzhiyun 		return 0;
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	mutex_init(&max8998->irqlock);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/* Mask the individual interrupt sources */
224*4882a593Smuzhiyun 	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
225*4882a593Smuzhiyun 		max8998->irq_masks_cur[i] = 0xff;
226*4882a593Smuzhiyun 		max8998->irq_masks_cache[i] = 0xff;
227*4882a593Smuzhiyun 		max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
228*4882a593Smuzhiyun 	}
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
231*4882a593Smuzhiyun 	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
234*4882a593Smuzhiyun 			max8998->irq_base, &max8998_irq_domain_ops, max8998);
235*4882a593Smuzhiyun 	if (!domain) {
236*4882a593Smuzhiyun 		dev_err(max8998->dev, "could not create irq domain\n");
237*4882a593Smuzhiyun 		return -ENODEV;
238*4882a593Smuzhiyun 	}
239*4882a593Smuzhiyun 	max8998->irq_domain = domain;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
242*4882a593Smuzhiyun 				   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
243*4882a593Smuzhiyun 				   "max8998-irq", max8998);
244*4882a593Smuzhiyun 	if (ret) {
245*4882a593Smuzhiyun 		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
246*4882a593Smuzhiyun 			max8998->irq, ret);
247*4882a593Smuzhiyun 		return ret;
248*4882a593Smuzhiyun 	}
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	if (!max8998->ono)
251*4882a593Smuzhiyun 		return 0;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
254*4882a593Smuzhiyun 				   IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
255*4882a593Smuzhiyun 				   IRQF_ONESHOT, "max8998-ono", max8998);
256*4882a593Smuzhiyun 	if (ret)
257*4882a593Smuzhiyun 		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
258*4882a593Smuzhiyun 			max8998->ono, ret);
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	return 0;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun 
max8998_irq_exit(struct max8998_dev * max8998)263*4882a593Smuzhiyun void max8998_irq_exit(struct max8998_dev *max8998)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	if (max8998->ono)
266*4882a593Smuzhiyun 		free_irq(max8998->ono, max8998);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	if (max8998->irq)
269*4882a593Smuzhiyun 		free_irq(max8998->irq, max8998);
270*4882a593Smuzhiyun }
271