1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // max8997-irq.c - Interrupt controller support for MAX8997
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2011 Samsung Electronics Co.Ltd
6*4882a593Smuzhiyun // MyungJoo Ham <myungjoo.ham@samsung.com>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // This driver is based on max8998-irq.c
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/mfd/max8997.h>
14*4882a593Smuzhiyun #include <linux/mfd/max8997-private.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static const u8 max8997_mask_reg[] = {
17*4882a593Smuzhiyun [PMIC_INT1] = MAX8997_REG_INT1MSK,
18*4882a593Smuzhiyun [PMIC_INT2] = MAX8997_REG_INT2MSK,
19*4882a593Smuzhiyun [PMIC_INT3] = MAX8997_REG_INT3MSK,
20*4882a593Smuzhiyun [PMIC_INT4] = MAX8997_REG_INT4MSK,
21*4882a593Smuzhiyun [FUEL_GAUGE] = MAX8997_REG_INVALID,
22*4882a593Smuzhiyun [MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
23*4882a593Smuzhiyun [MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
24*4882a593Smuzhiyun [MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
25*4882a593Smuzhiyun [GPIO_LOW] = MAX8997_REG_INVALID,
26*4882a593Smuzhiyun [GPIO_HI] = MAX8997_REG_INVALID,
27*4882a593Smuzhiyun [FLASH_STATUS] = MAX8997_REG_INVALID,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
get_i2c(struct max8997_dev * max8997,enum max8997_irq_source src)30*4882a593Smuzhiyun static struct i2c_client *get_i2c(struct max8997_dev *max8997,
31*4882a593Smuzhiyun enum max8997_irq_source src)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun switch (src) {
34*4882a593Smuzhiyun case PMIC_INT1 ... PMIC_INT4:
35*4882a593Smuzhiyun return max8997->i2c;
36*4882a593Smuzhiyun case FUEL_GAUGE:
37*4882a593Smuzhiyun return NULL;
38*4882a593Smuzhiyun case MUIC_INT1 ... MUIC_INT3:
39*4882a593Smuzhiyun return max8997->muic;
40*4882a593Smuzhiyun case GPIO_LOW ... GPIO_HI:
41*4882a593Smuzhiyun return max8997->i2c;
42*4882a593Smuzhiyun case FLASH_STATUS:
43*4882a593Smuzhiyun return max8997->i2c;
44*4882a593Smuzhiyun default:
45*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct max8997_irq_data {
50*4882a593Smuzhiyun int mask;
51*4882a593Smuzhiyun enum max8997_irq_source group;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define DECLARE_IRQ(idx, _group, _mask) \
55*4882a593Smuzhiyun [(idx)] = { .group = (_group), .mask = (_mask) }
56*4882a593Smuzhiyun static const struct max8997_irq_data max8997_irqs[] = {
57*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0),
58*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1),
59*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3),
60*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4),
61*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5),
62*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6),
63*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7),
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0),
66*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1),
67*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2),
68*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3),
69*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4),
70*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5),
71*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0),
74*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1),
75*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2),
76*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3),
77*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5),
78*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7),
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0),
81*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1),
82*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2),
83*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3),
84*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4),
85*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5),
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2),
88*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1),
89*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0),
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4),
92*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3),
93*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2),
94*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1),
95*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0),
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2),
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
max8997_irq_lock(struct irq_data * data)100*4882a593Smuzhiyun static void max8997_irq_lock(struct irq_data *data)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun mutex_lock(&max8997->irqlock);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
max8997_irq_sync_unlock(struct irq_data * data)107*4882a593Smuzhiyun static void max8997_irq_sync_unlock(struct irq_data *data)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
110*4882a593Smuzhiyun int i;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
113*4882a593Smuzhiyun u8 mask_reg = max8997_mask_reg[i];
114*4882a593Smuzhiyun struct i2c_client *i2c = get_i2c(max8997, i);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (mask_reg == MAX8997_REG_INVALID ||
117*4882a593Smuzhiyun IS_ERR_OR_NULL(i2c))
118*4882a593Smuzhiyun continue;
119*4882a593Smuzhiyun max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun max8997_write_reg(i2c, max8997_mask_reg[i],
122*4882a593Smuzhiyun max8997->irq_masks_cur[i]);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun mutex_unlock(&max8997->irqlock);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun inline static const struct max8997_irq_data *
irq_to_max8997_irq(struct max8997_dev * max8997,struct irq_data * data)129*4882a593Smuzhiyun irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun return &max8997_irqs[data->hwirq];
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
max8997_irq_mask(struct irq_data * data)134*4882a593Smuzhiyun static void max8997_irq_mask(struct irq_data *data)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
137*4882a593Smuzhiyun const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
138*4882a593Smuzhiyun data);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
max8997_irq_unmask(struct irq_data * data)143*4882a593Smuzhiyun static void max8997_irq_unmask(struct irq_data *data)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
146*4882a593Smuzhiyun const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
147*4882a593Smuzhiyun data);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static struct irq_chip max8997_irq_chip = {
153*4882a593Smuzhiyun .name = "max8997",
154*4882a593Smuzhiyun .irq_bus_lock = max8997_irq_lock,
155*4882a593Smuzhiyun .irq_bus_sync_unlock = max8997_irq_sync_unlock,
156*4882a593Smuzhiyun .irq_mask = max8997_irq_mask,
157*4882a593Smuzhiyun .irq_unmask = max8997_irq_unmask,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define MAX8997_IRQSRC_PMIC (1 << 1)
161*4882a593Smuzhiyun #define MAX8997_IRQSRC_FUELGAUGE (1 << 2)
162*4882a593Smuzhiyun #define MAX8997_IRQSRC_MUIC (1 << 3)
163*4882a593Smuzhiyun #define MAX8997_IRQSRC_GPIO (1 << 4)
164*4882a593Smuzhiyun #define MAX8997_IRQSRC_FLASH (1 << 5)
max8997_irq_thread(int irq,void * data)165*4882a593Smuzhiyun static irqreturn_t max8997_irq_thread(int irq, void *data)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct max8997_dev *max8997 = data;
168*4882a593Smuzhiyun u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
169*4882a593Smuzhiyun u8 irq_src;
170*4882a593Smuzhiyun int ret;
171*4882a593Smuzhiyun int i, cur_irq;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
174*4882a593Smuzhiyun if (ret < 0) {
175*4882a593Smuzhiyun dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
176*4882a593Smuzhiyun ret);
177*4882a593Smuzhiyun return IRQ_NONE;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun if (irq_src & MAX8997_IRQSRC_PMIC) {
181*4882a593Smuzhiyun /* PMIC INT1 ~ INT4 */
182*4882a593Smuzhiyun max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
183*4882a593Smuzhiyun &irq_reg[PMIC_INT1]);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
186*4882a593Smuzhiyun /*
187*4882a593Smuzhiyun * TODO: FUEL GAUGE
188*4882a593Smuzhiyun *
189*4882a593Smuzhiyun * This is to be supported by Max17042 driver. When
190*4882a593Smuzhiyun * an interrupt incurs here, it should be relayed to a
191*4882a593Smuzhiyun * Max17042 device that is connected (probably by
192*4882a593Smuzhiyun * platform-data). However, we do not have interrupt
193*4882a593Smuzhiyun * handling in Max17042 driver currently. The Max17042 IRQ
194*4882a593Smuzhiyun * driver should be ready to be used as a stand-alone device and
195*4882a593Smuzhiyun * a Max8997-dependent device. Because it is not ready in
196*4882a593Smuzhiyun * Max17042-side and it is not too critical in operating
197*4882a593Smuzhiyun * Max8997, we do not implement this in initial releases.
198*4882a593Smuzhiyun */
199*4882a593Smuzhiyun irq_reg[FUEL_GAUGE] = 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun if (irq_src & MAX8997_IRQSRC_MUIC) {
202*4882a593Smuzhiyun /* MUIC INT1 ~ INT3 */
203*4882a593Smuzhiyun max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
204*4882a593Smuzhiyun &irq_reg[MUIC_INT1]);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun if (irq_src & MAX8997_IRQSRC_GPIO) {
207*4882a593Smuzhiyun /* GPIO Interrupt */
208*4882a593Smuzhiyun u8 gpio_info[MAX8997_NUM_GPIO];
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun irq_reg[GPIO_LOW] = 0;
211*4882a593Smuzhiyun irq_reg[GPIO_HI] = 0;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
214*4882a593Smuzhiyun MAX8997_NUM_GPIO, gpio_info);
215*4882a593Smuzhiyun for (i = 0; i < MAX8997_NUM_GPIO; i++) {
216*4882a593Smuzhiyun bool interrupt = false;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
219*4882a593Smuzhiyun case MAX8997_GPIO_INT_BOTH:
220*4882a593Smuzhiyun if (max8997->gpio_status[i] != gpio_info[i])
221*4882a593Smuzhiyun interrupt = true;
222*4882a593Smuzhiyun break;
223*4882a593Smuzhiyun case MAX8997_GPIO_INT_RISE:
224*4882a593Smuzhiyun if ((max8997->gpio_status[i] != gpio_info[i]) &&
225*4882a593Smuzhiyun (gpio_info[i] & MAX8997_GPIO_DATA_MASK))
226*4882a593Smuzhiyun interrupt = true;
227*4882a593Smuzhiyun break;
228*4882a593Smuzhiyun case MAX8997_GPIO_INT_FALL:
229*4882a593Smuzhiyun if ((max8997->gpio_status[i] != gpio_info[i]) &&
230*4882a593Smuzhiyun !(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
231*4882a593Smuzhiyun interrupt = true;
232*4882a593Smuzhiyun break;
233*4882a593Smuzhiyun default:
234*4882a593Smuzhiyun break;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun if (interrupt) {
238*4882a593Smuzhiyun if (i < 8)
239*4882a593Smuzhiyun irq_reg[GPIO_LOW] |= (1 << i);
240*4882a593Smuzhiyun else
241*4882a593Smuzhiyun irq_reg[GPIO_HI] |= (1 << (i - 8));
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun if (irq_src & MAX8997_IRQSRC_FLASH) {
247*4882a593Smuzhiyun /* Flash Status Interrupt */
248*4882a593Smuzhiyun ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
249*4882a593Smuzhiyun &irq_reg[FLASH_STATUS]);
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun /* Apply masking */
253*4882a593Smuzhiyun for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
254*4882a593Smuzhiyun irq_reg[i] &= ~max8997->irq_masks_cur[i];
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* Report */
257*4882a593Smuzhiyun for (i = 0; i < MAX8997_IRQ_NR; i++) {
258*4882a593Smuzhiyun if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
259*4882a593Smuzhiyun cur_irq = irq_find_mapping(max8997->irq_domain, i);
260*4882a593Smuzhiyun if (cur_irq)
261*4882a593Smuzhiyun handle_nested_irq(cur_irq);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return IRQ_HANDLED;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
max8997_irq_resume(struct max8997_dev * max8997)268*4882a593Smuzhiyun int max8997_irq_resume(struct max8997_dev *max8997)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun if (max8997->irq && max8997->irq_domain)
271*4882a593Smuzhiyun max8997_irq_thread(0, max8997);
272*4882a593Smuzhiyun return 0;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
max8997_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)275*4882a593Smuzhiyun static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
276*4882a593Smuzhiyun irq_hw_number_t hw)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct max8997_dev *max8997 = d->host_data;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun irq_set_chip_data(irq, max8997);
281*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
282*4882a593Smuzhiyun irq_set_nested_thread(irq, 1);
283*4882a593Smuzhiyun irq_set_noprobe(irq);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun static const struct irq_domain_ops max8997_irq_domain_ops = {
289*4882a593Smuzhiyun .map = max8997_irq_domain_map,
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun
max8997_irq_init(struct max8997_dev * max8997)292*4882a593Smuzhiyun int max8997_irq_init(struct max8997_dev *max8997)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun struct irq_domain *domain;
295*4882a593Smuzhiyun int i;
296*4882a593Smuzhiyun int ret;
297*4882a593Smuzhiyun u8 val;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (!max8997->irq) {
300*4882a593Smuzhiyun dev_warn(max8997->dev, "No interrupt specified.\n");
301*4882a593Smuzhiyun return 0;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun mutex_init(&max8997->irqlock);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* Mask individual interrupt sources */
307*4882a593Smuzhiyun for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
308*4882a593Smuzhiyun struct i2c_client *i2c;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun max8997->irq_masks_cur[i] = 0xff;
311*4882a593Smuzhiyun max8997->irq_masks_cache[i] = 0xff;
312*4882a593Smuzhiyun i2c = get_i2c(max8997, i);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun if (IS_ERR_OR_NULL(i2c))
315*4882a593Smuzhiyun continue;
316*4882a593Smuzhiyun if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
317*4882a593Smuzhiyun continue;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun for (i = 0; i < MAX8997_NUM_GPIO; i++) {
323*4882a593Smuzhiyun max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
324*4882a593Smuzhiyun MAX8997_REG_GPIOCNTL1 + i,
325*4882a593Smuzhiyun &val)
326*4882a593Smuzhiyun & MAX8997_GPIO_DATA_MASK) ?
327*4882a593Smuzhiyun true : false;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
331*4882a593Smuzhiyun &max8997_irq_domain_ops, max8997);
332*4882a593Smuzhiyun if (!domain) {
333*4882a593Smuzhiyun dev_err(max8997->dev, "could not create irq domain\n");
334*4882a593Smuzhiyun return -ENODEV;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun max8997->irq_domain = domain;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
339*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
340*4882a593Smuzhiyun "max8997-irq", max8997);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun if (ret) {
343*4882a593Smuzhiyun dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
344*4882a593Smuzhiyun max8997->irq, ret);
345*4882a593Smuzhiyun return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun if (!max8997->ono)
349*4882a593Smuzhiyun return 0;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
352*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
353*4882a593Smuzhiyun IRQF_ONESHOT, "max8997-ono", max8997);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (ret)
356*4882a593Smuzhiyun dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
357*4882a593Smuzhiyun max8997->ono, ret);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun return 0;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
max8997_irq_exit(struct max8997_dev * max8997)362*4882a593Smuzhiyun void max8997_irq_exit(struct max8997_dev *max8997)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun if (max8997->ono)
365*4882a593Smuzhiyun free_irq(max8997->ono, max8997);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun if (max8997->irq)
368*4882a593Smuzhiyun free_irq(max8997->irq, max8997);
369*4882a593Smuzhiyun }
370