xref: /OK3568_Linux_fs/kernel/drivers/mfd/max77650.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (C) 2018 BayLibre SAS
4*4882a593Smuzhiyun // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // Core MFD driver for MAXIM 77650/77651 charger/power-supply.
7*4882a593Smuzhiyun // Programming manual: https://pdfserv.maximintegrated.com/en/an/AN6428.pdf
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/mfd/core.h>
13*4882a593Smuzhiyun #include <linux/mfd/max77650.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define MAX77650_INT_GPI_F_MSK		BIT(0)
19*4882a593Smuzhiyun #define MAX77650_INT_GPI_R_MSK		BIT(1)
20*4882a593Smuzhiyun #define MAX77650_INT_GPI_MSK \
21*4882a593Smuzhiyun 			(MAX77650_INT_GPI_F_MSK | MAX77650_INT_GPI_R_MSK)
22*4882a593Smuzhiyun #define MAX77650_INT_nEN_F_MSK		BIT(2)
23*4882a593Smuzhiyun #define MAX77650_INT_nEN_R_MSK		BIT(3)
24*4882a593Smuzhiyun #define MAX77650_INT_TJAL1_R_MSK	BIT(4)
25*4882a593Smuzhiyun #define MAX77650_INT_TJAL2_R_MSK	BIT(5)
26*4882a593Smuzhiyun #define MAX77650_INT_DOD_R_MSK		BIT(6)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define MAX77650_INT_THM_MSK		BIT(0)
29*4882a593Smuzhiyun #define MAX77650_INT_CHG_MSK		BIT(1)
30*4882a593Smuzhiyun #define MAX77650_INT_CHGIN_MSK		BIT(2)
31*4882a593Smuzhiyun #define MAX77650_INT_TJ_REG_MSK		BIT(3)
32*4882a593Smuzhiyun #define MAX77650_INT_CHGIN_CTRL_MSK	BIT(4)
33*4882a593Smuzhiyun #define MAX77650_INT_SYS_CTRL_MSK	BIT(5)
34*4882a593Smuzhiyun #define MAX77650_INT_SYS_CNFG_MSK	BIT(6)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MAX77650_INT_GLBL_OFFSET	0
37*4882a593Smuzhiyun #define MAX77650_INT_CHG_OFFSET		1
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define MAX77650_SBIA_LPM_MASK		BIT(5)
40*4882a593Smuzhiyun #define MAX77650_SBIA_LPM_DISABLED	0x00
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun enum {
43*4882a593Smuzhiyun 	MAX77650_INT_GPI,
44*4882a593Smuzhiyun 	MAX77650_INT_nEN_F,
45*4882a593Smuzhiyun 	MAX77650_INT_nEN_R,
46*4882a593Smuzhiyun 	MAX77650_INT_TJAL1_R,
47*4882a593Smuzhiyun 	MAX77650_INT_TJAL2_R,
48*4882a593Smuzhiyun 	MAX77650_INT_DOD_R,
49*4882a593Smuzhiyun 	MAX77650_INT_THM,
50*4882a593Smuzhiyun 	MAX77650_INT_CHG,
51*4882a593Smuzhiyun 	MAX77650_INT_CHGIN,
52*4882a593Smuzhiyun 	MAX77650_INT_TJ_REG,
53*4882a593Smuzhiyun 	MAX77650_INT_CHGIN_CTRL,
54*4882a593Smuzhiyun 	MAX77650_INT_SYS_CTRL,
55*4882a593Smuzhiyun 	MAX77650_INT_SYS_CNFG,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun static const struct resource max77650_charger_resources[] = {
59*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHG, "CHG"),
60*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHGIN, "CHGIN"),
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static const struct resource max77650_gpio_resources[] = {
64*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_GPI, "GPI"),
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun static const struct resource max77650_onkey_resources[] = {
68*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_F, "nEN_F"),
69*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_R, "nEN_R"),
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static const struct mfd_cell max77650_cells[] = {
73*4882a593Smuzhiyun 	{
74*4882a593Smuzhiyun 		.name		= "max77650-regulator",
75*4882a593Smuzhiyun 		.of_compatible	= "maxim,max77650-regulator",
76*4882a593Smuzhiyun 	}, {
77*4882a593Smuzhiyun 		.name		= "max77650-charger",
78*4882a593Smuzhiyun 		.of_compatible	= "maxim,max77650-charger",
79*4882a593Smuzhiyun 		.resources	= max77650_charger_resources,
80*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(max77650_charger_resources),
81*4882a593Smuzhiyun 	}, {
82*4882a593Smuzhiyun 		.name		= "max77650-gpio",
83*4882a593Smuzhiyun 		.of_compatible	= "maxim,max77650-gpio",
84*4882a593Smuzhiyun 		.resources	= max77650_gpio_resources,
85*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(max77650_gpio_resources),
86*4882a593Smuzhiyun 	}, {
87*4882a593Smuzhiyun 		.name		= "max77650-led",
88*4882a593Smuzhiyun 		.of_compatible	= "maxim,max77650-led",
89*4882a593Smuzhiyun 	}, {
90*4882a593Smuzhiyun 		.name		= "max77650-onkey",
91*4882a593Smuzhiyun 		.of_compatible	= "maxim,max77650-onkey",
92*4882a593Smuzhiyun 		.resources	= max77650_onkey_resources,
93*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(max77650_onkey_resources),
94*4882a593Smuzhiyun 	},
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static const struct regmap_irq max77650_irqs[] = {
98*4882a593Smuzhiyun 	[MAX77650_INT_GPI] = {
99*4882a593Smuzhiyun 		.reg_offset = MAX77650_INT_GLBL_OFFSET,
100*4882a593Smuzhiyun 		.mask = MAX77650_INT_GPI_MSK,
101*4882a593Smuzhiyun 		.type = {
102*4882a593Smuzhiyun 			.type_falling_val = MAX77650_INT_GPI_F_MSK,
103*4882a593Smuzhiyun 			.type_rising_val = MAX77650_INT_GPI_R_MSK,
104*4882a593Smuzhiyun 			.types_supported = IRQ_TYPE_EDGE_BOTH,
105*4882a593Smuzhiyun 		},
106*4882a593Smuzhiyun 	},
107*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_nEN_F,
108*4882a593Smuzhiyun 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_F_MSK),
109*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_nEN_R,
110*4882a593Smuzhiyun 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_R_MSK),
111*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_TJAL1_R,
112*4882a593Smuzhiyun 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL1_R_MSK),
113*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_TJAL2_R,
114*4882a593Smuzhiyun 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL2_R_MSK),
115*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_DOD_R,
116*4882a593Smuzhiyun 		       MAX77650_INT_GLBL_OFFSET, MAX77650_INT_DOD_R_MSK),
117*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_THM,
118*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_THM_MSK),
119*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_CHG,
120*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHG_MSK),
121*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_CHGIN,
122*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_MSK),
123*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_TJ_REG,
124*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_TJ_REG_MSK),
125*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_CHGIN_CTRL,
126*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_CTRL_MSK),
127*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_SYS_CTRL,
128*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CTRL_MSK),
129*4882a593Smuzhiyun 	REGMAP_IRQ_REG(MAX77650_INT_SYS_CNFG,
130*4882a593Smuzhiyun 		       MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CNFG_MSK),
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static const struct regmap_irq_chip max77650_irq_chip = {
134*4882a593Smuzhiyun 	.name			= "max77650-irq",
135*4882a593Smuzhiyun 	.irqs			= max77650_irqs,
136*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(max77650_irqs),
137*4882a593Smuzhiyun 	.num_regs		= 2,
138*4882a593Smuzhiyun 	.status_base		= MAX77650_REG_INT_GLBL,
139*4882a593Smuzhiyun 	.mask_base		= MAX77650_REG_INTM_GLBL,
140*4882a593Smuzhiyun 	.type_in_mask		= true,
141*4882a593Smuzhiyun 	.type_invert		= true,
142*4882a593Smuzhiyun 	.init_ack_masked	= true,
143*4882a593Smuzhiyun 	.clear_on_unmask	= true,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static const struct regmap_config max77650_regmap_config = {
147*4882a593Smuzhiyun 	.name		= "max77650",
148*4882a593Smuzhiyun 	.reg_bits	= 8,
149*4882a593Smuzhiyun 	.val_bits	= 8,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
max77650_i2c_probe(struct i2c_client * i2c)152*4882a593Smuzhiyun static int max77650_i2c_probe(struct i2c_client *i2c)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	struct regmap_irq_chip_data *irq_data;
155*4882a593Smuzhiyun 	struct device *dev = &i2c->dev;
156*4882a593Smuzhiyun 	struct irq_domain *domain;
157*4882a593Smuzhiyun 	struct regmap *map;
158*4882a593Smuzhiyun 	unsigned int val;
159*4882a593Smuzhiyun 	int rv, id;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	map = devm_regmap_init_i2c(i2c, &max77650_regmap_config);
162*4882a593Smuzhiyun 	if (IS_ERR(map)) {
163*4882a593Smuzhiyun 		dev_err(dev, "Unable to initialise I2C Regmap\n");
164*4882a593Smuzhiyun 		return PTR_ERR(map);
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	rv = regmap_read(map, MAX77650_REG_CID, &val);
168*4882a593Smuzhiyun 	if (rv) {
169*4882a593Smuzhiyun 		dev_err(dev, "Unable to read Chip ID\n");
170*4882a593Smuzhiyun 		return rv;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	id = MAX77650_CID_BITS(val);
174*4882a593Smuzhiyun 	switch (id) {
175*4882a593Smuzhiyun 	case MAX77650_CID_77650A:
176*4882a593Smuzhiyun 	case MAX77650_CID_77650C:
177*4882a593Smuzhiyun 	case MAX77650_CID_77651A:
178*4882a593Smuzhiyun 	case MAX77650_CID_77651B:
179*4882a593Smuzhiyun 		break;
180*4882a593Smuzhiyun 	default:
181*4882a593Smuzhiyun 		dev_err(dev, "Chip not supported - ID: 0x%02x\n", id);
182*4882a593Smuzhiyun 		return -ENODEV;
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	/*
186*4882a593Smuzhiyun 	 * This IC has a low-power mode which reduces the quiescent current
187*4882a593Smuzhiyun 	 * consumption to ~5.6uA but is only suitable for systems consuming
188*4882a593Smuzhiyun 	 * less than ~2mA. Since this is not likely the case even on
189*4882a593Smuzhiyun 	 * linux-based wearables - keep the chip in normal power mode.
190*4882a593Smuzhiyun 	 */
191*4882a593Smuzhiyun 	rv = regmap_update_bits(map,
192*4882a593Smuzhiyun 				MAX77650_REG_CNFG_GLBL,
193*4882a593Smuzhiyun 				MAX77650_SBIA_LPM_MASK,
194*4882a593Smuzhiyun 				MAX77650_SBIA_LPM_DISABLED);
195*4882a593Smuzhiyun 	if (rv) {
196*4882a593Smuzhiyun 		dev_err(dev, "Unable to change the power mode\n");
197*4882a593Smuzhiyun 		return rv;
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	rv = devm_regmap_add_irq_chip(dev, map, i2c->irq,
201*4882a593Smuzhiyun 				      IRQF_ONESHOT | IRQF_SHARED, 0,
202*4882a593Smuzhiyun 				      &max77650_irq_chip, &irq_data);
203*4882a593Smuzhiyun 	if (rv) {
204*4882a593Smuzhiyun 		dev_err(dev, "Unable to add Regmap IRQ chip\n");
205*4882a593Smuzhiyun 		return rv;
206*4882a593Smuzhiyun 	}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	domain = regmap_irq_get_domain(irq_data);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
211*4882a593Smuzhiyun 				    max77650_cells, ARRAY_SIZE(max77650_cells),
212*4882a593Smuzhiyun 				    NULL, 0, domain);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun static const struct of_device_id max77650_of_match[] = {
216*4882a593Smuzhiyun 	{ .compatible = "maxim,max77650" },
217*4882a593Smuzhiyun 	{ }
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max77650_of_match);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static struct i2c_driver max77650_i2c_driver = {
222*4882a593Smuzhiyun 	.driver = {
223*4882a593Smuzhiyun 		.name = "max77650",
224*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(max77650_of_match),
225*4882a593Smuzhiyun 	},
226*4882a593Smuzhiyun 	.probe_new = max77650_i2c_probe,
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun module_i2c_driver(max77650_i2c_driver);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun MODULE_DESCRIPTION("MAXIM 77650/77651 multi-function core driver");
231*4882a593Smuzhiyun MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
232*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
233