xref: /OK3568_Linux_fs/kernel/drivers/mfd/lm3533-ctrlbank.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * lm3533-ctrlbank.c -- LM3533 Generic Control Bank interface
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2011-2012 Texas Instruments
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Johan Hovold <jhovold@gmail.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/mfd/lm3533.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define LM3533_MAX_CURRENT_MIN		5000
17*4882a593Smuzhiyun #define LM3533_MAX_CURRENT_MAX		29800
18*4882a593Smuzhiyun #define LM3533_MAX_CURRENT_STEP		800
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define LM3533_PWM_MAX			0x3f
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define LM3533_REG_PWM_BASE		0x14
23*4882a593Smuzhiyun #define LM3533_REG_MAX_CURRENT_BASE	0x1f
24*4882a593Smuzhiyun #define LM3533_REG_CTRLBANK_ENABLE	0x27
25*4882a593Smuzhiyun #define LM3533_REG_BRIGHTNESS_BASE	0x40
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 
lm3533_ctrlbank_get_reg(struct lm3533_ctrlbank * cb,u8 base)28*4882a593Smuzhiyun static inline u8 lm3533_ctrlbank_get_reg(struct lm3533_ctrlbank *cb, u8 base)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	return base + cb->id;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun 
lm3533_ctrlbank_enable(struct lm3533_ctrlbank * cb)33*4882a593Smuzhiyun int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	u8 mask;
36*4882a593Smuzhiyun 	int ret;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	dev_dbg(cb->dev, "%s - %d\n", __func__, cb->id);
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	mask = 1 << cb->id;
41*4882a593Smuzhiyun 	ret = lm3533_update(cb->lm3533, LM3533_REG_CTRLBANK_ENABLE,
42*4882a593Smuzhiyun 								mask, mask);
43*4882a593Smuzhiyun 	if (ret)
44*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to enable ctrlbank %d\n", cb->id);
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	return ret;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_enable);
49*4882a593Smuzhiyun 
lm3533_ctrlbank_disable(struct lm3533_ctrlbank * cb)50*4882a593Smuzhiyun int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	u8 mask;
53*4882a593Smuzhiyun 	int ret;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	dev_dbg(cb->dev, "%s - %d\n", __func__, cb->id);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	mask = 1 << cb->id;
58*4882a593Smuzhiyun 	ret = lm3533_update(cb->lm3533, LM3533_REG_CTRLBANK_ENABLE, 0, mask);
59*4882a593Smuzhiyun 	if (ret)
60*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to disable ctrlbank %d\n", cb->id);
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	return ret;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_disable);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun  * Full-scale current.
68*4882a593Smuzhiyun  *
69*4882a593Smuzhiyun  * imax		5000 - 29800 uA (800 uA step)
70*4882a593Smuzhiyun  */
lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank * cb,u16 imax)71*4882a593Smuzhiyun int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb, u16 imax)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	u8 reg;
74*4882a593Smuzhiyun 	u8 val;
75*4882a593Smuzhiyun 	int ret;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	if (imax < LM3533_MAX_CURRENT_MIN || imax > LM3533_MAX_CURRENT_MAX)
78*4882a593Smuzhiyun 		return -EINVAL;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	val = (imax - LM3533_MAX_CURRENT_MIN) / LM3533_MAX_CURRENT_STEP;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_MAX_CURRENT_BASE);
83*4882a593Smuzhiyun 	ret = lm3533_write(cb->lm3533, reg, val);
84*4882a593Smuzhiyun 	if (ret)
85*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to set max current\n");
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return ret;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_max_current);
90*4882a593Smuzhiyun 
lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank * cb,u8 val)91*4882a593Smuzhiyun int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	u8 reg;
94*4882a593Smuzhiyun 	int ret;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_BRIGHTNESS_BASE);
97*4882a593Smuzhiyun 	ret = lm3533_write(cb->lm3533, reg, val);
98*4882a593Smuzhiyun 	if (ret)
99*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to set brightness\n");
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return ret;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_brightness);
104*4882a593Smuzhiyun 
lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank * cb,u8 * val)105*4882a593Smuzhiyun int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	u8 reg;
108*4882a593Smuzhiyun 	int ret;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_BRIGHTNESS_BASE);
111*4882a593Smuzhiyun 	ret = lm3533_read(cb->lm3533, reg, val);
112*4882a593Smuzhiyun 	if (ret)
113*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to get brightness\n");
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_get_brightness);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun  * PWM-input control mask:
121*4882a593Smuzhiyun  *
122*4882a593Smuzhiyun  *   bit 5 - PWM-input enabled in Zone 4
123*4882a593Smuzhiyun  *   bit 4 - PWM-input enabled in Zone 3
124*4882a593Smuzhiyun  *   bit 3 - PWM-input enabled in Zone 2
125*4882a593Smuzhiyun  *   bit 2 - PWM-input enabled in Zone 1
126*4882a593Smuzhiyun  *   bit 1 - PWM-input enabled in Zone 0
127*4882a593Smuzhiyun  *   bit 0 - PWM-input enabled
128*4882a593Smuzhiyun  */
lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank * cb,u8 val)129*4882a593Smuzhiyun int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	u8 reg;
132*4882a593Smuzhiyun 	int ret;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	if (val > LM3533_PWM_MAX)
135*4882a593Smuzhiyun 		return -EINVAL;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_PWM_BASE);
138*4882a593Smuzhiyun 	ret = lm3533_write(cb->lm3533, reg, val);
139*4882a593Smuzhiyun 	if (ret)
140*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to set PWM mask\n");
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	return ret;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_pwm);
145*4882a593Smuzhiyun 
lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank * cb,u8 * val)146*4882a593Smuzhiyun int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	u8 reg;
149*4882a593Smuzhiyun 	int ret;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_PWM_BASE);
152*4882a593Smuzhiyun 	ret = lm3533_read(cb->lm3533, reg, val);
153*4882a593Smuzhiyun 	if (ret)
154*4882a593Smuzhiyun 		dev_err(cb->dev, "failed to get PWM mask\n");
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	return ret;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(lm3533_ctrlbank_get_pwm);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun MODULE_AUTHOR("Johan Hovold <jhovold@gmail.com>");
161*4882a593Smuzhiyun MODULE_DESCRIPTION("LM3533 Control Bank interface");
162*4882a593Smuzhiyun MODULE_LICENSE("GPL");
163