xref: /OK3568_Linux_fs/kernel/drivers/mfd/intel_soc_pmic_chtdc_ti.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Device access for Dollar Cove TI PMIC
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2014, Intel Corporation.
6*4882a593Smuzhiyun  *   Author: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Cleanup and forward-ported
9*4882a593Smuzhiyun  *   Copyright (c) 2017 Takashi Iwai <tiwai@suse.de>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/acpi.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/mfd/core.h>
16*4882a593Smuzhiyun #include <linux/mfd/intel_soc_pmic.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define CHTDC_TI_IRQLVL1	0x01
21*4882a593Smuzhiyun #define CHTDC_TI_MASK_IRQLVL1	0x02
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /* Level 1 IRQs */
24*4882a593Smuzhiyun enum {
25*4882a593Smuzhiyun 	CHTDC_TI_PWRBTN = 0,	/* power button */
26*4882a593Smuzhiyun 	CHTDC_TI_DIETMPWARN,	/* thermal */
27*4882a593Smuzhiyun 	CHTDC_TI_ADCCMPL,	/* ADC */
28*4882a593Smuzhiyun 	/* No IRQ 3 */
29*4882a593Smuzhiyun 	CHTDC_TI_VBATLOW = 4,	/* battery */
30*4882a593Smuzhiyun 	CHTDC_TI_VBUSDET,	/* power source */
31*4882a593Smuzhiyun 	/* No IRQ 6 */
32*4882a593Smuzhiyun 	CHTDC_TI_CCEOCAL = 7,	/* battery */
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static struct resource power_button_resources[] = {
36*4882a593Smuzhiyun 	DEFINE_RES_IRQ(CHTDC_TI_PWRBTN),
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static struct resource thermal_resources[] = {
40*4882a593Smuzhiyun 	DEFINE_RES_IRQ(CHTDC_TI_DIETMPWARN),
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static struct resource adc_resources[] = {
44*4882a593Smuzhiyun 	DEFINE_RES_IRQ(CHTDC_TI_ADCCMPL),
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static struct resource pwrsrc_resources[] = {
48*4882a593Smuzhiyun 	DEFINE_RES_IRQ(CHTDC_TI_VBUSDET),
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun static struct resource battery_resources[] = {
52*4882a593Smuzhiyun 	DEFINE_RES_IRQ(CHTDC_TI_VBATLOW),
53*4882a593Smuzhiyun 	DEFINE_RES_IRQ(CHTDC_TI_CCEOCAL),
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun static struct mfd_cell chtdc_ti_dev[] = {
57*4882a593Smuzhiyun 	{
58*4882a593Smuzhiyun 		.name = "chtdc_ti_pwrbtn",
59*4882a593Smuzhiyun 		.num_resources = ARRAY_SIZE(power_button_resources),
60*4882a593Smuzhiyun 		.resources = power_button_resources,
61*4882a593Smuzhiyun 	}, {
62*4882a593Smuzhiyun 		.name = "chtdc_ti_adc",
63*4882a593Smuzhiyun 		.num_resources = ARRAY_SIZE(adc_resources),
64*4882a593Smuzhiyun 		.resources = adc_resources,
65*4882a593Smuzhiyun 	}, {
66*4882a593Smuzhiyun 		.name = "chtdc_ti_thermal",
67*4882a593Smuzhiyun 		.num_resources = ARRAY_SIZE(thermal_resources),
68*4882a593Smuzhiyun 		.resources = thermal_resources,
69*4882a593Smuzhiyun 	}, {
70*4882a593Smuzhiyun 		.name = "chtdc_ti_pwrsrc",
71*4882a593Smuzhiyun 		.num_resources = ARRAY_SIZE(pwrsrc_resources),
72*4882a593Smuzhiyun 		.resources = pwrsrc_resources,
73*4882a593Smuzhiyun 	}, {
74*4882a593Smuzhiyun 		.name = "chtdc_ti_battery",
75*4882a593Smuzhiyun 		.num_resources = ARRAY_SIZE(battery_resources),
76*4882a593Smuzhiyun 		.resources = battery_resources,
77*4882a593Smuzhiyun 	},
78*4882a593Smuzhiyun 	{	.name = "chtdc_ti_region", },
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun static const struct regmap_config chtdc_ti_regmap_config = {
82*4882a593Smuzhiyun 	.reg_bits = 8,
83*4882a593Smuzhiyun 	.val_bits = 8,
84*4882a593Smuzhiyun 	.max_register = 128,
85*4882a593Smuzhiyun 	.cache_type = REGCACHE_NONE,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun static const struct regmap_irq chtdc_ti_irqs[] = {
89*4882a593Smuzhiyun 	REGMAP_IRQ_REG(CHTDC_TI_PWRBTN, 0, BIT(CHTDC_TI_PWRBTN)),
90*4882a593Smuzhiyun 	REGMAP_IRQ_REG(CHTDC_TI_DIETMPWARN, 0, BIT(CHTDC_TI_DIETMPWARN)),
91*4882a593Smuzhiyun 	REGMAP_IRQ_REG(CHTDC_TI_ADCCMPL, 0, BIT(CHTDC_TI_ADCCMPL)),
92*4882a593Smuzhiyun 	REGMAP_IRQ_REG(CHTDC_TI_VBATLOW, 0, BIT(CHTDC_TI_VBATLOW)),
93*4882a593Smuzhiyun 	REGMAP_IRQ_REG(CHTDC_TI_VBUSDET, 0, BIT(CHTDC_TI_VBUSDET)),
94*4882a593Smuzhiyun 	REGMAP_IRQ_REG(CHTDC_TI_CCEOCAL, 0, BIT(CHTDC_TI_CCEOCAL)),
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static const struct regmap_irq_chip chtdc_ti_irq_chip = {
98*4882a593Smuzhiyun 	.name = KBUILD_MODNAME,
99*4882a593Smuzhiyun 	.irqs = chtdc_ti_irqs,
100*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(chtdc_ti_irqs),
101*4882a593Smuzhiyun 	.num_regs = 1,
102*4882a593Smuzhiyun 	.status_base = CHTDC_TI_IRQLVL1,
103*4882a593Smuzhiyun 	.mask_base = CHTDC_TI_MASK_IRQLVL1,
104*4882a593Smuzhiyun 	.ack_base = CHTDC_TI_IRQLVL1,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
chtdc_ti_probe(struct i2c_client * i2c)107*4882a593Smuzhiyun static int chtdc_ti_probe(struct i2c_client *i2c)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	struct device *dev = &i2c->dev;
110*4882a593Smuzhiyun 	struct intel_soc_pmic *pmic;
111*4882a593Smuzhiyun 	int ret;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
114*4882a593Smuzhiyun 	if (!pmic)
115*4882a593Smuzhiyun 		return -ENOMEM;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, pmic);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	pmic->regmap = devm_regmap_init_i2c(i2c, &chtdc_ti_regmap_config);
120*4882a593Smuzhiyun 	if (IS_ERR(pmic->regmap))
121*4882a593Smuzhiyun 		return PTR_ERR(pmic->regmap);
122*4882a593Smuzhiyun 	pmic->irq = i2c->irq;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
125*4882a593Smuzhiyun 				       IRQF_ONESHOT, 0,
126*4882a593Smuzhiyun 				       &chtdc_ti_irq_chip,
127*4882a593Smuzhiyun 				       &pmic->irq_chip_data);
128*4882a593Smuzhiyun 	if (ret)
129*4882a593Smuzhiyun 		return ret;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, chtdc_ti_dev,
132*4882a593Smuzhiyun 				    ARRAY_SIZE(chtdc_ti_dev), NULL, 0,
133*4882a593Smuzhiyun 				    regmap_irq_get_domain(pmic->irq_chip_data));
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
chtdc_ti_shutdown(struct i2c_client * i2c)136*4882a593Smuzhiyun static void chtdc_ti_shutdown(struct i2c_client *i2c)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	struct intel_soc_pmic *pmic = i2c_get_clientdata(i2c);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	disable_irq(pmic->irq);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
chtdc_ti_suspend(struct device * dev)143*4882a593Smuzhiyun static int __maybe_unused chtdc_ti_suspend(struct device *dev)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	disable_irq(pmic->irq);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	return 0;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
chtdc_ti_resume(struct device * dev)152*4882a593Smuzhiyun static int __maybe_unused chtdc_ti_resume(struct device *dev)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	enable_irq(pmic->irq);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(chtdc_ti_pm_ops, chtdc_ti_suspend, chtdc_ti_resume);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct acpi_device_id chtdc_ti_acpi_ids[] = {
164*4882a593Smuzhiyun 	{ "INT33F5" },
165*4882a593Smuzhiyun 	{ },
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, chtdc_ti_acpi_ids);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static struct i2c_driver chtdc_ti_i2c_driver = {
170*4882a593Smuzhiyun 	.driver = {
171*4882a593Smuzhiyun 		.name = "intel_soc_pmic_chtdc_ti",
172*4882a593Smuzhiyun 		.pm = &chtdc_ti_pm_ops,
173*4882a593Smuzhiyun 		.acpi_match_table = chtdc_ti_acpi_ids,
174*4882a593Smuzhiyun 	},
175*4882a593Smuzhiyun 	.probe_new = chtdc_ti_probe,
176*4882a593Smuzhiyun 	.shutdown = chtdc_ti_shutdown,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun module_i2c_driver(chtdc_ti_i2c_driver);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun MODULE_DESCRIPTION("I2C driver for Intel SoC Dollar Cove TI PMIC");
181*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
182