1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel Quark MFD PCI driver for I2C & GPIO
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright(c) 2014 Intel Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Intel Quark PCI device for I2C and GPIO controller sharing the same
8*4882a593Smuzhiyun * PCI function. This PCI driver will split the 2 devices into their
9*4882a593Smuzhiyun * respective drivers.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/mfd/core.h>
16*4882a593Smuzhiyun #include <linux/clkdev.h>
17*4882a593Smuzhiyun #include <linux/clk-provider.h>
18*4882a593Smuzhiyun #include <linux/dmi.h>
19*4882a593Smuzhiyun #include <linux/platform_data/gpio-dwapb.h>
20*4882a593Smuzhiyun #include <linux/platform_data/i2c-designware.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* PCI BAR for register base address */
23*4882a593Smuzhiyun #define MFD_I2C_BAR 0
24*4882a593Smuzhiyun #define MFD_GPIO_BAR 1
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* ACPI _ADR value to match the child node */
27*4882a593Smuzhiyun #define MFD_ACPI_MATCH_GPIO 0ULL
28*4882a593Smuzhiyun #define MFD_ACPI_MATCH_I2C 1ULL
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* The base GPIO number under GPIOLIB framework */
31*4882a593Smuzhiyun #define INTEL_QUARK_MFD_GPIO_BASE 8
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* The default number of South-Cluster GPIO on Quark. */
34*4882a593Smuzhiyun #define INTEL_QUARK_MFD_NGPIO 8
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* The DesignWare GPIO ports on Quark. */
37*4882a593Smuzhiyun #define INTEL_QUARK_GPIO_NPORTS 1
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define INTEL_QUARK_IORES_MEM 0
40*4882a593Smuzhiyun #define INTEL_QUARK_IORES_IRQ 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define INTEL_QUARK_I2C_CONTROLLER_CLK "i2c_designware.0"
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* The Quark I2C controller source clock */
45*4882a593Smuzhiyun #define INTEL_QUARK_I2C_CLK_HZ 33000000
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct intel_quark_mfd {
48*4882a593Smuzhiyun struct device *dev;
49*4882a593Smuzhiyun struct clk *i2c_clk;
50*4882a593Smuzhiyun struct clk_lookup *i2c_clk_lookup;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const struct dmi_system_id dmi_platform_info[] = {
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun .matches = {
56*4882a593Smuzhiyun DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
57*4882a593Smuzhiyun },
58*4882a593Smuzhiyun .driver_data = (void *)100000,
59*4882a593Smuzhiyun },
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun .matches = {
62*4882a593Smuzhiyun DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun .driver_data = (void *)400000,
65*4882a593Smuzhiyun },
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun .matches = {
68*4882a593Smuzhiyun DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
69*4882a593Smuzhiyun },
70*4882a593Smuzhiyun .driver_data = (void *)400000,
71*4882a593Smuzhiyun },
72*4882a593Smuzhiyun {}
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static struct resource intel_quark_i2c_res[] = {
76*4882a593Smuzhiyun [INTEL_QUARK_IORES_MEM] = {
77*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
78*4882a593Smuzhiyun },
79*4882a593Smuzhiyun [INTEL_QUARK_IORES_IRQ] = {
80*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
81*4882a593Smuzhiyun },
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static struct mfd_cell_acpi_match intel_quark_acpi_match_i2c = {
85*4882a593Smuzhiyun .adr = MFD_ACPI_MATCH_I2C,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static struct resource intel_quark_gpio_res[] = {
89*4882a593Smuzhiyun [INTEL_QUARK_IORES_MEM] = {
90*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static struct mfd_cell_acpi_match intel_quark_acpi_match_gpio = {
95*4882a593Smuzhiyun .adr = MFD_ACPI_MATCH_GPIO,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct mfd_cell intel_quark_mfd_cells[] = {
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun .id = MFD_GPIO_BAR,
101*4882a593Smuzhiyun .name = "gpio-dwapb",
102*4882a593Smuzhiyun .acpi_match = &intel_quark_acpi_match_gpio,
103*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(intel_quark_gpio_res),
104*4882a593Smuzhiyun .resources = intel_quark_gpio_res,
105*4882a593Smuzhiyun .ignore_resource_conflicts = true,
106*4882a593Smuzhiyun },
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun .id = MFD_I2C_BAR,
109*4882a593Smuzhiyun .name = "i2c_designware",
110*4882a593Smuzhiyun .acpi_match = &intel_quark_acpi_match_i2c,
111*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(intel_quark_i2c_res),
112*4882a593Smuzhiyun .resources = intel_quark_i2c_res,
113*4882a593Smuzhiyun .ignore_resource_conflicts = true,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const struct pci_device_id intel_quark_mfd_ids[] = {
118*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0934), },
119*4882a593Smuzhiyun {},
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, intel_quark_mfd_ids);
122*4882a593Smuzhiyun
intel_quark_register_i2c_clk(struct device * dev)123*4882a593Smuzhiyun static int intel_quark_register_i2c_clk(struct device *dev)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct intel_quark_mfd *quark_mfd = dev_get_drvdata(dev);
126*4882a593Smuzhiyun struct clk *i2c_clk;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun i2c_clk = clk_register_fixed_rate(dev,
129*4882a593Smuzhiyun INTEL_QUARK_I2C_CONTROLLER_CLK, NULL,
130*4882a593Smuzhiyun 0, INTEL_QUARK_I2C_CLK_HZ);
131*4882a593Smuzhiyun if (IS_ERR(i2c_clk))
132*4882a593Smuzhiyun return PTR_ERR(i2c_clk);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun quark_mfd->i2c_clk = i2c_clk;
135*4882a593Smuzhiyun quark_mfd->i2c_clk_lookup = clkdev_create(i2c_clk, NULL,
136*4882a593Smuzhiyun INTEL_QUARK_I2C_CONTROLLER_CLK);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (!quark_mfd->i2c_clk_lookup) {
139*4882a593Smuzhiyun clk_unregister(quark_mfd->i2c_clk);
140*4882a593Smuzhiyun dev_err(dev, "Fixed clk register failed\n");
141*4882a593Smuzhiyun return -ENOMEM;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
intel_quark_unregister_i2c_clk(struct device * dev)147*4882a593Smuzhiyun static void intel_quark_unregister_i2c_clk(struct device *dev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct intel_quark_mfd *quark_mfd = dev_get_drvdata(dev);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun if (!quark_mfd->i2c_clk_lookup)
152*4882a593Smuzhiyun return;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun clkdev_drop(quark_mfd->i2c_clk_lookup);
155*4882a593Smuzhiyun clk_unregister(quark_mfd->i2c_clk);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
intel_quark_i2c_setup(struct pci_dev * pdev,struct mfd_cell * cell)158*4882a593Smuzhiyun static int intel_quark_i2c_setup(struct pci_dev *pdev, struct mfd_cell *cell)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun const struct dmi_system_id *dmi_id;
161*4882a593Smuzhiyun struct dw_i2c_platform_data *pdata;
162*4882a593Smuzhiyun struct resource *res = (struct resource *)cell->resources;
163*4882a593Smuzhiyun struct device *dev = &pdev->dev;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun res[INTEL_QUARK_IORES_MEM].start =
166*4882a593Smuzhiyun pci_resource_start(pdev, MFD_I2C_BAR);
167*4882a593Smuzhiyun res[INTEL_QUARK_IORES_MEM].end =
168*4882a593Smuzhiyun pci_resource_end(pdev, MFD_I2C_BAR);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun res[INTEL_QUARK_IORES_IRQ].start = pdev->irq;
171*4882a593Smuzhiyun res[INTEL_QUARK_IORES_IRQ].end = pdev->irq;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
174*4882a593Smuzhiyun if (!pdata)
175*4882a593Smuzhiyun return -ENOMEM;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* Normal mode by default */
178*4882a593Smuzhiyun pdata->i2c_scl_freq = 100000;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun dmi_id = dmi_first_match(dmi_platform_info);
181*4882a593Smuzhiyun if (dmi_id)
182*4882a593Smuzhiyun pdata->i2c_scl_freq = (uintptr_t)dmi_id->driver_data;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun cell->platform_data = pdata;
185*4882a593Smuzhiyun cell->pdata_size = sizeof(*pdata);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
intel_quark_gpio_setup(struct pci_dev * pdev,struct mfd_cell * cell)190*4882a593Smuzhiyun static int intel_quark_gpio_setup(struct pci_dev *pdev, struct mfd_cell *cell)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun struct dwapb_platform_data *pdata;
193*4882a593Smuzhiyun struct resource *res = (struct resource *)cell->resources;
194*4882a593Smuzhiyun struct device *dev = &pdev->dev;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun res[INTEL_QUARK_IORES_MEM].start =
197*4882a593Smuzhiyun pci_resource_start(pdev, MFD_GPIO_BAR);
198*4882a593Smuzhiyun res[INTEL_QUARK_IORES_MEM].end =
199*4882a593Smuzhiyun pci_resource_end(pdev, MFD_GPIO_BAR);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
202*4882a593Smuzhiyun if (!pdata)
203*4882a593Smuzhiyun return -ENOMEM;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /* For intel quark x1000, it has only one port: portA */
206*4882a593Smuzhiyun pdata->nports = INTEL_QUARK_GPIO_NPORTS;
207*4882a593Smuzhiyun pdata->properties = devm_kcalloc(dev, pdata->nports,
208*4882a593Smuzhiyun sizeof(*pdata->properties),
209*4882a593Smuzhiyun GFP_KERNEL);
210*4882a593Smuzhiyun if (!pdata->properties)
211*4882a593Smuzhiyun return -ENOMEM;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* Set the properties for portA */
214*4882a593Smuzhiyun pdata->properties->fwnode = NULL;
215*4882a593Smuzhiyun pdata->properties->idx = 0;
216*4882a593Smuzhiyun pdata->properties->ngpio = INTEL_QUARK_MFD_NGPIO;
217*4882a593Smuzhiyun pdata->properties->gpio_base = INTEL_QUARK_MFD_GPIO_BASE;
218*4882a593Smuzhiyun pdata->properties->irq[0] = pdev->irq;
219*4882a593Smuzhiyun pdata->properties->irq_shared = true;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun cell->platform_data = pdata;
222*4882a593Smuzhiyun cell->pdata_size = sizeof(*pdata);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
intel_quark_mfd_probe(struct pci_dev * pdev,const struct pci_device_id * id)227*4882a593Smuzhiyun static int intel_quark_mfd_probe(struct pci_dev *pdev,
228*4882a593Smuzhiyun const struct pci_device_id *id)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun struct intel_quark_mfd *quark_mfd;
231*4882a593Smuzhiyun int ret;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ret = pcim_enable_device(pdev);
234*4882a593Smuzhiyun if (ret)
235*4882a593Smuzhiyun return ret;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun quark_mfd = devm_kzalloc(&pdev->dev, sizeof(*quark_mfd), GFP_KERNEL);
238*4882a593Smuzhiyun if (!quark_mfd)
239*4882a593Smuzhiyun return -ENOMEM;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun quark_mfd->dev = &pdev->dev;
242*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, quark_mfd);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun ret = intel_quark_register_i2c_clk(&pdev->dev);
245*4882a593Smuzhiyun if (ret)
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun ret = intel_quark_i2c_setup(pdev, &intel_quark_mfd_cells[1]);
249*4882a593Smuzhiyun if (ret)
250*4882a593Smuzhiyun goto err_unregister_i2c_clk;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun ret = intel_quark_gpio_setup(pdev, &intel_quark_mfd_cells[0]);
253*4882a593Smuzhiyun if (ret)
254*4882a593Smuzhiyun goto err_unregister_i2c_clk;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun ret = mfd_add_devices(&pdev->dev, 0, intel_quark_mfd_cells,
257*4882a593Smuzhiyun ARRAY_SIZE(intel_quark_mfd_cells), NULL, 0,
258*4882a593Smuzhiyun NULL);
259*4882a593Smuzhiyun if (ret)
260*4882a593Smuzhiyun goto err_unregister_i2c_clk;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun return 0;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun err_unregister_i2c_clk:
265*4882a593Smuzhiyun intel_quark_unregister_i2c_clk(&pdev->dev);
266*4882a593Smuzhiyun return ret;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
intel_quark_mfd_remove(struct pci_dev * pdev)269*4882a593Smuzhiyun static void intel_quark_mfd_remove(struct pci_dev *pdev)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun intel_quark_unregister_i2c_clk(&pdev->dev);
272*4882a593Smuzhiyun mfd_remove_devices(&pdev->dev);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static struct pci_driver intel_quark_mfd_driver = {
276*4882a593Smuzhiyun .name = "intel_quark_mfd_i2c_gpio",
277*4882a593Smuzhiyun .id_table = intel_quark_mfd_ids,
278*4882a593Smuzhiyun .probe = intel_quark_mfd_probe,
279*4882a593Smuzhiyun .remove = intel_quark_mfd_remove,
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun module_pci_driver(intel_quark_mfd_driver);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
285*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel Quark MFD PCI driver for I2C & GPIO");
286*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
287