xref: /OK3568_Linux_fs/kernel/drivers/mfd/da9063-i2c.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /* I2C support for Dialog DA9063
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright 2012 Dialog Semiconductor Ltd.
5*4882a593Smuzhiyun  * Copyright 2013 Philipp Zabel, Pengutronix
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Krystian Garbaciak, Dialog Semiconductor
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/mfd/core.h>
19*4882a593Smuzhiyun #include <linux/mfd/da9063/core.h>
20*4882a593Smuzhiyun #include <linux/mfd/da9063/registers.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/of.h>
23*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun  * Raw I2C access required for just accessing chip and variant info before we
27*4882a593Smuzhiyun  * know which device is present. The info read from the device using this
28*4882a593Smuzhiyun  * approach is then used to select the correct regmap tables.
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define DA9063_REG_PAGE_SIZE		0x100
32*4882a593Smuzhiyun #define DA9063_REG_PAGED_ADDR_MASK	0xFF
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun enum da9063_page_sel_buf_fmt {
35*4882a593Smuzhiyun 	DA9063_PAGE_SEL_BUF_PAGE_REG = 0,
36*4882a593Smuzhiyun 	DA9063_PAGE_SEL_BUF_PAGE_VAL,
37*4882a593Smuzhiyun 	DA9063_PAGE_SEL_BUF_SIZE,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun enum da9063_paged_read_msgs {
41*4882a593Smuzhiyun 	DA9063_PAGED_READ_MSG_PAGE_SEL = 0,
42*4882a593Smuzhiyun 	DA9063_PAGED_READ_MSG_REG_SEL,
43*4882a593Smuzhiyun 	DA9063_PAGED_READ_MSG_DATA,
44*4882a593Smuzhiyun 	DA9063_PAGED_READ_MSG_CNT,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
da9063_i2c_blockreg_read(struct i2c_client * client,u16 addr,u8 * buf,int count)47*4882a593Smuzhiyun static int da9063_i2c_blockreg_read(struct i2c_client *client, u16 addr,
48*4882a593Smuzhiyun 				    u8 *buf, int count)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct i2c_msg xfer[DA9063_PAGED_READ_MSG_CNT];
51*4882a593Smuzhiyun 	u8 page_sel_buf[DA9063_PAGE_SEL_BUF_SIZE];
52*4882a593Smuzhiyun 	u8 page_num, paged_addr;
53*4882a593Smuzhiyun 	int ret;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/* Determine page info based on register address */
56*4882a593Smuzhiyun 	page_num = (addr / DA9063_REG_PAGE_SIZE);
57*4882a593Smuzhiyun 	if (page_num > 1) {
58*4882a593Smuzhiyun 		dev_err(&client->dev, "Invalid register address provided\n");
59*4882a593Smuzhiyun 		return -EINVAL;
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	paged_addr = (addr % DA9063_REG_PAGE_SIZE) & DA9063_REG_PAGED_ADDR_MASK;
63*4882a593Smuzhiyun 	page_sel_buf[DA9063_PAGE_SEL_BUF_PAGE_REG] = DA9063_REG_PAGE_CON;
64*4882a593Smuzhiyun 	page_sel_buf[DA9063_PAGE_SEL_BUF_PAGE_VAL] =
65*4882a593Smuzhiyun 		(page_num << DA9063_I2C_PAGE_SEL_SHIFT) & DA9063_REG_PAGE_MASK;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* Write reg address, page selection */
68*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].addr = client->addr;
69*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].flags = 0;
70*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].len = DA9063_PAGE_SEL_BUF_SIZE;
71*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].buf = page_sel_buf;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* Select register address */
74*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_REG_SEL].addr = client->addr;
75*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_REG_SEL].flags = 0;
76*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_REG_SEL].len = sizeof(paged_addr);
77*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_REG_SEL].buf = &paged_addr;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* Read data */
80*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_DATA].addr = client->addr;
81*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_DATA].flags = I2C_M_RD;
82*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_DATA].len = count;
83*4882a593Smuzhiyun 	xfer[DA9063_PAGED_READ_MSG_DATA].buf = buf;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, xfer, DA9063_PAGED_READ_MSG_CNT);
86*4882a593Smuzhiyun 	if (ret < 0) {
87*4882a593Smuzhiyun 		dev_err(&client->dev, "Paged block read failed: %d\n", ret);
88*4882a593Smuzhiyun 		return ret;
89*4882a593Smuzhiyun 	}
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	if (ret != DA9063_PAGED_READ_MSG_CNT) {
92*4882a593Smuzhiyun 		dev_err(&client->dev, "Paged block read failed to complete\n");
93*4882a593Smuzhiyun 		return -EIO;
94*4882a593Smuzhiyun 	}
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun enum {
100*4882a593Smuzhiyun 	DA9063_DEV_ID_REG = 0,
101*4882a593Smuzhiyun 	DA9063_VAR_ID_REG,
102*4882a593Smuzhiyun 	DA9063_CHIP_ID_REGS,
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
da9063_get_device_type(struct i2c_client * i2c,struct da9063 * da9063)105*4882a593Smuzhiyun static int da9063_get_device_type(struct i2c_client *i2c, struct da9063 *da9063)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	u8 buf[DA9063_CHIP_ID_REGS];
108*4882a593Smuzhiyun 	int ret;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	ret = da9063_i2c_blockreg_read(i2c, DA9063_REG_DEVICE_ID, buf,
111*4882a593Smuzhiyun 				       DA9063_CHIP_ID_REGS);
112*4882a593Smuzhiyun 	if (ret)
113*4882a593Smuzhiyun 		return ret;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	if (buf[DA9063_DEV_ID_REG] != PMIC_CHIP_ID_DA9063) {
116*4882a593Smuzhiyun 		dev_err(da9063->dev,
117*4882a593Smuzhiyun 			"Invalid chip device ID: 0x%02x\n",
118*4882a593Smuzhiyun 			buf[DA9063_DEV_ID_REG]);
119*4882a593Smuzhiyun 		return -ENODEV;
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	dev_info(da9063->dev,
123*4882a593Smuzhiyun 		 "Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n",
124*4882a593Smuzhiyun 		 buf[DA9063_DEV_ID_REG], buf[DA9063_VAR_ID_REG]);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	da9063->variant_code =
127*4882a593Smuzhiyun 		(buf[DA9063_VAR_ID_REG] & DA9063_VARIANT_ID_MRC_MASK)
128*4882a593Smuzhiyun 		>> DA9063_VARIANT_ID_MRC_SHIFT;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun  * Variant specific regmap configs
135*4882a593Smuzhiyun  */
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static const struct regmap_range da9063_ad_readable_ranges[] = {
138*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_AD_REG_SECOND_D),
139*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
140*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
141*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_AD_REG_GP_ID_19),
142*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun static const struct regmap_range da9063_ad_writeable_ranges[] = {
146*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
147*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
148*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_COUNT_S, DA9063_AD_REG_ALARM_Y),
149*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
150*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
151*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_AD_REG_MON_REG_4),
152*4882a593Smuzhiyun 	regmap_reg_range(DA9063_AD_REG_GP_ID_0, DA9063_AD_REG_GP_ID_19),
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static const struct regmap_range da9063_ad_volatile_ranges[] = {
156*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_EVENT_D),
157*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONTROL_A, DA9063_REG_CONTROL_B),
158*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONTROL_E, DA9063_REG_CONTROL_F),
159*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_BCORE2_CONT, DA9063_REG_LDO11_CONT),
160*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DVC_1, DA9063_REG_ADC_MAN),
161*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_ADC_RES_L, DA9063_AD_REG_SECOND_D),
162*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_SEQ),
163*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_EN_32K, DA9063_REG_EN_32K),
164*4882a593Smuzhiyun 	regmap_reg_range(DA9063_AD_REG_MON_REG_5, DA9063_AD_REG_MON_REG_6),
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const struct regmap_access_table da9063_ad_readable_table = {
168*4882a593Smuzhiyun 	.yes_ranges = da9063_ad_readable_ranges,
169*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_ad_readable_ranges),
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun static const struct regmap_access_table da9063_ad_writeable_table = {
173*4882a593Smuzhiyun 	.yes_ranges = da9063_ad_writeable_ranges,
174*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_ad_writeable_ranges),
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static const struct regmap_access_table da9063_ad_volatile_table = {
178*4882a593Smuzhiyun 	.yes_ranges = da9063_ad_volatile_ranges,
179*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_ad_volatile_ranges),
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static const struct regmap_range da9063_bb_readable_ranges[] = {
183*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_BB_REG_SECOND_D),
184*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
185*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
186*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_19),
187*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const struct regmap_range da9063_bb_writeable_ranges[] = {
191*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
192*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
193*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_COUNT_S, DA9063_BB_REG_ALARM_Y),
194*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
195*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
196*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
197*4882a593Smuzhiyun 	regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_19),
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static const struct regmap_range da9063_bb_da_volatile_ranges[] = {
201*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_EVENT_D),
202*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONTROL_A, DA9063_REG_CONTROL_B),
203*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONTROL_E, DA9063_REG_CONTROL_F),
204*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_BCORE2_CONT, DA9063_REG_LDO11_CONT),
205*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DVC_1, DA9063_REG_ADC_MAN),
206*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_ADC_RES_L, DA9063_BB_REG_SECOND_D),
207*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_SEQ),
208*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_EN_32K, DA9063_REG_EN_32K),
209*4882a593Smuzhiyun 	regmap_reg_range(DA9063_BB_REG_MON_REG_5, DA9063_BB_REG_MON_REG_6),
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun static const struct regmap_access_table da9063_bb_readable_table = {
213*4882a593Smuzhiyun 	.yes_ranges = da9063_bb_readable_ranges,
214*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_bb_readable_ranges),
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun static const struct regmap_access_table da9063_bb_writeable_table = {
218*4882a593Smuzhiyun 	.yes_ranges = da9063_bb_writeable_ranges,
219*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_bb_writeable_ranges),
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun static const struct regmap_access_table da9063_bb_da_volatile_table = {
223*4882a593Smuzhiyun 	.yes_ranges = da9063_bb_da_volatile_ranges,
224*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_bb_da_volatile_ranges),
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static const struct regmap_range da9063l_bb_readable_ranges[] = {
228*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_MON_A10_RES),
229*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
230*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
231*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_19),
232*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const struct regmap_range da9063l_bb_writeable_ranges[] = {
236*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
237*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
238*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
239*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
240*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
241*4882a593Smuzhiyun 	regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_19),
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun static const struct regmap_range da9063l_bb_da_volatile_ranges[] = {
245*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_EVENT_D),
246*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONTROL_A, DA9063_REG_CONTROL_B),
247*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONTROL_E, DA9063_REG_CONTROL_F),
248*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_BCORE2_CONT, DA9063_REG_LDO11_CONT),
249*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DVC_1, DA9063_REG_ADC_MAN),
250*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_ADC_RES_L, DA9063_REG_MON_A10_RES),
251*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_SEQ),
252*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_EN_32K, DA9063_REG_EN_32K),
253*4882a593Smuzhiyun 	regmap_reg_range(DA9063_BB_REG_MON_REG_5, DA9063_BB_REG_MON_REG_6),
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun static const struct regmap_access_table da9063l_bb_readable_table = {
257*4882a593Smuzhiyun 	.yes_ranges = da9063l_bb_readable_ranges,
258*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063l_bb_readable_ranges),
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun static const struct regmap_access_table da9063l_bb_writeable_table = {
262*4882a593Smuzhiyun 	.yes_ranges = da9063l_bb_writeable_ranges,
263*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063l_bb_writeable_ranges),
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static const struct regmap_access_table da9063l_bb_da_volatile_table = {
267*4882a593Smuzhiyun 	.yes_ranges = da9063l_bb_da_volatile_ranges,
268*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063l_bb_da_volatile_ranges),
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun static const struct regmap_range da9063_da_readable_ranges[] = {
272*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_BB_REG_SECOND_D),
273*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
274*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
275*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_11),
276*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun static const struct regmap_range da9063_da_writeable_ranges[] = {
280*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
281*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
282*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_COUNT_S, DA9063_BB_REG_ALARM_Y),
283*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
284*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
285*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
286*4882a593Smuzhiyun 	regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_11),
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static const struct regmap_access_table da9063_da_readable_table = {
290*4882a593Smuzhiyun 	.yes_ranges = da9063_da_readable_ranges,
291*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_da_readable_ranges),
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun static const struct regmap_access_table da9063_da_writeable_table = {
295*4882a593Smuzhiyun 	.yes_ranges = da9063_da_writeable_ranges,
296*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063_da_writeable_ranges),
297*4882a593Smuzhiyun };
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun static const struct regmap_range da9063l_da_readable_ranges[] = {
300*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_MON_A10_RES),
301*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
302*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
303*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_11),
304*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun static const struct regmap_range da9063l_da_writeable_ranges[] = {
308*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
309*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
310*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
311*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
312*4882a593Smuzhiyun 	regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
313*4882a593Smuzhiyun 	regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_11),
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun static const struct regmap_access_table da9063l_da_readable_table = {
317*4882a593Smuzhiyun 	.yes_ranges = da9063l_da_readable_ranges,
318*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063l_da_readable_ranges),
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun static const struct regmap_access_table da9063l_da_writeable_table = {
322*4882a593Smuzhiyun 	.yes_ranges = da9063l_da_writeable_ranges,
323*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(da9063l_da_writeable_ranges),
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun static const struct regmap_range_cfg da9063_range_cfg[] = {
327*4882a593Smuzhiyun 	{
328*4882a593Smuzhiyun 		.range_min = DA9063_REG_PAGE_CON,
329*4882a593Smuzhiyun 		.range_max = DA9063_REG_CONFIG_ID,
330*4882a593Smuzhiyun 		.selector_reg = DA9063_REG_PAGE_CON,
331*4882a593Smuzhiyun 		.selector_mask = 1 << DA9063_I2C_PAGE_SEL_SHIFT,
332*4882a593Smuzhiyun 		.selector_shift = DA9063_I2C_PAGE_SEL_SHIFT,
333*4882a593Smuzhiyun 		.window_start = 0,
334*4882a593Smuzhiyun 		.window_len = 256,
335*4882a593Smuzhiyun 	}
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun static struct regmap_config da9063_regmap_config = {
339*4882a593Smuzhiyun 	.reg_bits = 8,
340*4882a593Smuzhiyun 	.val_bits = 8,
341*4882a593Smuzhiyun 	.ranges = da9063_range_cfg,
342*4882a593Smuzhiyun 	.num_ranges = ARRAY_SIZE(da9063_range_cfg),
343*4882a593Smuzhiyun 	.max_register = DA9063_REG_CONFIG_ID,
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun static const struct of_device_id da9063_dt_ids[] = {
349*4882a593Smuzhiyun 	{ .compatible = "dlg,da9063", },
350*4882a593Smuzhiyun 	{ .compatible = "dlg,da9063l", },
351*4882a593Smuzhiyun 	{ }
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, da9063_dt_ids);
da9063_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)354*4882a593Smuzhiyun static int da9063_i2c_probe(struct i2c_client *i2c,
355*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun 	struct da9063 *da9063;
358*4882a593Smuzhiyun 	int ret;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	da9063 = devm_kzalloc(&i2c->dev, sizeof(struct da9063), GFP_KERNEL);
361*4882a593Smuzhiyun 	if (da9063 == NULL)
362*4882a593Smuzhiyun 		return -ENOMEM;
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, da9063);
365*4882a593Smuzhiyun 	da9063->dev = &i2c->dev;
366*4882a593Smuzhiyun 	da9063->chip_irq = i2c->irq;
367*4882a593Smuzhiyun 	da9063->type = id->driver_data;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	ret = da9063_get_device_type(i2c, da9063);
370*4882a593Smuzhiyun 	if (ret)
371*4882a593Smuzhiyun 		return ret;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	switch (da9063->type) {
374*4882a593Smuzhiyun 	case PMIC_TYPE_DA9063:
375*4882a593Smuzhiyun 		switch (da9063->variant_code) {
376*4882a593Smuzhiyun 		case PMIC_DA9063_AD:
377*4882a593Smuzhiyun 			da9063_regmap_config.rd_table =
378*4882a593Smuzhiyun 				&da9063_ad_readable_table;
379*4882a593Smuzhiyun 			da9063_regmap_config.wr_table =
380*4882a593Smuzhiyun 				&da9063_ad_writeable_table;
381*4882a593Smuzhiyun 			da9063_regmap_config.volatile_table =
382*4882a593Smuzhiyun 				&da9063_ad_volatile_table;
383*4882a593Smuzhiyun 			break;
384*4882a593Smuzhiyun 		case PMIC_DA9063_BB:
385*4882a593Smuzhiyun 		case PMIC_DA9063_CA:
386*4882a593Smuzhiyun 			da9063_regmap_config.rd_table =
387*4882a593Smuzhiyun 				&da9063_bb_readable_table;
388*4882a593Smuzhiyun 			da9063_regmap_config.wr_table =
389*4882a593Smuzhiyun 				&da9063_bb_writeable_table;
390*4882a593Smuzhiyun 			da9063_regmap_config.volatile_table =
391*4882a593Smuzhiyun 				&da9063_bb_da_volatile_table;
392*4882a593Smuzhiyun 			break;
393*4882a593Smuzhiyun 		case PMIC_DA9063_DA:
394*4882a593Smuzhiyun 			da9063_regmap_config.rd_table =
395*4882a593Smuzhiyun 				&da9063_da_readable_table;
396*4882a593Smuzhiyun 			da9063_regmap_config.wr_table =
397*4882a593Smuzhiyun 				&da9063_da_writeable_table;
398*4882a593Smuzhiyun 			da9063_regmap_config.volatile_table =
399*4882a593Smuzhiyun 				&da9063_bb_da_volatile_table;
400*4882a593Smuzhiyun 			break;
401*4882a593Smuzhiyun 		default:
402*4882a593Smuzhiyun 			dev_err(da9063->dev,
403*4882a593Smuzhiyun 				"Chip variant not supported for DA9063\n");
404*4882a593Smuzhiyun 			return -ENODEV;
405*4882a593Smuzhiyun 		}
406*4882a593Smuzhiyun 		break;
407*4882a593Smuzhiyun 	case PMIC_TYPE_DA9063L:
408*4882a593Smuzhiyun 		switch (da9063->variant_code) {
409*4882a593Smuzhiyun 		case PMIC_DA9063_BB:
410*4882a593Smuzhiyun 		case PMIC_DA9063_CA:
411*4882a593Smuzhiyun 			da9063_regmap_config.rd_table =
412*4882a593Smuzhiyun 				&da9063l_bb_readable_table;
413*4882a593Smuzhiyun 			da9063_regmap_config.wr_table =
414*4882a593Smuzhiyun 				&da9063l_bb_writeable_table;
415*4882a593Smuzhiyun 			da9063_regmap_config.volatile_table =
416*4882a593Smuzhiyun 				&da9063l_bb_da_volatile_table;
417*4882a593Smuzhiyun 			break;
418*4882a593Smuzhiyun 		case PMIC_DA9063_DA:
419*4882a593Smuzhiyun 			da9063_regmap_config.rd_table =
420*4882a593Smuzhiyun 				&da9063l_da_readable_table;
421*4882a593Smuzhiyun 			da9063_regmap_config.wr_table =
422*4882a593Smuzhiyun 				&da9063l_da_writeable_table;
423*4882a593Smuzhiyun 			da9063_regmap_config.volatile_table =
424*4882a593Smuzhiyun 				&da9063l_bb_da_volatile_table;
425*4882a593Smuzhiyun 			break;
426*4882a593Smuzhiyun 		default:
427*4882a593Smuzhiyun 			dev_err(da9063->dev,
428*4882a593Smuzhiyun 				"Chip variant not supported for DA9063L\n");
429*4882a593Smuzhiyun 			return -ENODEV;
430*4882a593Smuzhiyun 		}
431*4882a593Smuzhiyun 		break;
432*4882a593Smuzhiyun 	default:
433*4882a593Smuzhiyun 		dev_err(da9063->dev, "Chip type not supported\n");
434*4882a593Smuzhiyun 		return -ENODEV;
435*4882a593Smuzhiyun 	}
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	da9063->regmap = devm_regmap_init_i2c(i2c, &da9063_regmap_config);
438*4882a593Smuzhiyun 	if (IS_ERR(da9063->regmap)) {
439*4882a593Smuzhiyun 		ret = PTR_ERR(da9063->regmap);
440*4882a593Smuzhiyun 		dev_err(da9063->dev, "Failed to allocate register map: %d\n",
441*4882a593Smuzhiyun 			ret);
442*4882a593Smuzhiyun 		return ret;
443*4882a593Smuzhiyun 	}
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	/* If SMBus is not available and only I2C is possible, enter I2C mode */
446*4882a593Smuzhiyun 	if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
447*4882a593Smuzhiyun 		ret = regmap_clear_bits(da9063->regmap, DA9063_REG_CONFIG_J,
448*4882a593Smuzhiyun 					DA9063_TWOWIRE_TO);
449*4882a593Smuzhiyun 		if (ret < 0) {
450*4882a593Smuzhiyun 			dev_err(da9063->dev, "Failed to set Two-Wire Bus Mode.\n");
451*4882a593Smuzhiyun 			return -EIO;
452*4882a593Smuzhiyun 		}
453*4882a593Smuzhiyun 	}
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	return da9063_device_init(da9063, i2c->irq);
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun static const struct i2c_device_id da9063_i2c_id[] = {
459*4882a593Smuzhiyun 	{ "da9063", PMIC_TYPE_DA9063 },
460*4882a593Smuzhiyun 	{ "da9063l", PMIC_TYPE_DA9063L },
461*4882a593Smuzhiyun 	{},
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, da9063_i2c_id);
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun static struct i2c_driver da9063_i2c_driver = {
466*4882a593Smuzhiyun 	.driver = {
467*4882a593Smuzhiyun 		.name = "da9063",
468*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(da9063_dt_ids),
469*4882a593Smuzhiyun 	},
470*4882a593Smuzhiyun 	.probe    = da9063_i2c_probe,
471*4882a593Smuzhiyun 	.id_table = da9063_i2c_id,
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun module_i2c_driver(da9063_i2c_driver);
475