1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ROHM BD9571MWV-M MFD driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License version 2 as
8*4882a593Smuzhiyun * published by the Free Software Foundation.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11*4882a593Smuzhiyun * kind, whether expressed or implied; without even the implied warranty
12*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13*4882a593Smuzhiyun * GNU General Public License version 2 for more details.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * Based on the TPS65086 driver
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/mfd/core.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/mfd/bd9571mwv.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static const struct mfd_cell bd9571mwv_cells[] = {
26*4882a593Smuzhiyun { .name = "bd9571mwv-regulator", },
27*4882a593Smuzhiyun { .name = "bd9571mwv-gpio", },
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static const struct regmap_range bd9571mwv_readable_yes_ranges[] = {
31*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_VENDOR_CODE, BD9571MWV_PRODUCT_REVISION),
32*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
33*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_AVS_SET_MONI, BD9571MWV_AVS_DVFS_VID(3)),
34*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_VD18_VID, BD9571MWV_VD33_VID),
35*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_DVFS_VINIT, BD9571MWV_DVFS_VINIT),
36*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_DVFS_SETVMAX, BD9571MWV_DVFS_MONIVDAC),
37*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
38*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INTMASK),
39*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const struct regmap_access_table bd9571mwv_readable_table = {
43*4882a593Smuzhiyun .yes_ranges = bd9571mwv_readable_yes_ranges,
44*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(bd9571mwv_readable_yes_ranges),
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct regmap_range bd9571mwv_writable_yes_ranges[] = {
48*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
49*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_AVS_VD09_VID(0), BD9571MWV_AVS_VD09_VID(3)),
50*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_SETVID),
51*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_GPIO_DIR, BD9571MWV_GPIO_OUT),
52*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_GPIO_INT_SET, BD9571MWV_GPIO_INTMASK),
53*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static const struct regmap_access_table bd9571mwv_writable_table = {
57*4882a593Smuzhiyun .yes_ranges = bd9571mwv_writable_yes_ranges,
58*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(bd9571mwv_writable_yes_ranges),
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct regmap_range bd9571mwv_volatile_yes_ranges[] = {
62*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_DVFS_MONIVDAC, BD9571MWV_DVFS_MONIVDAC),
63*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
64*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INT),
65*4882a593Smuzhiyun regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTREQ),
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct regmap_access_table bd9571mwv_volatile_table = {
69*4882a593Smuzhiyun .yes_ranges = bd9571mwv_volatile_yes_ranges,
70*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(bd9571mwv_volatile_yes_ranges),
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const struct regmap_config bd9571mwv_regmap_config = {
74*4882a593Smuzhiyun .reg_bits = 8,
75*4882a593Smuzhiyun .val_bits = 8,
76*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
77*4882a593Smuzhiyun .rd_table = &bd9571mwv_readable_table,
78*4882a593Smuzhiyun .wr_table = &bd9571mwv_writable_table,
79*4882a593Smuzhiyun .volatile_table = &bd9571mwv_volatile_table,
80*4882a593Smuzhiyun .max_register = 0xff,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct regmap_irq bd9571mwv_irqs[] = {
84*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_MD1, 0,
85*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_MD1_INT),
86*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E1, 0,
87*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_MD2_E1_INT),
88*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E2, 0,
89*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_MD2_E2_INT),
90*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_PROT_ERR, 0,
91*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_PROT_ERR_INT),
92*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_GP, 0,
93*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_GP_INT),
94*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_128H_OF, 0,
95*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_128H_OF_INT),
96*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_WDT_OF, 0,
97*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_WDT_OF_INT),
98*4882a593Smuzhiyun REGMAP_IRQ_REG(BD9571MWV_IRQ_BKUP_TRG, 0,
99*4882a593Smuzhiyun BD9571MWV_INT_INTREQ_BKUP_TRG_INT),
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static struct regmap_irq_chip bd9571mwv_irq_chip = {
103*4882a593Smuzhiyun .name = "bd9571mwv",
104*4882a593Smuzhiyun .status_base = BD9571MWV_INT_INTREQ,
105*4882a593Smuzhiyun .mask_base = BD9571MWV_INT_INTMASK,
106*4882a593Smuzhiyun .ack_base = BD9571MWV_INT_INTREQ,
107*4882a593Smuzhiyun .init_ack_masked = true,
108*4882a593Smuzhiyun .num_regs = 1,
109*4882a593Smuzhiyun .irqs = bd9571mwv_irqs,
110*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(bd9571mwv_irqs),
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
bd9571mwv_identify(struct bd9571mwv * bd)113*4882a593Smuzhiyun static int bd9571mwv_identify(struct bd9571mwv *bd)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct device *dev = bd->dev;
116*4882a593Smuzhiyun unsigned int value;
117*4882a593Smuzhiyun int ret;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ret = regmap_read(bd->regmap, BD9571MWV_VENDOR_CODE, &value);
120*4882a593Smuzhiyun if (ret) {
121*4882a593Smuzhiyun dev_err(dev, "Failed to read vendor code register (ret=%i)\n",
122*4882a593Smuzhiyun ret);
123*4882a593Smuzhiyun return ret;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (value != BD9571MWV_VENDOR_CODE_VAL) {
127*4882a593Smuzhiyun dev_err(dev, "Invalid vendor code ID %02x (expected %02x)\n",
128*4882a593Smuzhiyun value, BD9571MWV_VENDOR_CODE_VAL);
129*4882a593Smuzhiyun return -EINVAL;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun ret = regmap_read(bd->regmap, BD9571MWV_PRODUCT_CODE, &value);
133*4882a593Smuzhiyun if (ret) {
134*4882a593Smuzhiyun dev_err(dev, "Failed to read product code register (ret=%i)\n",
135*4882a593Smuzhiyun ret);
136*4882a593Smuzhiyun return ret;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (value != BD9571MWV_PRODUCT_CODE_VAL) {
140*4882a593Smuzhiyun dev_err(dev, "Invalid product code ID %02x (expected %02x)\n",
141*4882a593Smuzhiyun value, BD9571MWV_PRODUCT_CODE_VAL);
142*4882a593Smuzhiyun return -EINVAL;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ret = regmap_read(bd->regmap, BD9571MWV_PRODUCT_REVISION, &value);
146*4882a593Smuzhiyun if (ret) {
147*4882a593Smuzhiyun dev_err(dev, "Failed to read revision register (ret=%i)\n",
148*4882a593Smuzhiyun ret);
149*4882a593Smuzhiyun return ret;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun dev_info(dev, "Device: BD9571MWV rev. %d\n", value & 0xff);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
bd9571mwv_probe(struct i2c_client * client,const struct i2c_device_id * ids)157*4882a593Smuzhiyun static int bd9571mwv_probe(struct i2c_client *client,
158*4882a593Smuzhiyun const struct i2c_device_id *ids)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct bd9571mwv *bd;
161*4882a593Smuzhiyun int ret;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun bd = devm_kzalloc(&client->dev, sizeof(*bd), GFP_KERNEL);
164*4882a593Smuzhiyun if (!bd)
165*4882a593Smuzhiyun return -ENOMEM;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun i2c_set_clientdata(client, bd);
168*4882a593Smuzhiyun bd->dev = &client->dev;
169*4882a593Smuzhiyun bd->irq = client->irq;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun bd->regmap = devm_regmap_init_i2c(client, &bd9571mwv_regmap_config);
172*4882a593Smuzhiyun if (IS_ERR(bd->regmap)) {
173*4882a593Smuzhiyun dev_err(bd->dev, "Failed to initialize register map\n");
174*4882a593Smuzhiyun return PTR_ERR(bd->regmap);
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ret = bd9571mwv_identify(bd);
178*4882a593Smuzhiyun if (ret)
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun ret = regmap_add_irq_chip(bd->regmap, bd->irq, IRQF_ONESHOT, 0,
182*4882a593Smuzhiyun &bd9571mwv_irq_chip, &bd->irq_data);
183*4882a593Smuzhiyun if (ret) {
184*4882a593Smuzhiyun dev_err(bd->dev, "Failed to register IRQ chip\n");
185*4882a593Smuzhiyun return ret;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun ret = devm_mfd_add_devices(bd->dev, PLATFORM_DEVID_AUTO,
189*4882a593Smuzhiyun bd9571mwv_cells, ARRAY_SIZE(bd9571mwv_cells),
190*4882a593Smuzhiyun NULL, 0, regmap_irq_get_domain(bd->irq_data));
191*4882a593Smuzhiyun if (ret) {
192*4882a593Smuzhiyun regmap_del_irq_chip(bd->irq, bd->irq_data);
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
bd9571mwv_remove(struct i2c_client * client)199*4882a593Smuzhiyun static int bd9571mwv_remove(struct i2c_client *client)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct bd9571mwv *bd = i2c_get_clientdata(client);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun regmap_del_irq_chip(bd->irq, bd->irq_data);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun static const struct of_device_id bd9571mwv_of_match_table[] = {
209*4882a593Smuzhiyun { .compatible = "rohm,bd9571mwv", },
210*4882a593Smuzhiyun { /* sentinel */ }
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bd9571mwv_of_match_table);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun static const struct i2c_device_id bd9571mwv_id_table[] = {
215*4882a593Smuzhiyun { "bd9571mwv", 0 },
216*4882a593Smuzhiyun { /* sentinel */ }
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, bd9571mwv_id_table);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun static struct i2c_driver bd9571mwv_driver = {
221*4882a593Smuzhiyun .driver = {
222*4882a593Smuzhiyun .name = "bd9571mwv",
223*4882a593Smuzhiyun .of_match_table = bd9571mwv_of_match_table,
224*4882a593Smuzhiyun },
225*4882a593Smuzhiyun .probe = bd9571mwv_probe,
226*4882a593Smuzhiyun .remove = bd9571mwv_remove,
227*4882a593Smuzhiyun .id_table = bd9571mwv_id_table,
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun module_i2c_driver(bd9571mwv_driver);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun MODULE_AUTHOR("Marek Vasut <marek.vasut+renesas@gmail.com>");
232*4882a593Smuzhiyun MODULE_DESCRIPTION("BD9571MWV PMIC Driver");
233*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
234