xref: /OK3568_Linux_fs/kernel/drivers/mfd/axp20x.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * MFD core driver for the X-Powers' Power Management ICs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
6*4882a593Smuzhiyun  * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
7*4882a593Smuzhiyun  * as well as configurable GPIOs.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file contains the interface independent core functions.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Copyright (C) 2014 Carlo Caione
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Author: Carlo Caione <carlo@caione.org>
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/acpi.h>
17*4882a593Smuzhiyun #include <linux/bitops.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/err.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/kernel.h>
22*4882a593Smuzhiyun #include <linux/mfd/axp20x.h>
23*4882a593Smuzhiyun #include <linux/mfd/core.h>
24*4882a593Smuzhiyun #include <linux/module.h>
25*4882a593Smuzhiyun #include <linux/of_device.h>
26*4882a593Smuzhiyun #include <linux/pm_runtime.h>
27*4882a593Smuzhiyun #include <linux/regmap.h>
28*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define AXP20X_OFF	BIT(7)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE	0
33*4882a593Smuzhiyun #define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE	BIT(4)
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static const char * const axp20x_model_names[] = {
36*4882a593Smuzhiyun 	"AXP152",
37*4882a593Smuzhiyun 	"AXP202",
38*4882a593Smuzhiyun 	"AXP209",
39*4882a593Smuzhiyun 	"AXP221",
40*4882a593Smuzhiyun 	"AXP223",
41*4882a593Smuzhiyun 	"AXP288",
42*4882a593Smuzhiyun 	"AXP803",
43*4882a593Smuzhiyun 	"AXP806",
44*4882a593Smuzhiyun 	"AXP809",
45*4882a593Smuzhiyun 	"AXP813",
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static const struct regmap_range axp152_writeable_ranges[] = {
49*4882a593Smuzhiyun 	regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
50*4882a593Smuzhiyun 	regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static const struct regmap_range axp152_volatile_ranges[] = {
54*4882a593Smuzhiyun 	regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
55*4882a593Smuzhiyun 	regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
56*4882a593Smuzhiyun 	regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static const struct regmap_access_table axp152_writeable_table = {
60*4882a593Smuzhiyun 	.yes_ranges	= axp152_writeable_ranges,
61*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp152_writeable_ranges),
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun static const struct regmap_access_table axp152_volatile_table = {
65*4882a593Smuzhiyun 	.yes_ranges	= axp152_volatile_ranges,
66*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp152_volatile_ranges),
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun static const struct regmap_range axp20x_writeable_ranges[] = {
70*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
71*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
72*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
73*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static const struct regmap_range axp20x_volatile_ranges[] = {
77*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
78*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
79*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
80*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
81*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
82*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun static const struct regmap_access_table axp20x_writeable_table = {
86*4882a593Smuzhiyun 	.yes_ranges	= axp20x_writeable_ranges,
87*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp20x_writeable_ranges),
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static const struct regmap_access_table axp20x_volatile_table = {
91*4882a593Smuzhiyun 	.yes_ranges	= axp20x_volatile_ranges,
92*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp20x_volatile_ranges),
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /* AXP22x ranges are shared with the AXP809, as they cover the same range */
96*4882a593Smuzhiyun static const struct regmap_range axp22x_writeable_ranges[] = {
97*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
98*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
99*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static const struct regmap_range axp22x_volatile_ranges[] = {
103*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
104*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
105*4882a593Smuzhiyun 	regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
106*4882a593Smuzhiyun 	regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
107*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const struct regmap_access_table axp22x_writeable_table = {
111*4882a593Smuzhiyun 	.yes_ranges	= axp22x_writeable_ranges,
112*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp22x_writeable_ranges),
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static const struct regmap_access_table axp22x_volatile_table = {
116*4882a593Smuzhiyun 	.yes_ranges	= axp22x_volatile_ranges,
117*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp22x_volatile_ranges),
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* AXP288 ranges are shared with the AXP803, as they cover the same range */
121*4882a593Smuzhiyun static const struct regmap_range axp288_writeable_ranges[] = {
122*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
123*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static const struct regmap_range axp288_volatile_ranges[] = {
127*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
128*4882a593Smuzhiyun 	regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT),
129*4882a593Smuzhiyun 	regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
130*4882a593Smuzhiyun 	regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
131*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
132*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
133*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
134*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE),
135*4882a593Smuzhiyun 	regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
136*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun static const struct regmap_access_table axp288_writeable_table = {
140*4882a593Smuzhiyun 	.yes_ranges	= axp288_writeable_ranges,
141*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp288_writeable_ranges),
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static const struct regmap_access_table axp288_volatile_table = {
145*4882a593Smuzhiyun 	.yes_ranges	= axp288_volatile_ranges,
146*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp288_volatile_ranges),
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun static const struct regmap_range axp806_writeable_ranges[] = {
150*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
151*4882a593Smuzhiyun 	regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
152*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
153*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
154*4882a593Smuzhiyun 	regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static const struct regmap_range axp806_volatile_ranges[] = {
158*4882a593Smuzhiyun 	regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static const struct regmap_access_table axp806_writeable_table = {
162*4882a593Smuzhiyun 	.yes_ranges	= axp806_writeable_ranges,
163*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp806_writeable_ranges),
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun static const struct regmap_access_table axp806_volatile_table = {
167*4882a593Smuzhiyun 	.yes_ranges	= axp806_volatile_ranges,
168*4882a593Smuzhiyun 	.n_yes_ranges	= ARRAY_SIZE(axp806_volatile_ranges),
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun static const struct resource axp152_pek_resources[] = {
172*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
173*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun static const struct resource axp20x_ac_power_supply_resources[] = {
177*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
178*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
179*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static const struct resource axp20x_pek_resources[] = {
183*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
184*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun static const struct resource axp20x_usb_power_supply_resources[] = {
188*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
189*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
190*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
191*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun static const struct resource axp22x_usb_power_supply_resources[] = {
195*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
196*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun /* AXP803 and AXP813/AXP818 share the same interrupts */
200*4882a593Smuzhiyun static const struct resource axp803_usb_power_supply_resources[] = {
201*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
202*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct resource axp22x_pek_resources[] = {
206*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
207*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static const struct resource axp288_power_button_resources[] = {
211*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"),
212*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"),
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun static const struct resource axp288_fuel_gauge_resources[] = {
216*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_QWBTU),
217*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_WBTU),
218*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_QWBTO),
219*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_WBTO),
220*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_WL2),
221*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_WL1),
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static const struct resource axp803_pek_resources[] = {
225*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
226*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun static const struct resource axp806_pek_resources[] = {
230*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_RISE, "PEK_DBR"),
231*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_FALL, "PEK_DBF"),
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun static const struct resource axp809_pek_resources[] = {
235*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
236*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun static const struct regmap_config axp152_regmap_config = {
240*4882a593Smuzhiyun 	.reg_bits	= 8,
241*4882a593Smuzhiyun 	.val_bits	= 8,
242*4882a593Smuzhiyun 	.wr_table	= &axp152_writeable_table,
243*4882a593Smuzhiyun 	.volatile_table	= &axp152_volatile_table,
244*4882a593Smuzhiyun 	.max_register	= AXP152_PWM1_DUTY_CYCLE,
245*4882a593Smuzhiyun 	.cache_type	= REGCACHE_RBTREE,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun static const struct regmap_config axp20x_regmap_config = {
249*4882a593Smuzhiyun 	.reg_bits	= 8,
250*4882a593Smuzhiyun 	.val_bits	= 8,
251*4882a593Smuzhiyun 	.wr_table	= &axp20x_writeable_table,
252*4882a593Smuzhiyun 	.volatile_table	= &axp20x_volatile_table,
253*4882a593Smuzhiyun 	.max_register	= AXP20X_OCV(AXP20X_OCV_MAX),
254*4882a593Smuzhiyun 	.cache_type	= REGCACHE_RBTREE,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static const struct regmap_config axp22x_regmap_config = {
258*4882a593Smuzhiyun 	.reg_bits	= 8,
259*4882a593Smuzhiyun 	.val_bits	= 8,
260*4882a593Smuzhiyun 	.wr_table	= &axp22x_writeable_table,
261*4882a593Smuzhiyun 	.volatile_table	= &axp22x_volatile_table,
262*4882a593Smuzhiyun 	.max_register	= AXP22X_BATLOW_THRES1,
263*4882a593Smuzhiyun 	.cache_type	= REGCACHE_RBTREE,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static const struct regmap_config axp288_regmap_config = {
267*4882a593Smuzhiyun 	.reg_bits	= 8,
268*4882a593Smuzhiyun 	.val_bits	= 8,
269*4882a593Smuzhiyun 	.wr_table	= &axp288_writeable_table,
270*4882a593Smuzhiyun 	.volatile_table	= &axp288_volatile_table,
271*4882a593Smuzhiyun 	.max_register	= AXP288_FG_TUNE5,
272*4882a593Smuzhiyun 	.cache_type	= REGCACHE_RBTREE,
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun static const struct regmap_config axp806_regmap_config = {
276*4882a593Smuzhiyun 	.reg_bits	= 8,
277*4882a593Smuzhiyun 	.val_bits	= 8,
278*4882a593Smuzhiyun 	.wr_table	= &axp806_writeable_table,
279*4882a593Smuzhiyun 	.volatile_table	= &axp806_volatile_table,
280*4882a593Smuzhiyun 	.max_register	= AXP806_REG_ADDR_EXT,
281*4882a593Smuzhiyun 	.cache_type	= REGCACHE_RBTREE,
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask)			\
285*4882a593Smuzhiyun 	[_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun static const struct regmap_irq axp152_regmap_irqs[] = {
288*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT,		0, 6),
289*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL,		0, 5),
290*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT,	0, 3),
291*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL,	0, 2),
292*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW,		1, 5),
293*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW,		1, 4),
294*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW,		1, 3),
295*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW,		1, 2),
296*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, PEK_SHORT,		1, 1),
297*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, PEK_LONG,		1, 0),
298*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, TIMER,			2, 7),
299*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE,		2, 6),
300*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE,		2, 5),
301*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT,		2, 3),
302*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT,		2, 2),
303*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT,		2, 1),
304*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT,		2, 0),
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun static const struct regmap_irq axp20x_regmap_irqs[] = {
308*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V,		0, 7),
309*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN,		0, 6),
310*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL,	        0, 5),
311*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V,		0, 4),
312*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN,		0, 3),
313*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL,	        0, 2),
314*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW,		0, 1),
315*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN,		1, 7),
316*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL,	        1, 6),
317*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE,	1, 5),
318*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE,	1, 4),
319*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, CHARG,		        1, 3),
320*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, CHARG_DONE,		1, 2),
321*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH,	        1, 1),
322*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW,	        1, 0),
323*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH,	        2, 7),
324*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW,		2, 6),
325*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG,	        2, 5),
326*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG,	        2, 4),
327*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG,	        2, 3),
328*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, PEK_SHORT,		2, 1),
329*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, PEK_LONG,		2, 0),
330*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON,		3, 7),
331*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF,	        3, 6),
332*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_VALID,		3, 5),
333*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID,	        3, 4),
334*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID,	3, 3),
335*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END,	        3, 2),
336*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1,	        3, 1),
337*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2,	        3, 0),
338*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, TIMER,		        4, 7),
339*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE,	        4, 6),
340*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE,	        4, 5),
341*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT,		4, 3),
342*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT,		4, 2),
343*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT,		4, 1),
344*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT,		4, 0),
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static const struct regmap_irq axp22x_regmap_irqs[] = {
348*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V,		0, 7),
349*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN,		0, 6),
350*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL,	        0, 5),
351*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V,		0, 4),
352*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN,		0, 3),
353*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL,	        0, 2),
354*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW,		0, 1),
355*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN,		1, 7),
356*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL,	        1, 6),
357*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE,	1, 5),
358*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE,	1, 4),
359*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, CHARG,		        1, 3),
360*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, CHARG_DONE,		1, 2),
361*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH,	        1, 1),
362*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW,	        1, 0),
363*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH,	        2, 7),
364*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, PEK_SHORT,		2, 1),
365*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, PEK_LONG,		2, 0),
366*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1,	        3, 1),
367*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2,	        3, 0),
368*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, TIMER,		        4, 7),
369*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE,	        4, 6),
370*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE,	        4, 5),
371*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT,		4, 1),
372*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT,		4, 0),
373*4882a593Smuzhiyun };
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun /* some IRQs are compatible with axp20x models */
376*4882a593Smuzhiyun static const struct regmap_irq axp288_regmap_irqs[] = {
377*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, VBUS_FALL,              0, 2),
378*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, VBUS_RISE,              0, 3),
379*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, OV,                     0, 4),
380*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, FALLING_ALT,            0, 5),
381*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, RISING_ALT,             0, 6),
382*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, OV_ALT,                 0, 7),
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, DONE,                   1, 2),
385*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, CHARGING,               1, 3),
386*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, SAFE_QUIT,              1, 4),
387*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, SAFE_ENTER,             1, 5),
388*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, ABSENT,                 1, 6),
389*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, APPEND,                 1, 7),
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, QWBTU,                  2, 0),
392*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, WBTU,                   2, 1),
393*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, QWBTO,                  2, 2),
394*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, WBTO,                   2, 3),
395*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, QCBTU,                  2, 4),
396*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, CBTU,                   2, 5),
397*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, QCBTO,                  2, 6),
398*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, CBTO,                   2, 7),
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, WL2,                    3, 0),
401*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, WL1,                    3, 1),
402*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, GPADC,                  3, 2),
403*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, OT,                     3, 7),
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, GPIO0,                  4, 0),
406*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, GPIO1,                  4, 1),
407*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, POKO,                   4, 2),
408*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, POKL,                   4, 3),
409*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, POKS,                   4, 4),
410*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, POKN,                   4, 5),
411*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, POKP,                   4, 6),
412*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, TIMER,                  4, 7),
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, MV_CHNG,                5, 0),
415*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG,            5, 1),
416*4882a593Smuzhiyun };
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun static const struct regmap_irq axp803_regmap_irqs[] = {
419*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V,		0, 7),
420*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN,		0, 6),
421*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL,	        0, 5),
422*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V,		0, 4),
423*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN,		0, 3),
424*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL,	        0, 2),
425*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN,		1, 7),
426*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL,	        1, 6),
427*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE,	1, 5),
428*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE,	1, 4),
429*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, CHARG,		        1, 3),
430*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, CHARG_DONE,		1, 2),
431*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH,	2, 7),
432*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END,	2, 6),
433*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW,	2, 5),
434*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END,	2, 4),
435*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH,	2, 3),
436*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END,	2, 2),
437*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW,	2, 1),
438*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END,	2, 0),
439*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH,	        3, 7),
440*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, GPADC,		        3, 2),
441*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1,	        3, 1),
442*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2,	        3, 0),
443*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, TIMER,		        4, 7),
444*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE,	        4, 6),
445*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE,	        4, 5),
446*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, PEK_SHORT,		4, 4),
447*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, PEK_LONG,		4, 3),
448*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF,		4, 2),
449*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT,		4, 1),
450*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT,		4, 0),
451*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG,            5, 1),
452*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP803, MV_CHNG,                5, 0),
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct regmap_irq axp806_regmap_irqs[] = {
456*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1,	0, 0),
457*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2,	0, 1),
458*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW,		0, 3),
459*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW,		0, 4),
460*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW,		0, 5),
461*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW,		0, 6),
462*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW,		0, 7),
463*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, POK_LONG,		1, 0),
464*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, POK_SHORT,		1, 1),
465*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, WAKEUP,			1, 4),
466*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, POK_FALL,		1, 5),
467*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP806, POK_RISE,		1, 6),
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun static const struct regmap_irq axp809_regmap_irqs[] = {
471*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V,		0, 7),
472*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN,		0, 6),
473*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL,	        0, 5),
474*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V,		0, 4),
475*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN,		0, 3),
476*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL,	        0, 2),
477*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW,		0, 1),
478*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN,		1, 7),
479*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL,	        1, 6),
480*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE,	1, 5),
481*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE,	1, 4),
482*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, CHARG,		        1, 3),
483*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, CHARG_DONE,		1, 2),
484*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH,	2, 7),
485*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END,	2, 6),
486*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW,	2, 5),
487*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END,	2, 4),
488*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH,	2, 3),
489*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END,	2, 2),
490*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW,	2, 1),
491*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END,	2, 0),
492*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH,	        3, 7),
493*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1,	        3, 1),
494*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2,	        3, 0),
495*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, TIMER,		        4, 7),
496*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE,	        4, 6),
497*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE,	        4, 5),
498*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, PEK_SHORT,		4, 4),
499*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, PEK_LONG,		4, 3),
500*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF,		4, 2),
501*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT,		4, 1),
502*4882a593Smuzhiyun 	INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT,		4, 0),
503*4882a593Smuzhiyun };
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun static const struct regmap_irq_chip axp152_regmap_irq_chip = {
506*4882a593Smuzhiyun 	.name			= "axp152_irq_chip",
507*4882a593Smuzhiyun 	.status_base		= AXP152_IRQ1_STATE,
508*4882a593Smuzhiyun 	.ack_base		= AXP152_IRQ1_STATE,
509*4882a593Smuzhiyun 	.mask_base		= AXP152_IRQ1_EN,
510*4882a593Smuzhiyun 	.mask_invert		= true,
511*4882a593Smuzhiyun 	.init_ack_masked	= true,
512*4882a593Smuzhiyun 	.irqs			= axp152_regmap_irqs,
513*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp152_regmap_irqs),
514*4882a593Smuzhiyun 	.num_regs		= 3,
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
518*4882a593Smuzhiyun 	.name			= "axp20x_irq_chip",
519*4882a593Smuzhiyun 	.status_base		= AXP20X_IRQ1_STATE,
520*4882a593Smuzhiyun 	.ack_base		= AXP20X_IRQ1_STATE,
521*4882a593Smuzhiyun 	.mask_base		= AXP20X_IRQ1_EN,
522*4882a593Smuzhiyun 	.mask_invert		= true,
523*4882a593Smuzhiyun 	.init_ack_masked	= true,
524*4882a593Smuzhiyun 	.irqs			= axp20x_regmap_irqs,
525*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp20x_regmap_irqs),
526*4882a593Smuzhiyun 	.num_regs		= 5,
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
531*4882a593Smuzhiyun 	.name			= "axp22x_irq_chip",
532*4882a593Smuzhiyun 	.status_base		= AXP20X_IRQ1_STATE,
533*4882a593Smuzhiyun 	.ack_base		= AXP20X_IRQ1_STATE,
534*4882a593Smuzhiyun 	.mask_base		= AXP20X_IRQ1_EN,
535*4882a593Smuzhiyun 	.mask_invert		= true,
536*4882a593Smuzhiyun 	.init_ack_masked	= true,
537*4882a593Smuzhiyun 	.irqs			= axp22x_regmap_irqs,
538*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp22x_regmap_irqs),
539*4882a593Smuzhiyun 	.num_regs		= 5,
540*4882a593Smuzhiyun };
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun static const struct regmap_irq_chip axp288_regmap_irq_chip = {
543*4882a593Smuzhiyun 	.name			= "axp288_irq_chip",
544*4882a593Smuzhiyun 	.status_base		= AXP20X_IRQ1_STATE,
545*4882a593Smuzhiyun 	.ack_base		= AXP20X_IRQ1_STATE,
546*4882a593Smuzhiyun 	.mask_base		= AXP20X_IRQ1_EN,
547*4882a593Smuzhiyun 	.mask_invert		= true,
548*4882a593Smuzhiyun 	.init_ack_masked	= true,
549*4882a593Smuzhiyun 	.irqs			= axp288_regmap_irqs,
550*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp288_regmap_irqs),
551*4882a593Smuzhiyun 	.num_regs		= 6,
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun };
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun static const struct regmap_irq_chip axp803_regmap_irq_chip = {
556*4882a593Smuzhiyun 	.name			= "axp803",
557*4882a593Smuzhiyun 	.status_base		= AXP20X_IRQ1_STATE,
558*4882a593Smuzhiyun 	.ack_base		= AXP20X_IRQ1_STATE,
559*4882a593Smuzhiyun 	.mask_base		= AXP20X_IRQ1_EN,
560*4882a593Smuzhiyun 	.mask_invert		= true,
561*4882a593Smuzhiyun 	.init_ack_masked	= true,
562*4882a593Smuzhiyun 	.irqs			= axp803_regmap_irqs,
563*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp803_regmap_irqs),
564*4882a593Smuzhiyun 	.num_regs		= 6,
565*4882a593Smuzhiyun };
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun static const struct regmap_irq_chip axp806_regmap_irq_chip = {
568*4882a593Smuzhiyun 	.name			= "axp806",
569*4882a593Smuzhiyun 	.status_base		= AXP20X_IRQ1_STATE,
570*4882a593Smuzhiyun 	.ack_base		= AXP20X_IRQ1_STATE,
571*4882a593Smuzhiyun 	.mask_base		= AXP20X_IRQ1_EN,
572*4882a593Smuzhiyun 	.mask_invert		= true,
573*4882a593Smuzhiyun 	.init_ack_masked	= true,
574*4882a593Smuzhiyun 	.irqs			= axp806_regmap_irqs,
575*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp806_regmap_irqs),
576*4882a593Smuzhiyun 	.num_regs		= 2,
577*4882a593Smuzhiyun };
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun static const struct regmap_irq_chip axp809_regmap_irq_chip = {
580*4882a593Smuzhiyun 	.name			= "axp809",
581*4882a593Smuzhiyun 	.status_base		= AXP20X_IRQ1_STATE,
582*4882a593Smuzhiyun 	.ack_base		= AXP20X_IRQ1_STATE,
583*4882a593Smuzhiyun 	.mask_base		= AXP20X_IRQ1_EN,
584*4882a593Smuzhiyun 	.mask_invert		= true,
585*4882a593Smuzhiyun 	.init_ack_masked	= true,
586*4882a593Smuzhiyun 	.irqs			= axp809_regmap_irqs,
587*4882a593Smuzhiyun 	.num_irqs		= ARRAY_SIZE(axp809_regmap_irqs),
588*4882a593Smuzhiyun 	.num_regs		= 5,
589*4882a593Smuzhiyun };
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun static const struct mfd_cell axp20x_cells[] = {
592*4882a593Smuzhiyun 	{
593*4882a593Smuzhiyun 		.name		= "axp20x-gpio",
594*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp209-gpio",
595*4882a593Smuzhiyun 	}, {
596*4882a593Smuzhiyun 		.name		= "axp20x-pek",
597*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_pek_resources),
598*4882a593Smuzhiyun 		.resources	= axp20x_pek_resources,
599*4882a593Smuzhiyun 	}, {
600*4882a593Smuzhiyun 		.name		= "axp20x-regulator",
601*4882a593Smuzhiyun 	}, {
602*4882a593Smuzhiyun 		.name		= "axp20x-adc",
603*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp209-adc",
604*4882a593Smuzhiyun 	}, {
605*4882a593Smuzhiyun 		.name		= "axp20x-battery-power-supply",
606*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp209-battery-power-supply",
607*4882a593Smuzhiyun 	}, {
608*4882a593Smuzhiyun 		.name		= "axp20x-ac-power-supply",
609*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp202-ac-power-supply",
610*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_ac_power_supply_resources),
611*4882a593Smuzhiyun 		.resources	= axp20x_ac_power_supply_resources,
612*4882a593Smuzhiyun 	}, {
613*4882a593Smuzhiyun 		.name		= "axp20x-usb-power-supply",
614*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp202-usb-power-supply",
615*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_usb_power_supply_resources),
616*4882a593Smuzhiyun 		.resources	= axp20x_usb_power_supply_resources,
617*4882a593Smuzhiyun 	},
618*4882a593Smuzhiyun };
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun static const struct mfd_cell axp221_cells[] = {
621*4882a593Smuzhiyun 	{
622*4882a593Smuzhiyun 		.name		= "axp221-pek",
623*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp22x_pek_resources),
624*4882a593Smuzhiyun 		.resources	= axp22x_pek_resources,
625*4882a593Smuzhiyun 	}, {
626*4882a593Smuzhiyun 		.name		= "axp20x-regulator",
627*4882a593Smuzhiyun 	}, {
628*4882a593Smuzhiyun 		.name		= "axp22x-adc",
629*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-adc",
630*4882a593Smuzhiyun 	}, {
631*4882a593Smuzhiyun 		.name		= "axp20x-ac-power-supply",
632*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-ac-power-supply",
633*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_ac_power_supply_resources),
634*4882a593Smuzhiyun 		.resources	= axp20x_ac_power_supply_resources,
635*4882a593Smuzhiyun 	}, {
636*4882a593Smuzhiyun 		.name		= "axp20x-battery-power-supply",
637*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-battery-power-supply",
638*4882a593Smuzhiyun 	}, {
639*4882a593Smuzhiyun 		.name		= "axp20x-usb-power-supply",
640*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-usb-power-supply",
641*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp22x_usb_power_supply_resources),
642*4882a593Smuzhiyun 		.resources	= axp22x_usb_power_supply_resources,
643*4882a593Smuzhiyun 	},
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun static const struct mfd_cell axp223_cells[] = {
647*4882a593Smuzhiyun 	{
648*4882a593Smuzhiyun 		.name		= "axp221-pek",
649*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp22x_pek_resources),
650*4882a593Smuzhiyun 		.resources	= axp22x_pek_resources,
651*4882a593Smuzhiyun 	}, {
652*4882a593Smuzhiyun 		.name		= "axp22x-adc",
653*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-adc",
654*4882a593Smuzhiyun 	}, {
655*4882a593Smuzhiyun 		.name		= "axp20x-battery-power-supply",
656*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-battery-power-supply",
657*4882a593Smuzhiyun 	}, {
658*4882a593Smuzhiyun 		.name		= "axp20x-regulator",
659*4882a593Smuzhiyun 	}, {
660*4882a593Smuzhiyun 		.name		= "axp20x-ac-power-supply",
661*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp221-ac-power-supply",
662*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_ac_power_supply_resources),
663*4882a593Smuzhiyun 		.resources	= axp20x_ac_power_supply_resources,
664*4882a593Smuzhiyun 	}, {
665*4882a593Smuzhiyun 		.name		= "axp20x-usb-power-supply",
666*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp223-usb-power-supply",
667*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp22x_usb_power_supply_resources),
668*4882a593Smuzhiyun 		.resources	= axp22x_usb_power_supply_resources,
669*4882a593Smuzhiyun 	},
670*4882a593Smuzhiyun };
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun static const struct mfd_cell axp152_cells[] = {
673*4882a593Smuzhiyun 	{
674*4882a593Smuzhiyun 		.name		= "axp20x-pek",
675*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp152_pek_resources),
676*4882a593Smuzhiyun 		.resources	= axp152_pek_resources,
677*4882a593Smuzhiyun 	},
678*4882a593Smuzhiyun };
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun static const struct resource axp288_adc_resources[] = {
681*4882a593Smuzhiyun 	DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"),
682*4882a593Smuzhiyun };
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun static const struct resource axp288_extcon_resources[] = {
685*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_VBUS_FALL),
686*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_VBUS_RISE),
687*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_MV_CHNG),
688*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_BC_USB_CHNG),
689*4882a593Smuzhiyun };
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun static const struct resource axp288_charger_resources[] = {
692*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_OV),
693*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_DONE),
694*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_CHARGING),
695*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_SAFE_QUIT),
696*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_SAFE_ENTER),
697*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_QCBTU),
698*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_CBTU),
699*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_QCBTO),
700*4882a593Smuzhiyun 	DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
701*4882a593Smuzhiyun };
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun static const struct mfd_cell axp288_cells[] = {
704*4882a593Smuzhiyun 	{
705*4882a593Smuzhiyun 		.name		= "axp288_adc",
706*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp288_adc_resources),
707*4882a593Smuzhiyun 		.resources	= axp288_adc_resources,
708*4882a593Smuzhiyun 	}, {
709*4882a593Smuzhiyun 		.name		= "axp288_extcon",
710*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp288_extcon_resources),
711*4882a593Smuzhiyun 		.resources	= axp288_extcon_resources,
712*4882a593Smuzhiyun 	}, {
713*4882a593Smuzhiyun 		.name		= "axp288_charger",
714*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp288_charger_resources),
715*4882a593Smuzhiyun 		.resources	= axp288_charger_resources,
716*4882a593Smuzhiyun 	}, {
717*4882a593Smuzhiyun 		.name		= "axp288_fuel_gauge",
718*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp288_fuel_gauge_resources),
719*4882a593Smuzhiyun 		.resources	= axp288_fuel_gauge_resources,
720*4882a593Smuzhiyun 	}, {
721*4882a593Smuzhiyun 		.name		= "axp221-pek",
722*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp288_power_button_resources),
723*4882a593Smuzhiyun 		.resources	= axp288_power_button_resources,
724*4882a593Smuzhiyun 	}, {
725*4882a593Smuzhiyun 		.name		= "axp288_pmic_acpi",
726*4882a593Smuzhiyun 	},
727*4882a593Smuzhiyun };
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun static const struct mfd_cell axp803_cells[] = {
730*4882a593Smuzhiyun 	{
731*4882a593Smuzhiyun 		.name		= "axp221-pek",
732*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp803_pek_resources),
733*4882a593Smuzhiyun 		.resources	= axp803_pek_resources,
734*4882a593Smuzhiyun 	}, {
735*4882a593Smuzhiyun 		.name		= "axp20x-gpio",
736*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-gpio",
737*4882a593Smuzhiyun 	}, {
738*4882a593Smuzhiyun 		.name		= "axp813-adc",
739*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-adc",
740*4882a593Smuzhiyun 	}, {
741*4882a593Smuzhiyun 		.name		= "axp20x-battery-power-supply",
742*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-battery-power-supply",
743*4882a593Smuzhiyun 	}, {
744*4882a593Smuzhiyun 		.name		= "axp20x-ac-power-supply",
745*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-ac-power-supply",
746*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_ac_power_supply_resources),
747*4882a593Smuzhiyun 		.resources	= axp20x_ac_power_supply_resources,
748*4882a593Smuzhiyun 	}, {
749*4882a593Smuzhiyun 		.name		= "axp20x-usb-power-supply",
750*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp803_usb_power_supply_resources),
751*4882a593Smuzhiyun 		.resources	= axp803_usb_power_supply_resources,
752*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-usb-power-supply",
753*4882a593Smuzhiyun 	},
754*4882a593Smuzhiyun 	{	.name		= "axp20x-regulator" },
755*4882a593Smuzhiyun };
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun static const struct mfd_cell axp806_self_working_cells[] = {
758*4882a593Smuzhiyun 	{
759*4882a593Smuzhiyun 		.name		= "axp221-pek",
760*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp806_pek_resources),
761*4882a593Smuzhiyun 		.resources	= axp806_pek_resources,
762*4882a593Smuzhiyun 	},
763*4882a593Smuzhiyun 	{	.name		= "axp20x-regulator" },
764*4882a593Smuzhiyun };
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun static const struct mfd_cell axp806_cells[] = {
767*4882a593Smuzhiyun 	{
768*4882a593Smuzhiyun 		.id		= 2,
769*4882a593Smuzhiyun 		.name		= "axp20x-regulator",
770*4882a593Smuzhiyun 	},
771*4882a593Smuzhiyun };
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun static const struct mfd_cell axp809_cells[] = {
774*4882a593Smuzhiyun 	{
775*4882a593Smuzhiyun 		.name		= "axp221-pek",
776*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp809_pek_resources),
777*4882a593Smuzhiyun 		.resources	= axp809_pek_resources,
778*4882a593Smuzhiyun 	}, {
779*4882a593Smuzhiyun 		.id		= 1,
780*4882a593Smuzhiyun 		.name		= "axp20x-regulator",
781*4882a593Smuzhiyun 	},
782*4882a593Smuzhiyun };
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun static const struct mfd_cell axp813_cells[] = {
785*4882a593Smuzhiyun 	{
786*4882a593Smuzhiyun 		.name		= "axp221-pek",
787*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp803_pek_resources),
788*4882a593Smuzhiyun 		.resources	= axp803_pek_resources,
789*4882a593Smuzhiyun 	}, {
790*4882a593Smuzhiyun 		.name		= "axp20x-regulator",
791*4882a593Smuzhiyun 	}, {
792*4882a593Smuzhiyun 		.name		= "axp20x-gpio",
793*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-gpio",
794*4882a593Smuzhiyun 	}, {
795*4882a593Smuzhiyun 		.name		= "axp813-adc",
796*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-adc",
797*4882a593Smuzhiyun 	}, {
798*4882a593Smuzhiyun 		.name		= "axp20x-battery-power-supply",
799*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-battery-power-supply",
800*4882a593Smuzhiyun 	}, {
801*4882a593Smuzhiyun 		.name		= "axp20x-ac-power-supply",
802*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-ac-power-supply",
803*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp20x_ac_power_supply_resources),
804*4882a593Smuzhiyun 		.resources	= axp20x_ac_power_supply_resources,
805*4882a593Smuzhiyun 	}, {
806*4882a593Smuzhiyun 		.name		= "axp20x-usb-power-supply",
807*4882a593Smuzhiyun 		.num_resources	= ARRAY_SIZE(axp803_usb_power_supply_resources),
808*4882a593Smuzhiyun 		.resources	= axp803_usb_power_supply_resources,
809*4882a593Smuzhiyun 		.of_compatible	= "x-powers,axp813-usb-power-supply",
810*4882a593Smuzhiyun 	},
811*4882a593Smuzhiyun };
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun static struct axp20x_dev *axp20x_pm_power_off;
axp20x_power_off(void)814*4882a593Smuzhiyun static void axp20x_power_off(void)
815*4882a593Smuzhiyun {
816*4882a593Smuzhiyun 	if (axp20x_pm_power_off->variant == AXP288_ID)
817*4882a593Smuzhiyun 		return;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
820*4882a593Smuzhiyun 		     AXP20X_OFF);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	/* Give capacitors etc. time to drain to avoid kernel panic msg. */
823*4882a593Smuzhiyun 	msleep(500);
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun 
axp20x_match_device(struct axp20x_dev * axp20x)826*4882a593Smuzhiyun int axp20x_match_device(struct axp20x_dev *axp20x)
827*4882a593Smuzhiyun {
828*4882a593Smuzhiyun 	struct device *dev = axp20x->dev;
829*4882a593Smuzhiyun 	const struct acpi_device_id *acpi_id;
830*4882a593Smuzhiyun 	const struct of_device_id *of_id;
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 	if (dev->of_node) {
833*4882a593Smuzhiyun 		of_id = of_match_device(dev->driver->of_match_table, dev);
834*4882a593Smuzhiyun 		if (!of_id) {
835*4882a593Smuzhiyun 			dev_err(dev, "Unable to match OF ID\n");
836*4882a593Smuzhiyun 			return -ENODEV;
837*4882a593Smuzhiyun 		}
838*4882a593Smuzhiyun 		axp20x->variant = (long)of_id->data;
839*4882a593Smuzhiyun 	} else {
840*4882a593Smuzhiyun 		acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
841*4882a593Smuzhiyun 		if (!acpi_id || !acpi_id->driver_data) {
842*4882a593Smuzhiyun 			dev_err(dev, "Unable to match ACPI ID and data\n");
843*4882a593Smuzhiyun 			return -ENODEV;
844*4882a593Smuzhiyun 		}
845*4882a593Smuzhiyun 		axp20x->variant = (long)acpi_id->driver_data;
846*4882a593Smuzhiyun 	}
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun 	switch (axp20x->variant) {
849*4882a593Smuzhiyun 	case AXP152_ID:
850*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
851*4882a593Smuzhiyun 		axp20x->cells = axp152_cells;
852*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp152_regmap_config;
853*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
854*4882a593Smuzhiyun 		break;
855*4882a593Smuzhiyun 	case AXP202_ID:
856*4882a593Smuzhiyun 	case AXP209_ID:
857*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
858*4882a593Smuzhiyun 		axp20x->cells = axp20x_cells;
859*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp20x_regmap_config;
860*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
861*4882a593Smuzhiyun 		break;
862*4882a593Smuzhiyun 	case AXP221_ID:
863*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
864*4882a593Smuzhiyun 		axp20x->cells = axp221_cells;
865*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp22x_regmap_config;
866*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
867*4882a593Smuzhiyun 		break;
868*4882a593Smuzhiyun 	case AXP223_ID:
869*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
870*4882a593Smuzhiyun 		axp20x->cells = axp223_cells;
871*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp22x_regmap_config;
872*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
873*4882a593Smuzhiyun 		break;
874*4882a593Smuzhiyun 	case AXP288_ID:
875*4882a593Smuzhiyun 		axp20x->cells = axp288_cells;
876*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
877*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp288_regmap_config;
878*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
879*4882a593Smuzhiyun 		axp20x->irq_flags = IRQF_TRIGGER_LOW;
880*4882a593Smuzhiyun 		break;
881*4882a593Smuzhiyun 	case AXP803_ID:
882*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
883*4882a593Smuzhiyun 		axp20x->cells = axp803_cells;
884*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp288_regmap_config;
885*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
886*4882a593Smuzhiyun 		break;
887*4882a593Smuzhiyun 	case AXP806_ID:
888*4882a593Smuzhiyun 		if (of_property_read_bool(axp20x->dev->of_node,
889*4882a593Smuzhiyun 					  "x-powers,self-working-mode")) {
890*4882a593Smuzhiyun 			axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells);
891*4882a593Smuzhiyun 			axp20x->cells = axp806_self_working_cells;
892*4882a593Smuzhiyun 		} else {
893*4882a593Smuzhiyun 			axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
894*4882a593Smuzhiyun 			axp20x->cells = axp806_cells;
895*4882a593Smuzhiyun 		}
896*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp806_regmap_config;
897*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
898*4882a593Smuzhiyun 		break;
899*4882a593Smuzhiyun 	case AXP809_ID:
900*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
901*4882a593Smuzhiyun 		axp20x->cells = axp809_cells;
902*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp22x_regmap_config;
903*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
904*4882a593Smuzhiyun 		break;
905*4882a593Smuzhiyun 	case AXP813_ID:
906*4882a593Smuzhiyun 		axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
907*4882a593Smuzhiyun 		axp20x->cells = axp813_cells;
908*4882a593Smuzhiyun 		axp20x->regmap_cfg = &axp288_regmap_config;
909*4882a593Smuzhiyun 		/*
910*4882a593Smuzhiyun 		 * The IRQ table given in the datasheet is incorrect.
911*4882a593Smuzhiyun 		 * In IRQ enable/status registers 1, there are separate
912*4882a593Smuzhiyun 		 * IRQs for ACIN and VBUS, instead of bits [7:5] being
913*4882a593Smuzhiyun 		 * the same as bits [4:2]. So it shares the same IRQs
914*4882a593Smuzhiyun 		 * as the AXP803, rather than the AXP288.
915*4882a593Smuzhiyun 		 */
916*4882a593Smuzhiyun 		axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
917*4882a593Smuzhiyun 		break;
918*4882a593Smuzhiyun 	default:
919*4882a593Smuzhiyun 		dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
920*4882a593Smuzhiyun 		return -EINVAL;
921*4882a593Smuzhiyun 	}
922*4882a593Smuzhiyun 	dev_info(dev, "AXP20x variant %s found\n",
923*4882a593Smuzhiyun 		 axp20x_model_names[axp20x->variant]);
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	return 0;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun EXPORT_SYMBOL(axp20x_match_device);
928*4882a593Smuzhiyun 
axp20x_device_probe(struct axp20x_dev * axp20x)929*4882a593Smuzhiyun int axp20x_device_probe(struct axp20x_dev *axp20x)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun 	int ret;
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun 	/*
934*4882a593Smuzhiyun 	 * The AXP806 supports either master/standalone or slave mode.
935*4882a593Smuzhiyun 	 * Slave mode allows sharing the serial bus, even with multiple
936*4882a593Smuzhiyun 	 * AXP806 which all have the same hardware address.
937*4882a593Smuzhiyun 	 *
938*4882a593Smuzhiyun 	 * This is done with extra "serial interface address extension",
939*4882a593Smuzhiyun 	 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
940*4882a593Smuzhiyun 	 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
941*4882a593Smuzhiyun 	 * 1 bit customizable at the factory, and 1 bit depending on the
942*4882a593Smuzhiyun 	 * state of an external pin. The latter is writable. The device
943*4882a593Smuzhiyun 	 * will only respond to operations to its other registers when
944*4882a593Smuzhiyun 	 * the these device addressing bits (in the upper 4 bits of the
945*4882a593Smuzhiyun 	 * registers) match.
946*4882a593Smuzhiyun 	 *
947*4882a593Smuzhiyun 	 * By default we support an AXP806 chained to an AXP809 in slave
948*4882a593Smuzhiyun 	 * mode. Boards which use an AXP806 in master mode can set the
949*4882a593Smuzhiyun 	 * property "x-powers,master-mode" to override the default.
950*4882a593Smuzhiyun 	 */
951*4882a593Smuzhiyun 	if (axp20x->variant == AXP806_ID) {
952*4882a593Smuzhiyun 		if (of_property_read_bool(axp20x->dev->of_node,
953*4882a593Smuzhiyun 					  "x-powers,master-mode") ||
954*4882a593Smuzhiyun 		    of_property_read_bool(axp20x->dev->of_node,
955*4882a593Smuzhiyun 					  "x-powers,self-working-mode"))
956*4882a593Smuzhiyun 			regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
957*4882a593Smuzhiyun 				     AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
958*4882a593Smuzhiyun 		else
959*4882a593Smuzhiyun 			regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
960*4882a593Smuzhiyun 				     AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
961*4882a593Smuzhiyun 	}
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 	ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
964*4882a593Smuzhiyun 			  IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
965*4882a593Smuzhiyun 			   -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
966*4882a593Smuzhiyun 	if (ret) {
967*4882a593Smuzhiyun 		dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
968*4882a593Smuzhiyun 		return ret;
969*4882a593Smuzhiyun 	}
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
972*4882a593Smuzhiyun 			      axp20x->nr_cells, NULL, 0, NULL);
973*4882a593Smuzhiyun 
974*4882a593Smuzhiyun 	if (ret) {
975*4882a593Smuzhiyun 		dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
976*4882a593Smuzhiyun 		regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
977*4882a593Smuzhiyun 		return ret;
978*4882a593Smuzhiyun 	}
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	if (!pm_power_off) {
981*4882a593Smuzhiyun 		axp20x_pm_power_off = axp20x;
982*4882a593Smuzhiyun 		pm_power_off = axp20x_power_off;
983*4882a593Smuzhiyun 	}
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	dev_info(axp20x->dev, "AXP20X driver loaded\n");
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	return 0;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun EXPORT_SYMBOL(axp20x_device_probe);
990*4882a593Smuzhiyun 
axp20x_device_remove(struct axp20x_dev * axp20x)991*4882a593Smuzhiyun int axp20x_device_remove(struct axp20x_dev *axp20x)
992*4882a593Smuzhiyun {
993*4882a593Smuzhiyun 	if (axp20x == axp20x_pm_power_off) {
994*4882a593Smuzhiyun 		axp20x_pm_power_off = NULL;
995*4882a593Smuzhiyun 		pm_power_off = NULL;
996*4882a593Smuzhiyun 	}
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	mfd_remove_devices(axp20x->dev);
999*4882a593Smuzhiyun 	regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
1000*4882a593Smuzhiyun 
1001*4882a593Smuzhiyun 	return 0;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun EXPORT_SYMBOL(axp20x_device_remove);
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
1006*4882a593Smuzhiyun MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1007*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1008