1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Core driver for ams AS3722 PMICs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 AMS AG
6*4882a593Smuzhiyun * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Florian Lobmaier <florian.lobmaier@ams.com>
9*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/mfd/core.h>
19*4882a593Smuzhiyun #include <linux/mfd/as3722.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/regmap.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define AS3722_DEVICE_ID 0x0C
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static const struct resource as3722_rtc_resource[] = {
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun .name = "as3722-rtc-alarm",
29*4882a593Smuzhiyun .start = AS3722_IRQ_RTC_ALARM,
30*4882a593Smuzhiyun .end = AS3722_IRQ_RTC_ALARM,
31*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct resource as3722_adc_resource[] = {
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun .name = "as3722-adc",
38*4882a593Smuzhiyun .start = AS3722_IRQ_ADC,
39*4882a593Smuzhiyun .end = AS3722_IRQ_ADC,
40*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
41*4882a593Smuzhiyun },
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static const struct mfd_cell as3722_devs[] = {
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun .name = "as3722-pinctrl",
47*4882a593Smuzhiyun },
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun .name = "as3722-regulator",
50*4882a593Smuzhiyun },
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun .name = "as3722-rtc",
53*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(as3722_rtc_resource),
54*4882a593Smuzhiyun .resources = as3722_rtc_resource,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun .name = "as3722-adc",
58*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(as3722_adc_resource),
59*4882a593Smuzhiyun .resources = as3722_adc_resource,
60*4882a593Smuzhiyun },
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun .name = "as3722-power-off",
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun .name = "as3722-wdt",
66*4882a593Smuzhiyun },
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const struct regmap_irq as3722_irqs[] = {
70*4882a593Smuzhiyun /* INT1 IRQs */
71*4882a593Smuzhiyun [AS3722_IRQ_LID] = {
72*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_LID,
73*4882a593Smuzhiyun },
74*4882a593Smuzhiyun [AS3722_IRQ_ACOK] = {
75*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_ACOK,
76*4882a593Smuzhiyun },
77*4882a593Smuzhiyun [AS3722_IRQ_ENABLE1] = {
78*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_ENABLE1,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun [AS3722_IRQ_OCCUR_ALARM_SD0] = {
81*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun [AS3722_IRQ_ONKEY_LONG_PRESS] = {
84*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
85*4882a593Smuzhiyun },
86*4882a593Smuzhiyun [AS3722_IRQ_ONKEY] = {
87*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_ONKEY,
88*4882a593Smuzhiyun },
89*4882a593Smuzhiyun [AS3722_IRQ_OVTMP] = {
90*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_OVTMP,
91*4882a593Smuzhiyun },
92*4882a593Smuzhiyun [AS3722_IRQ_LOWBAT] = {
93*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK1_LOWBAT,
94*4882a593Smuzhiyun },
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* INT2 IRQs */
97*4882a593Smuzhiyun [AS3722_IRQ_SD0_LV] = {
98*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_SD0_LV,
99*4882a593Smuzhiyun .reg_offset = 1,
100*4882a593Smuzhiyun },
101*4882a593Smuzhiyun [AS3722_IRQ_SD1_LV] = {
102*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_SD1_LV,
103*4882a593Smuzhiyun .reg_offset = 1,
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun [AS3722_IRQ_SD2_LV] = {
106*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_SD2345_LV,
107*4882a593Smuzhiyun .reg_offset = 1,
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun [AS3722_IRQ_PWM1_OV_PROT] = {
110*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_PWM1_OV_PROT,
111*4882a593Smuzhiyun .reg_offset = 1,
112*4882a593Smuzhiyun },
113*4882a593Smuzhiyun [AS3722_IRQ_PWM2_OV_PROT] = {
114*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_PWM2_OV_PROT,
115*4882a593Smuzhiyun .reg_offset = 1,
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun [AS3722_IRQ_ENABLE2] = {
118*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_ENABLE2,
119*4882a593Smuzhiyun .reg_offset = 1,
120*4882a593Smuzhiyun },
121*4882a593Smuzhiyun [AS3722_IRQ_SD6_LV] = {
122*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_SD6_LV,
123*4882a593Smuzhiyun .reg_offset = 1,
124*4882a593Smuzhiyun },
125*4882a593Smuzhiyun [AS3722_IRQ_RTC_REP] = {
126*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK2_RTC_REP,
127*4882a593Smuzhiyun .reg_offset = 1,
128*4882a593Smuzhiyun },
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* INT3 IRQs */
131*4882a593Smuzhiyun [AS3722_IRQ_RTC_ALARM] = {
132*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_RTC_ALARM,
133*4882a593Smuzhiyun .reg_offset = 2,
134*4882a593Smuzhiyun },
135*4882a593Smuzhiyun [AS3722_IRQ_GPIO1] = {
136*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_GPIO1,
137*4882a593Smuzhiyun .reg_offset = 2,
138*4882a593Smuzhiyun },
139*4882a593Smuzhiyun [AS3722_IRQ_GPIO2] = {
140*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_GPIO2,
141*4882a593Smuzhiyun .reg_offset = 2,
142*4882a593Smuzhiyun },
143*4882a593Smuzhiyun [AS3722_IRQ_GPIO3] = {
144*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_GPIO3,
145*4882a593Smuzhiyun .reg_offset = 2,
146*4882a593Smuzhiyun },
147*4882a593Smuzhiyun [AS3722_IRQ_GPIO4] = {
148*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_GPIO4,
149*4882a593Smuzhiyun .reg_offset = 2,
150*4882a593Smuzhiyun },
151*4882a593Smuzhiyun [AS3722_IRQ_GPIO5] = {
152*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_GPIO5,
153*4882a593Smuzhiyun .reg_offset = 2,
154*4882a593Smuzhiyun },
155*4882a593Smuzhiyun [AS3722_IRQ_WATCHDOG] = {
156*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_WATCHDOG,
157*4882a593Smuzhiyun .reg_offset = 2,
158*4882a593Smuzhiyun },
159*4882a593Smuzhiyun [AS3722_IRQ_ENABLE3] = {
160*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK3_ENABLE3,
161*4882a593Smuzhiyun .reg_offset = 2,
162*4882a593Smuzhiyun },
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun /* INT4 IRQs */
165*4882a593Smuzhiyun [AS3722_IRQ_TEMP_SD0_SHUTDOWN] = {
166*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN,
167*4882a593Smuzhiyun .reg_offset = 3,
168*4882a593Smuzhiyun },
169*4882a593Smuzhiyun [AS3722_IRQ_TEMP_SD1_SHUTDOWN] = {
170*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN,
171*4882a593Smuzhiyun .reg_offset = 3,
172*4882a593Smuzhiyun },
173*4882a593Smuzhiyun [AS3722_IRQ_TEMP_SD2_SHUTDOWN] = {
174*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN,
175*4882a593Smuzhiyun .reg_offset = 3,
176*4882a593Smuzhiyun },
177*4882a593Smuzhiyun [AS3722_IRQ_TEMP_SD0_ALARM] = {
178*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM,
179*4882a593Smuzhiyun .reg_offset = 3,
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun [AS3722_IRQ_TEMP_SD1_ALARM] = {
182*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM,
183*4882a593Smuzhiyun .reg_offset = 3,
184*4882a593Smuzhiyun },
185*4882a593Smuzhiyun [AS3722_IRQ_TEMP_SD6_ALARM] = {
186*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM,
187*4882a593Smuzhiyun .reg_offset = 3,
188*4882a593Smuzhiyun },
189*4882a593Smuzhiyun [AS3722_IRQ_OCCUR_ALARM_SD6] = {
190*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6,
191*4882a593Smuzhiyun .reg_offset = 3,
192*4882a593Smuzhiyun },
193*4882a593Smuzhiyun [AS3722_IRQ_ADC] = {
194*4882a593Smuzhiyun .mask = AS3722_INTERRUPT_MASK4_ADC,
195*4882a593Smuzhiyun .reg_offset = 3,
196*4882a593Smuzhiyun },
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static const struct regmap_irq_chip as3722_irq_chip = {
200*4882a593Smuzhiyun .name = "as3722",
201*4882a593Smuzhiyun .irqs = as3722_irqs,
202*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(as3722_irqs),
203*4882a593Smuzhiyun .num_regs = 4,
204*4882a593Smuzhiyun .status_base = AS3722_INTERRUPT_STATUS1_REG,
205*4882a593Smuzhiyun .mask_base = AS3722_INTERRUPT_MASK1_REG,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
as3722_check_device_id(struct as3722 * as3722)208*4882a593Smuzhiyun static int as3722_check_device_id(struct as3722 *as3722)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun u32 val;
211*4882a593Smuzhiyun int ret;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* Check that this is actually a AS3722 */
214*4882a593Smuzhiyun ret = as3722_read(as3722, AS3722_ASIC_ID1_REG, &val);
215*4882a593Smuzhiyun if (ret < 0) {
216*4882a593Smuzhiyun dev_err(as3722->dev, "ASIC_ID1 read failed: %d\n", ret);
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (val != AS3722_DEVICE_ID) {
221*4882a593Smuzhiyun dev_err(as3722->dev, "Device is not AS3722, ID is 0x%x\n", val);
222*4882a593Smuzhiyun return -ENODEV;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun ret = as3722_read(as3722, AS3722_ASIC_ID2_REG, &val);
226*4882a593Smuzhiyun if (ret < 0) {
227*4882a593Smuzhiyun dev_err(as3722->dev, "ASIC_ID2 read failed: %d\n", ret);
228*4882a593Smuzhiyun return ret;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun dev_info(as3722->dev, "AS3722 with revision 0x%x found\n", val);
232*4882a593Smuzhiyun return 0;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
as3722_configure_pullups(struct as3722 * as3722)235*4882a593Smuzhiyun static int as3722_configure_pullups(struct as3722 *as3722)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun int ret;
238*4882a593Smuzhiyun u32 val = 0;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (as3722->en_intern_int_pullup)
241*4882a593Smuzhiyun val |= AS3722_INT_PULL_UP;
242*4882a593Smuzhiyun if (as3722->en_intern_i2c_pullup)
243*4882a593Smuzhiyun val |= AS3722_I2C_PULL_UP;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun ret = as3722_update_bits(as3722, AS3722_IOVOLTAGE_REG,
246*4882a593Smuzhiyun AS3722_INT_PULL_UP | AS3722_I2C_PULL_UP, val);
247*4882a593Smuzhiyun if (ret < 0)
248*4882a593Smuzhiyun dev_err(as3722->dev, "IOVOLTAGE_REG update failed: %d\n", ret);
249*4882a593Smuzhiyun return ret;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static const struct regmap_range as3722_readable_ranges[] = {
253*4882a593Smuzhiyun regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
254*4882a593Smuzhiyun regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
255*4882a593Smuzhiyun regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_REG_SEQU_MOD3_REG),
256*4882a593Smuzhiyun regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
257*4882a593Smuzhiyun regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
258*4882a593Smuzhiyun regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
259*4882a593Smuzhiyun AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
260*4882a593Smuzhiyun regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
261*4882a593Smuzhiyun regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
262*4882a593Smuzhiyun regmap_reg_range(AS3722_RTC_ACCESS_REG, AS3722_RTC_ACCESS_REG),
263*4882a593Smuzhiyun regmap_reg_range(AS3722_RTC_STATUS_REG, AS3722_TEMP_STATUS_REG),
264*4882a593Smuzhiyun regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC_CONFIGURATION_REG),
265*4882a593Smuzhiyun regmap_reg_range(AS3722_ASIC_ID1_REG, AS3722_ASIC_ID2_REG),
266*4882a593Smuzhiyun regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
267*4882a593Smuzhiyun regmap_reg_range(AS3722_FUSE7_REG, AS3722_FUSE7_REG),
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun static const struct regmap_access_table as3722_readable_table = {
271*4882a593Smuzhiyun .yes_ranges = as3722_readable_ranges,
272*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(as3722_readable_ranges),
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const struct regmap_range as3722_writable_ranges[] = {
276*4882a593Smuzhiyun regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
277*4882a593Smuzhiyun regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
278*4882a593Smuzhiyun regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_GPIO_SIGNAL_OUT_REG),
279*4882a593Smuzhiyun regmap_reg_range(AS3722_REG_SEQU_MOD1_REG, AS3722_REG_SEQU_MOD3_REG),
280*4882a593Smuzhiyun regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
281*4882a593Smuzhiyun regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
282*4882a593Smuzhiyun regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
283*4882a593Smuzhiyun AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
284*4882a593Smuzhiyun regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
285*4882a593Smuzhiyun regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
286*4882a593Smuzhiyun regmap_reg_range(AS3722_INTERRUPT_MASK1_REG, AS3722_TEMP_STATUS_REG),
287*4882a593Smuzhiyun regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC1_CONTROL_REG),
288*4882a593Smuzhiyun regmap_reg_range(AS3722_ADC1_THRESHOLD_HI_MSB_REG,
289*4882a593Smuzhiyun AS3722_ADC_CONFIGURATION_REG),
290*4882a593Smuzhiyun regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun static const struct regmap_access_table as3722_writable_table = {
294*4882a593Smuzhiyun .yes_ranges = as3722_writable_ranges,
295*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(as3722_writable_ranges),
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static const struct regmap_range as3722_cacheable_ranges[] = {
299*4882a593Smuzhiyun regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_LDO11_VOLTAGE_REG),
300*4882a593Smuzhiyun regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_LDOCONTROL1_REG),
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun static const struct regmap_access_table as3722_volatile_table = {
304*4882a593Smuzhiyun .no_ranges = as3722_cacheable_ranges,
305*4882a593Smuzhiyun .n_no_ranges = ARRAY_SIZE(as3722_cacheable_ranges),
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static const struct regmap_config as3722_regmap_config = {
309*4882a593Smuzhiyun .reg_bits = 8,
310*4882a593Smuzhiyun .val_bits = 8,
311*4882a593Smuzhiyun .max_register = AS3722_MAX_REGISTER,
312*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
313*4882a593Smuzhiyun .rd_table = &as3722_readable_table,
314*4882a593Smuzhiyun .wr_table = &as3722_writable_table,
315*4882a593Smuzhiyun .volatile_table = &as3722_volatile_table,
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
as3722_i2c_of_probe(struct i2c_client * i2c,struct as3722 * as3722)318*4882a593Smuzhiyun static int as3722_i2c_of_probe(struct i2c_client *i2c,
319*4882a593Smuzhiyun struct as3722 *as3722)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct device_node *np = i2c->dev.of_node;
322*4882a593Smuzhiyun struct irq_data *irq_data;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun if (!np) {
325*4882a593Smuzhiyun dev_err(&i2c->dev, "Device Tree not found\n");
326*4882a593Smuzhiyun return -EINVAL;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun irq_data = irq_get_irq_data(i2c->irq);
330*4882a593Smuzhiyun if (!irq_data) {
331*4882a593Smuzhiyun dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
332*4882a593Smuzhiyun return -EINVAL;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun as3722->en_intern_int_pullup = of_property_read_bool(np,
336*4882a593Smuzhiyun "ams,enable-internal-int-pullup");
337*4882a593Smuzhiyun as3722->en_intern_i2c_pullup = of_property_read_bool(np,
338*4882a593Smuzhiyun "ams,enable-internal-i2c-pullup");
339*4882a593Smuzhiyun as3722->en_ac_ok_pwr_on = of_property_read_bool(np,
340*4882a593Smuzhiyun "ams,enable-ac-ok-power-on");
341*4882a593Smuzhiyun as3722->irq_flags = irqd_get_trigger_type(irq_data);
342*4882a593Smuzhiyun dev_dbg(&i2c->dev, "IRQ flags are 0x%08lx\n", as3722->irq_flags);
343*4882a593Smuzhiyun return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
as3722_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)346*4882a593Smuzhiyun static int as3722_i2c_probe(struct i2c_client *i2c,
347*4882a593Smuzhiyun const struct i2c_device_id *id)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct as3722 *as3722;
350*4882a593Smuzhiyun unsigned long irq_flags;
351*4882a593Smuzhiyun int ret;
352*4882a593Smuzhiyun u8 val = 0;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun as3722 = devm_kzalloc(&i2c->dev, sizeof(struct as3722), GFP_KERNEL);
355*4882a593Smuzhiyun if (!as3722)
356*4882a593Smuzhiyun return -ENOMEM;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun as3722->dev = &i2c->dev;
359*4882a593Smuzhiyun as3722->chip_irq = i2c->irq;
360*4882a593Smuzhiyun i2c_set_clientdata(i2c, as3722);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun ret = as3722_i2c_of_probe(i2c, as3722);
363*4882a593Smuzhiyun if (ret < 0)
364*4882a593Smuzhiyun return ret;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun as3722->regmap = devm_regmap_init_i2c(i2c, &as3722_regmap_config);
367*4882a593Smuzhiyun if (IS_ERR(as3722->regmap)) {
368*4882a593Smuzhiyun ret = PTR_ERR(as3722->regmap);
369*4882a593Smuzhiyun dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
370*4882a593Smuzhiyun return ret;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun ret = as3722_check_device_id(as3722);
374*4882a593Smuzhiyun if (ret < 0)
375*4882a593Smuzhiyun return ret;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun irq_flags = as3722->irq_flags | IRQF_ONESHOT;
378*4882a593Smuzhiyun ret = devm_regmap_add_irq_chip(as3722->dev, as3722->regmap,
379*4882a593Smuzhiyun as3722->chip_irq,
380*4882a593Smuzhiyun irq_flags, -1, &as3722_irq_chip,
381*4882a593Smuzhiyun &as3722->irq_data);
382*4882a593Smuzhiyun if (ret < 0) {
383*4882a593Smuzhiyun dev_err(as3722->dev, "Failed to add regmap irq: %d\n", ret);
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun ret = as3722_configure_pullups(as3722);
388*4882a593Smuzhiyun if (ret < 0)
389*4882a593Smuzhiyun return ret;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (as3722->en_ac_ok_pwr_on)
392*4882a593Smuzhiyun val = AS3722_CTRL_SEQU1_AC_OK_PWR_ON;
393*4882a593Smuzhiyun ret = as3722_update_bits(as3722, AS3722_CTRL_SEQU1_REG,
394*4882a593Smuzhiyun AS3722_CTRL_SEQU1_AC_OK_PWR_ON, val);
395*4882a593Smuzhiyun if (ret < 0) {
396*4882a593Smuzhiyun dev_err(as3722->dev, "CTRLsequ1 update failed: %d\n", ret);
397*4882a593Smuzhiyun return ret;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun ret = devm_mfd_add_devices(&i2c->dev, -1, as3722_devs,
401*4882a593Smuzhiyun ARRAY_SIZE(as3722_devs), NULL, 0,
402*4882a593Smuzhiyun regmap_irq_get_domain(as3722->irq_data));
403*4882a593Smuzhiyun if (ret) {
404*4882a593Smuzhiyun dev_err(as3722->dev, "Failed to add MFD devices: %d\n", ret);
405*4882a593Smuzhiyun return ret;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun device_init_wakeup(as3722->dev, true);
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun dev_dbg(as3722->dev, "AS3722 core driver initialized successfully\n");
411*4882a593Smuzhiyun return 0;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
as3722_i2c_suspend(struct device * dev)414*4882a593Smuzhiyun static int __maybe_unused as3722_i2c_suspend(struct device *dev)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun struct as3722 *as3722 = dev_get_drvdata(dev);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (device_may_wakeup(dev))
419*4882a593Smuzhiyun enable_irq_wake(as3722->chip_irq);
420*4882a593Smuzhiyun disable_irq(as3722->chip_irq);
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun return 0;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
as3722_i2c_resume(struct device * dev)425*4882a593Smuzhiyun static int __maybe_unused as3722_i2c_resume(struct device *dev)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun struct as3722 *as3722 = dev_get_drvdata(dev);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun enable_irq(as3722->chip_irq);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun if (device_may_wakeup(dev))
432*4882a593Smuzhiyun disable_irq_wake(as3722->chip_irq);
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun return 0;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun static const struct of_device_id as3722_of_match[] = {
438*4882a593Smuzhiyun { .compatible = "ams,as3722", },
439*4882a593Smuzhiyun {},
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, as3722_of_match);
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun static const struct i2c_device_id as3722_i2c_id[] = {
444*4882a593Smuzhiyun { "as3722", 0 },
445*4882a593Smuzhiyun {},
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, as3722_i2c_id);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun static const struct dev_pm_ops as3722_pm_ops = {
450*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(as3722_i2c_suspend, as3722_i2c_resume)
451*4882a593Smuzhiyun };
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun static struct i2c_driver as3722_i2c_driver = {
454*4882a593Smuzhiyun .driver = {
455*4882a593Smuzhiyun .name = "as3722",
456*4882a593Smuzhiyun .of_match_table = as3722_of_match,
457*4882a593Smuzhiyun .pm = &as3722_pm_ops,
458*4882a593Smuzhiyun },
459*4882a593Smuzhiyun .probe = as3722_i2c_probe,
460*4882a593Smuzhiyun .id_table = as3722_i2c_id,
461*4882a593Smuzhiyun };
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun module_i2c_driver(as3722_i2c_driver);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun MODULE_DESCRIPTION("I2C support for AS3722 PMICs");
466*4882a593Smuzhiyun MODULE_AUTHOR("Florian Lobmaier <florian.lobmaier@ams.com>");
467*4882a593Smuzhiyun MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
468*4882a593Smuzhiyun MODULE_LICENSE("GPL");
469